diff --git a/sound/soc/sof/intel/hda-dai.c b/sound/soc/sof/intel/hda-dai.c
index cca873fc86bc05..d5067db0d9f5c6 100644
--- a/sound/soc/sof/intel/hda-dai.c
+++ b/sound/soc/sof/intel/hda-dai.c
@@ -110,5 +110,3 @@ struct snd_soc_dai_driver skl_dai[] = {
 				   SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
 },
 };
-
-
diff --git a/sound/soc/sof/intel/hda-pcm.c b/sound/soc/sof/intel/hda-pcm.c
index 0abb2e5778cae2..5511277985284d 100644
--- a/sound/soc/sof/intel/hda-pcm.c
+++ b/sound/soc/sof/intel/hda-pcm.c
@@ -34,11 +34,11 @@
 #include "../ops.h"
 #include "hda.h"
 
-#define SDnFMT_BASE(x)	(x << 14)
-#define SDnFMT_MULT(x)	((x - 1) << 11)
-#define SDnFMT_DIV(x)	((x - 1) << 8)
-#define SDnFMT_BITS(x)	(x << 4)
-#define SDnFMT_CHAN(x)	(x << 0)
+#define SDnFMT_BASE(x)	((x) << 14)
+#define SDnFMT_MULT(x)	(((x) - 1) << 11)
+#define SDnFMT_DIV(x)	(((x) - 1) << 8)
+#define SDnFMT_BITS(x)	((x) << 4)
+#define SDnFMT_CHAN(x)	((x) << 0)
 
 static inline u32 get_mult_div(struct snd_sof_dev *sdev, int rate)
 {
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index 7f63b454e07844..86ab6a6c3c1a69 100644
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -119,7 +119,7 @@
 #define HDA_DSP_DRSM_BAR			3
 #define HDA_DSP_BAR				4
 
-#define SRAM_WINDOW_OFFSET(x)			(0x80000 + x * 0x20000)
+#define SRAM_WINDOW_OFFSET(x)			(0x80000 + (x) * 0x20000)
 
 #define HDA_DSP_MBOX_OFFSET			SRAM_WINDOW_OFFSET(0)
 
@@ -266,7 +266,7 @@
  * Mask for a given number of cores
  * nc = number of supported cores
  */
-#define SOF_DSP_CORES_MASK(nc)	GENMASK((nc - 1), 0)
+#define SOF_DSP_CORES_MASK(nc)	GENMASK(((nc) - 1), 0)
 
 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
 #define CNL_DSP_IPC_BASE		0xc0
diff --git a/sound/soc/sof/intel/shim.h b/sound/soc/sof/intel/shim.h
index 512441387b1e32..b6481fc65b2de7 100644
--- a/sound/soc/sof/intel/shim.h
+++ b/sound/soc/sof/intel/shim.h
@@ -46,7 +46,7 @@
 #define SHIM_CSR_RST		(0x1 << 1)
 #define SHIM_CSR_SBCS0		(0x1 << 2)
 #define SHIM_CSR_SBCS1		(0x1 << 3)
-#define SHIM_CSR_DCS(x)		(x << 4)
+#define SHIM_CSR_DCS(x)		((x) << 4)
 #define SHIM_CSR_DCS_MASK	(0x7 << 4)
 #define SHIM_CSR_STALL		(0x1 << 10)
 #define SHIM_CSR_S0IOCS		(0x1 << 21)
@@ -95,7 +95,7 @@
 #define SHIM_BYT_IPCD_BUSY	((u64)0x1 << 63)
 
 /* CLKCTL */
-#define SHIM_CLKCTL_SMOS(x)	(x << 24)
+#define SHIM_CLKCTL_SMOS(x)	((x) << 24)
 #define SHIM_CLKCTL_MASK	(3 << 24)
 #define SHIM_CLKCTL_DCPLCG	BIT(18)
 #define SHIM_CLKCTL_SCOE1	BIT(17)
@@ -106,11 +106,11 @@
 #define SHIM_CSR2_SDFD_SSP1	BIT(2)
 
 /* LTRC */
-#define SHIM_LTRC_VAL(x)	(x << 0)
+#define SHIM_LTRC_VAL(x)	((x) << 0)
 
 /* HMDC */
-#define SHIM_HMDC_HDDA0(x)	(x << 0)
-#define SHIM_HMDC_HDDA1(x)	(x << 7)
+#define SHIM_HMDC_HDDA0(x)	((x) << 0)
+#define SHIM_HMDC_HDDA1(x)	((x) << 7)
 #define SHIM_HMDC_HDDA_E0_CH0	1
 #define SHIM_HMDC_HDDA_E0_CH1	2
 #define SHIM_HMDC_HDDA_E0_CH2	4