|
| 1 | +# RUN: llc -verify-machineinstrs -mtriple aarch64--- \ |
| 2 | +# RUN: -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - \ |
| 3 | +# RUN: | FileCheck %s |
| 4 | +... |
| 5 | +--- |
| 6 | +name: test_v4f16.atan2 |
| 7 | +alignment: 4 |
| 8 | +tracksRegLiveness: true |
| 9 | +registers: |
| 10 | + - { id: 0, class: _ } |
| 11 | + - { id: 1, class: _ } |
| 12 | +body: | |
| 13 | + bb.0: |
| 14 | + liveins: $d0, $d1 |
| 15 | + ; CHECK-LABEL: name: test_v4f16.atan2 |
| 16 | + ; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>) |
| 17 | + ; CHECK: [[V5:%[0-9]+]]:_(s16), [[V6:%[0-9]+]]:_(s16), [[V7:%[0-9]+]]:_(s16), [[V8:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>) |
| 18 | +
|
| 19 | + ; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16) |
| 20 | + ; CHECK-DAG: [[V5_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V5]](s16) |
| 21 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 22 | + ; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32) |
| 23 | + ; CHECK-NEXT: $s1 = COPY [[V5_S32]](s32) |
| 24 | + ; CHECK-NEXT: BL &atan2f |
| 25 | + ; CHECK-NEXT: ADJCALLSTACKUP |
| 26 | + ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0 |
| 27 | + ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32) |
| 28 | +
|
| 29 | + ; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16) |
| 30 | + ; CHECK-DAG: [[V6_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V6]](s16) |
| 31 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 32 | + ; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32) |
| 33 | + ; CHECK-NEXT: $s1 = COPY [[V6_S32]](s32) |
| 34 | + ; CHECK-NEXT: BL &atan2f |
| 35 | + ; CHECK-NEXT: ADJCALLSTACKUP |
| 36 | + ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0 |
| 37 | + ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32) |
| 38 | +
|
| 39 | + ; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16) |
| 40 | + ; CHECK-DAG: [[V7_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V7]](s16) |
| 41 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 42 | + ; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32) |
| 43 | + ; CHECK-NEXT: $s1 = COPY [[V7_S32]](s32) |
| 44 | + ; CHECK-NEXT: BL &atan2f |
| 45 | + ; CHECK-NEXT: ADJCALLSTACKUP |
| 46 | + ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0 |
| 47 | + ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32) |
| 48 | +
|
| 49 | + ; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16) |
| 50 | + ; CHECK-DAG: [[V8_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V8]](s16) |
| 51 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 52 | + ; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32) |
| 53 | + ; CHECK-NEXT: $s1 = COPY [[V8_S32]](s32) |
| 54 | + ; CHECK-NEXT: BL &atan2f |
| 55 | + ; CHECK-NEXT: ADJCALLSTACKUP |
| 56 | + ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0 |
| 57 | + ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32) |
| 58 | +
|
| 59 | + ; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16) |
| 60 | +
|
| 61 | + %0:_(<4 x s16>) = COPY $d0 |
| 62 | + %1:_(<4 x s16>) = COPY $d1 |
| 63 | + %2:_(<4 x s16>) = G_FATAN2 %0, %1 |
| 64 | + $d0 = COPY %2(<4 x s16>) |
| 65 | + RET_ReallyLR implicit $d0 |
| 66 | +
|
| 67 | +... |
| 68 | +--- |
| 69 | +name: test_v8f16.atan2 |
| 70 | +alignment: 4 |
| 71 | +tracksRegLiveness: true |
| 72 | +registers: |
| 73 | + - { id: 0, class: _ } |
| 74 | + - { id: 1, class: _ } |
| 75 | +body: | |
| 76 | + bb.0: |
| 77 | + liveins: $q0, $q1 |
| 78 | +
|
| 79 | + ; CHECK-LABEL: name: test_v8f16.atan2 |
| 80 | +
|
| 81 | + ; This is big, so let's just check for the 8 calls to atan2f, the the |
| 82 | + ; G_UNMERGE_VALUES, and the G_BUILD_VECTOR. The other instructions ought |
| 83 | + ; to be covered by the other tests. |
| 84 | +
|
| 85 | + ; CHECK: G_UNMERGE_VALUES |
| 86 | + ; CHECK: BL &atan2f |
| 87 | + ; CHECK: BL &atan2f |
| 88 | + ; CHECK: BL &atan2f |
| 89 | + ; CHECK: BL &atan2f |
| 90 | + ; CHECK: BL &atan2f |
| 91 | + ; CHECK: BL &atan2f |
| 92 | + ; CHECK: BL &atan2f |
| 93 | + ; CHECK: BL &atan2f |
| 94 | + ; CHECK: G_BUILD_VECTOR |
| 95 | +
|
| 96 | + %0:_(<8 x s16>) = COPY $q0 |
| 97 | + %1:_(<8 x s16>) = COPY $q1 |
| 98 | + %2:_(<8 x s16>) = G_FATAN2 %0, %1 |
| 99 | + $q0 = COPY %2(<8 x s16>) |
| 100 | + RET_ReallyLR implicit $q0 |
| 101 | +
|
| 102 | +... |
| 103 | +--- |
| 104 | +name: test_v2f32.atan2 |
| 105 | +alignment: 4 |
| 106 | +tracksRegLiveness: true |
| 107 | +registers: |
| 108 | + - { id: 0, class: _ } |
| 109 | + - { id: 1, class: _ } |
| 110 | +body: | |
| 111 | + bb.0: |
| 112 | + liveins: $d0, $d1 |
| 113 | +
|
| 114 | + ; CHECK-LABEL: name: test_v2f32.atan2 |
| 115 | + ; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s32>) |
| 116 | + ; CHECK: [[V3:%[0-9]+]]:_(s32), [[V4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s32>) |
| 117 | +
|
| 118 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 119 | + ; CHECK-DAG: $s0 = COPY [[V1]](s32) |
| 120 | + ; CHECK-DAG: $s1 = COPY [[V3]](s32) |
| 121 | + ; CHECK: BL &atan2f |
| 122 | + ; CHECK: ADJCALLSTACKUP |
| 123 | + ; CHECK: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0 |
| 124 | +
|
| 125 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 126 | + ; CHECK-DAG: $s0 = COPY [[V2]](s32) |
| 127 | + ; CHECK-DAG: $s1 = COPY [[V4]](s32) |
| 128 | + ; CHECK: BL &atan2f |
| 129 | + ; CHECK: ADJCALLSTACKUP |
| 130 | + ; CHECK: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0 |
| 131 | +
|
| 132 | + ; CHECK: %2:_(<2 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32) |
| 133 | +
|
| 134 | + %0:_(<2 x s32>) = COPY $d0 |
| 135 | + %1:_(<2 x s32>) = COPY $d1 |
| 136 | + %2:_(<2 x s32>) = G_FATAN2 %0, %1 |
| 137 | + $d0 = COPY %2(<2 x s32>) |
| 138 | + RET_ReallyLR implicit $d0 |
| 139 | +
|
| 140 | +... |
| 141 | +--- |
| 142 | +name: test_v4f32.atan2 |
| 143 | +alignment: 4 |
| 144 | +tracksRegLiveness: true |
| 145 | +registers: |
| 146 | + - { id: 0, class: _ } |
| 147 | + - { id: 1, class: _ } |
| 148 | +body: | |
| 149 | + bb.0: |
| 150 | + liveins: $q0, $q1 |
| 151 | + ; CHECK-LABEL: name: test_v4f32.atan2 |
| 152 | + ; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32), [[V3:%[0-9]+]]:_(s32), [[V4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s32>) |
| 153 | + ; CHECK: [[V5:%[0-9]+]]:_(s32), [[V6:%[0-9]+]]:_(s32), [[V7:%[0-9]+]]:_(s32), [[V8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s32>) |
| 154 | +
|
| 155 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 156 | + ; CHECK-DAG: $s0 = COPY [[V1]](s32) |
| 157 | + ; CHECK-DAG: $s1 = COPY [[V5]](s32) |
| 158 | + ; CHECK: BL &atan2f |
| 159 | + ; CHECK: ADJCALLSTACKUP |
| 160 | + ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0 |
| 161 | +
|
| 162 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 163 | + ; CHECK-DAG: $s0 = COPY [[V2]](s32) |
| 164 | + ; CHECK-DAG: $s1 = COPY [[V6]](s32) |
| 165 | + ; CHECK: BL &atan2f |
| 166 | + ; CHECK: ADJCALLSTACKUP |
| 167 | + ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0 |
| 168 | +
|
| 169 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 170 | + ; CHECK-DAG: $s0 = COPY [[V3]](s32) |
| 171 | + ; CHECK-DAG: $s1 = COPY [[V7]](s32) |
| 172 | + ; CHECK: BL &atan2f |
| 173 | + ; CHECK: ADJCALLSTACKUP |
| 174 | + ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s32) = COPY $s0 |
| 175 | +
|
| 176 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 177 | + ; CHECK-DAG: $s0 = COPY [[V4]](s32) |
| 178 | + ; CHECK-DAG: $s1 = COPY [[V8]](s32) |
| 179 | + ; CHECK: BL &atan2f |
| 180 | + ; CHECK: ADJCALLSTACKUP |
| 181 | + ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s32) = COPY $s0 |
| 182 | +
|
| 183 | + ; CHECK: %2:_(<4 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32), [[ELT3]](s32), [[ELT4]](s32) |
| 184 | +
|
| 185 | + %0:_(<4 x s32>) = COPY $q0 |
| 186 | + %1:_(<4 x s32>) = COPY $q1 |
| 187 | + %2:_(<4 x s32>) = G_FATAN2 %0, %1 |
| 188 | + $q0 = COPY %2(<4 x s32>) |
| 189 | + RET_ReallyLR implicit $q0 |
| 190 | +
|
| 191 | +... |
| 192 | +--- |
| 193 | +name: test_v2f64.atan2 |
| 194 | +alignment: 4 |
| 195 | +tracksRegLiveness: true |
| 196 | +registers: |
| 197 | + - { id: 0, class: _ } |
| 198 | + - { id: 1, class: _ } |
| 199 | +body: | |
| 200 | + bb.0: |
| 201 | + liveins: $q0, $q1 |
| 202 | +
|
| 203 | + ; CHECK-LABEL: name: test_v2f64.atan2 |
| 204 | + ; CHECK: [[V1:%[0-9]+]]:_(s64), [[V2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s64>) |
| 205 | + ; CHECK: [[V3:%[0-9]+]]:_(s64), [[V4:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s64>) |
| 206 | +
|
| 207 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 208 | + ; CHECK-DAG: $d0 = COPY [[V1]](s64) |
| 209 | + ; CHECK-DAG: $d1 = COPY [[V3]](s64) |
| 210 | + ; CHECK: BL &atan2 |
| 211 | + ; CHECK: ADJCALLSTACKUP |
| 212 | + ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s64) = COPY $d0 |
| 213 | +
|
| 214 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 215 | + ; CHECK-DAG: $d0 = COPY [[V2]](s64) |
| 216 | + ; CHECK-DAG: $d1 = COPY [[V4]](s64) |
| 217 | + ; CHECK: BL &atan2 |
| 218 | + ; CHECK: ADJCALLSTACKUP |
| 219 | + ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s64) = COPY $d0 |
| 220 | +
|
| 221 | + ; CHECK: %2:_(<2 x s64>) = G_BUILD_VECTOR [[ELT1]](s64), [[ELT2]](s64) |
| 222 | +
|
| 223 | + %0:_(<2 x s64>) = COPY $q0 |
| 224 | + %1:_(<2 x s64>) = COPY $q1 |
| 225 | + %2:_(<2 x s64>) = G_FATAN2 %0, %1 |
| 226 | + $q0 = COPY %2(<2 x s64>) |
| 227 | + RET_ReallyLR implicit $q0 |
| 228 | +
|
| 229 | +... |
| 230 | +--- |
| 231 | +name: test_atan2_half |
| 232 | +alignment: 4 |
| 233 | +tracksRegLiveness: true |
| 234 | +registers: |
| 235 | + - { id: 0, class: _ } |
| 236 | + - { id: 1, class: _ } |
| 237 | +body: | |
| 238 | + bb.0: |
| 239 | + liveins: $h0, $h1 |
| 240 | + ; CHECK-LABEL: name: test_atan2_half |
| 241 | + ; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16) |
| 242 | + ; CHECK: [[REG2:%[0-9]+]]:_(s32) = G_FPEXT %1(s16) |
| 243 | + ; CHECK-NEXT: ADJCALLSTACKDOWN |
| 244 | + ; CHECK-NEXT: $s0 = COPY [[REG1]](s32) |
| 245 | + ; CHECK-NEXT: $s1 = COPY [[REG2]](s32) |
| 246 | + ; CHECK-NEXT: BL &atan2f |
| 247 | + ; CHECK: ADJCALLSTACKUP |
| 248 | + ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0 |
| 249 | + ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32) |
| 250 | +
|
| 251 | + %0:_(s16) = COPY $h0 |
| 252 | + %1:_(s16) = COPY $h1 |
| 253 | + %2:_(s16) = G_FATAN2 %0, %1 |
| 254 | + $h0 = COPY %2(s16) |
| 255 | + RET_ReallyLR implicit $h0 |
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