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Simon Moll
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[VP] IR support for vector-predicated integer operations
This patch is part of the integer patch set of the Vector Predication extension (D57504). VP / integer slice / patch #1
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‎llvm/docs/LangRef.rst

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‎llvm/include/llvm/IR/IntrinsicInst.h

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@@ -206,6 +206,48 @@ namespace llvm {
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/// @}
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};
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209+
/// This is the common base class for vector predication intrinsics.
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class VPIntrinsic : public IntrinsicInst {
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public:
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static Optional<int> GetMaskParamPos(Intrinsic::ID IntrinsicID);
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static Optional<int> GetVectorLengthParamPos(Intrinsic::ID IntrinsicID);
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/// The llvm.vp.* intrinsics for this instruction Opcode
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static Intrinsic::ID GetForOpcode(unsigned OC);
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// Whether \p ID is a VP intrinsic ID.
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static bool IsVPIntrinsic(Intrinsic::ID);
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/// \return the mask parameter or nullptr.
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Value *getMaskParam() const;
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/// \return the vector length parameter or nullptr.
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Value *getVectorLengthParam() const;
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/// \return whether the vector length param can be ignored.
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bool canIgnoreVectorLengthParam() const;
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/// \return the static element count (vector number of elements) the vector
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/// length parameter applies to.
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ElementCount getVectorLength() const;
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// Methods for support type inquiry through isa, cast, and dyn_cast:
235+
static bool classof(const IntrinsicInst *I) {
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return IsVPIntrinsic(I->getIntrinsicID());
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}
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static bool classof(const Value *V) {
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return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
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}
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// Equivalent non-predicated opcode
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unsigned getFunctionalOpcode() const {
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return GetFunctionalOpcodeForVP(getIntrinsicID());
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}
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// Equivalent non-predicated opcode
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static unsigned GetFunctionalOpcodeForVP(Intrinsic::ID ID);
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};
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/// This is the common base class for constrained floating point intrinsics.
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class ConstrainedFPIntrinsic : public IntrinsicInst {
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public:

‎llvm/include/llvm/IR/Intrinsics.td

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@@ -27,6 +27,10 @@ class IntrinsicProperty;
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// effects. It may be CSE'd deleted if dead, etc.
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def IntrNoMem : IntrinsicProperty;
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// IntrNoSync - Threads executing the intrinsic will not synchronize using
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// memory or other means.
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def IntrNoSync : IntrinsicProperty;
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// IntrReadMem - This intrinsic only reads from memory. It does not write to
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// memory and has no other side effects. Therefore, it cannot be moved across
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// potentially aliasing stores. However, it can be reordered otherwise and can
@@ -1145,6 +1149,79 @@ def int_is_constant : Intrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem, IntrWil
11451149
def int_ptrmask: Intrinsic<[llvm_anyptr_ty], [llvm_anyptr_ty, llvm_anyint_ty],
11461150
[IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
11471151

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//===---------------- Vector Predication Intrinsics --------------===//
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// Binary operators
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let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn] in {
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def int_vp_add : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_sub : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_mul : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_sdiv : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_udiv : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_srem : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_urem : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_ashr : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_lshr : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_shl : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_or : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
1210+
llvm_i32_ty]>;
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def int_vp_and : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_xor : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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1222+
}
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//===-------------------------- Masked Intrinsics -------------------------===//
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//
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def int_masked_store : Intrinsic<[], [llvm_anyvector_ty,

‎llvm/include/llvm/IR/VPIntrinsics.def

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@@ -0,0 +1,84 @@
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//===-- IR/VPIntrinsics.def - Describes llvm.vp.* Intrinsics -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains descriptions of the various Vector Predication intrinsics.
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// This is used as a central place for enumerating the different instructions
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// and should eventually be the place to put comments about the instructions.
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//
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//===----------------------------------------------------------------------===//
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// NOTE: NO INCLUDE GUARD DESIRED!
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// Provide definitions of macros so that users of this file do not have to
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// define everything to use it...
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//
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#ifndef REGISTER_VP_INTRINSIC
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#define REGISTER_VP_INTRINSIC(VPID, MASKPOS, VLENPOS)
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#endif
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// Map this VP intrinsic to its functional Opcode
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#ifndef HANDLE_VP_TO_OC
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#define HANDLE_VP_TO_OC(VPID, OC)
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#endif
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///// Integer Arithmetic /////
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// llvm.vp.add(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_add, 2, 3)
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HANDLE_VP_TO_OC(vp_add, Add)
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// llvm.vp.and(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_and, 2, 3)
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HANDLE_VP_TO_OC(vp_and, And)
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// llvm.vp.ashr(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_ashr, 2, 3)
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HANDLE_VP_TO_OC(vp_ashr, AShr)
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// llvm.vp.lshr(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_lshr, 2, 3)
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HANDLE_VP_TO_OC(vp_lshr, LShr)
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// llvm.vp.mul(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_mul, 2, 3)
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HANDLE_VP_TO_OC(vp_mul, Mul)
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// llvm.vp.or(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_or, 2, 3)
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HANDLE_VP_TO_OC(vp_or, Or)
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// llvm.vp.sdiv(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_sdiv, 2, 3)
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HANDLE_VP_TO_OC(vp_sdiv, SDiv)
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// llvm.vp.shl(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_shl, 2, 3)
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HANDLE_VP_TO_OC(vp_shl, Shl)
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// llvm.vp.srem(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_srem, 2, 3)
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HANDLE_VP_TO_OC(vp_srem, SRem)
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// llvm.vp.sub(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_sub, 2, 3)
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HANDLE_VP_TO_OC(vp_sub, Sub)
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// llvm.vp.udiv(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_udiv, 2, 3)
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HANDLE_VP_TO_OC(vp_udiv, UDiv)
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// llvm.vp.urem(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_urem, 2, 3)
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HANDLE_VP_TO_OC(vp_urem, URem)
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// llvm.vp.xor(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_xor, 2, 3)
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HANDLE_VP_TO_OC(vp_xor, Xor)
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#undef REGISTER_VP_INTRINSIC
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#undef HANDLE_VP_TO_OC

‎llvm/lib/IR/IntrinsicInst.cpp

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@@ -178,6 +178,119 @@ bool ConstrainedFPIntrinsic::classof(const IntrinsicInst *I) {
178178
}
179179
}
180180

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ElementCount VPIntrinsic::getVectorLength() const {
182+
auto GetVectorLengthOfType = [](const Type *T) -> ElementCount {
183+
auto VT = cast<VectorType>(T);
184+
auto ElemCount = VT->getElementCount();
185+
return ElemCount;
186+
};
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auto VPMask = getMaskParam();
189+
return GetVectorLengthOfType(VPMask->getType());
190+
}
191+
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Value *VPIntrinsic::getMaskParam() const {
193+
auto maskPos = GetMaskParamPos(getIntrinsicID());
194+
if (maskPos)
195+
return getArgOperand(maskPos.getValue());
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return nullptr;
197+
}
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Value *VPIntrinsic::getVectorLengthParam() const {
200+
auto vlenPos = GetVectorLengthParamPos(getIntrinsicID());
201+
if (vlenPos)
202+
return getArgOperand(vlenPos.getValue());
203+
return nullptr;
204+
}
205+
206+
Optional<int> VPIntrinsic::GetMaskParamPos(Intrinsic::ID IntrinsicID) {
207+
switch (IntrinsicID) {
208+
default:
209+
return None;
210+
211+
#define REGISTER_VP_INTRINSIC(VPID, MASKPOS, VLENPOS) \
212+
case Intrinsic::VPID: \
213+
return MASKPOS;
214+
#include "llvm/IR/VPIntrinsics.def"
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}
216+
}
217+
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Optional<int> VPIntrinsic::GetVectorLengthParamPos(Intrinsic::ID IntrinsicID) {
219+
switch (IntrinsicID) {
220+
default:
221+
return None;
222+
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#define REGISTER_VP_INTRINSIC(VPID, MASKPOS, VLENPOS) \
224+
case Intrinsic::VPID: \
225+
return VLENPOS;
226+
#include "llvm/IR/VPIntrinsics.def"
227+
}
228+
}
229+
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bool VPIntrinsic::IsVPIntrinsic(Intrinsic::ID ID) {
231+
switch (ID) {
232+
default:
233+
return false;
234+
235+
#define REGISTER_VP_INTRINSIC(VPID, MASKPOS, VLENPOS) \
236+
case Intrinsic::VPID: \
237+
break;
238+
#include "llvm/IR/VPIntrinsics.def"
239+
}
240+
return true;
241+
}
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// Equivalent non-predicated opcode
244+
unsigned VPIntrinsic::GetFunctionalOpcodeForVP(Intrinsic::ID ID) {
245+
switch (ID) {
246+
default:
247+
return Instruction::Call;
248+
249+
#define HANDLE_VP_TO_OC(VPID, OC) \
250+
case Intrinsic::VPID: \
251+
return Instruction::OC;
252+
#include "llvm/IR/VPIntrinsics.def"
253+
}
254+
}
255+
256+
Intrinsic::ID VPIntrinsic::GetForOpcode(unsigned OC) {
257+
switch (OC) {
258+
default:
259+
return Intrinsic::not_intrinsic;
260+
261+
#define HANDLE_VP_TO_OC(VPID, OC) \
262+
case Instruction::OC: \
263+
return Intrinsic::VPID;
264+
#include "llvm/IR/VPIntrinsics.def"
265+
}
266+
}
267+
268+
bool VPIntrinsic::canIgnoreVectorLengthParam() const {
269+
// No vlen param - no lanes masked-off by it.
270+
auto *VLParam = getVectorLengthParam();
271+
if (!VLParam)
272+
return true;
273+
274+
// Can ignore if MSB of vlen is set.
275+
auto VLConst = dyn_cast<ConstantInt>(VLParam);
276+
if (VLConst && VLConst->getSExtValue() < 0)
277+
return true;
278+
279+
// Vlen param greater-equal type vlen - no lanes masked-off.
280+
if (VLConst) {
281+
auto ElemCount = getVectorLength();
282+
if (ElemCount.Scalable)
283+
return false;
284+
285+
uint64_t VLNum = VLConst->getZExtValue();
286+
if (VLNum >= ElemCount.Min)
287+
return true;
288+
}
289+
290+
// Cannot ignore vlen param by default.
291+
return false;
292+
}
293+
181294
Instruction::BinaryOps BinaryOpIntrinsic::getBinaryOp() const {
182295
switch (getIntrinsicID()) {
183296
case Intrinsic::uadd_with_overflow:

‎llvm/test/Verifier/vp-intrinsics.ll

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1+
; RUN: opt --verify %s
2+
3+
define void @test_vp_int(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n) {
4+
%r0 = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
5+
%r1 = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
6+
%r2 = call <8 x i32> @llvm.vp.mul.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
7+
%r3 = call <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
8+
%r4 = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
9+
%r5 = call <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
10+
%r6 = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
11+
%r7 = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
12+
%r8 = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
13+
%r9 = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
14+
%rA = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
15+
%rB = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
16+
%rC = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
17+
ret void
18+
}
19+
20+
; integer arith
21+
declare <8 x i32> @llvm.vp.add.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
22+
declare <8 x i32> @llvm.vp.sub.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
23+
declare <8 x i32> @llvm.vp.mul.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
24+
declare <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
25+
declare <8 x i32> @llvm.vp.srem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
26+
declare <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
27+
declare <8 x i32> @llvm.vp.urem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
28+
; bit arith
29+
declare <8 x i32> @llvm.vp.and.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
30+
declare <8 x i32> @llvm.vp.or.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
31+
declare <8 x i32> @llvm.vp.xor.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
32+
declare <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
33+
declare <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
34+
declare <8 x i32> @llvm.vp.shl.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)

‎llvm/unittests/IR/CMakeLists.txt

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@@ -40,6 +40,7 @@ add_llvm_unittest(IRTests
4040
ValueTest.cpp
4141
VectorTypesTest.cpp
4242
VerifierTest.cpp
43+
VPIntrinsicTest.cpp
4344
WaymarkTest.cpp
4445
)
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