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guy-davidGuy David
guy-david
authored and
Guy David
committed
[AArch64] Skip storing of stack arguments when lowering tail calls (llvm#126735)
This issue starts in the selection DAG and causes the backend to emit the following for a trivial tail call: ``` ldr w8, [sp] str w8, [sp] b func ``` I'm not too sure that checking for immutability of a specific stack object is a good enough of a gurantee, because as soon a tail-call is done lowering,`setHasTailCall()` is called and in that case perhaps a pass is allowed to change the value of the object in-memory? This can be extended to the ARM backend as well. Removed the `tailcall` keyword from a few other test assets, I'm assuming their original intent was left intact. (cherry picked from commit 4d4b7cc)
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+241
-57
lines changed

9 files changed

+241
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lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/Utils.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -589,5 +589,9 @@ bool isGuaranteedNotToBeUndef(Register Reg, const MachineRegisterInfo &MRI,
589589
/// estimate of the type.
590590
Type *getTypeForLLT(LLT Ty, LLVMContext &C);
591591

592+
/// Returns true if the instruction \p MI is one of the assert
593+
/// instructions.
594+
bool isAssertMI(const MachineInstr &MI);
595+
592596
} // End namespace llvm.
593597
#endif

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -717,6 +717,18 @@ END_TWO_BYTE_PACK()
717717
}
718718
}
719719

720+
/// Test if this node is an assert operation.
721+
bool isAssert() const {
722+
switch (NodeType) {
723+
default:
724+
return false;
725+
case ISD::AssertAlign:
726+
case ISD::AssertSext:
727+
case ISD::AssertZext:
728+
return true;
729+
}
730+
}
731+
720732
/// Test if this node is a vector predication operation.
721733
bool isVPOpcode() const { return ISD::isVPOpcode(getOpcode()); }
722734

‎llvm/lib/CodeGen/GlobalISel/Utils.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1977,3 +1977,14 @@ Type *llvm::getTypeForLLT(LLT Ty, LLVMContext &C) {
19771977
Ty.getElementCount());
19781978
return IntegerType::get(C, Ty.getSizeInBits());
19791979
}
1980+
1981+
bool llvm::isAssertMI(const MachineInstr &MI) {
1982+
switch (MI.getOpcode()) {
1983+
default:
1984+
return false;
1985+
case TargetOpcode::G_ASSERT_ALIGN:
1986+
case TargetOpcode::G_ASSERT_SEXT:
1987+
case TargetOpcode::G_ASSERT_ZEXT:
1988+
return true;
1989+
}
1990+
}

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 44 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8264,6 +8264,45 @@ static unsigned getSMCondition(const SMEAttrs &CallerAttrs,
82648264
llvm_unreachable("Unsupported attributes");
82658265
}
82668266

8267+
/// Check whether a stack argument requires lowering in a tail call.
8268+
static bool shouldLowerTailCallStackArg(const MachineFunction &MF,
8269+
const CCValAssign &VA, SDValue Arg,
8270+
ISD::ArgFlagsTy Flags, int CallOffset) {
8271+
// FIXME: We should be able to handle this case, but it's not clear how to.
8272+
if (Flags.isZExt() || Flags.isSExt())
8273+
return true;
8274+
8275+
for (;;) {
8276+
// Look through nodes that don't alter the bits of the incoming value.
8277+
unsigned Op = Arg.getOpcode();
8278+
if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST ||
8279+
Arg->isAssert() || Op == AArch64ISD::ASSERT_ZEXT_BOOL) {
8280+
Arg = Arg.getOperand(0);
8281+
continue;
8282+
}
8283+
break;
8284+
}
8285+
8286+
// If the argument is a load from the same immutable stack slot, we can reuse
8287+
// it.
8288+
if (auto *LoadNode = dyn_cast<LoadSDNode>(Arg)) {
8289+
if (auto *FINode = dyn_cast<FrameIndexSDNode>(LoadNode->getBasePtr())) {
8290+
const MachineFrameInfo &MFI = MF.getFrameInfo();
8291+
int FI = FINode->getIndex();
8292+
if (!MFI.isImmutableObjectIndex(FI))
8293+
return true;
8294+
if (CallOffset != MFI.getObjectOffset(FI))
8295+
return true;
8296+
uint64_t SizeInBits = LoadNode->getMemoryVT().getFixedSizeInBits();
8297+
if (SizeInBits / 8 != MFI.getObjectSize(FI))
8298+
return true;
8299+
return false;
8300+
}
8301+
}
8302+
8303+
return true;
8304+
}
8305+
82678306
/// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
82688307
/// and add input and output parameter nodes.
82698308
SDValue
@@ -8691,10 +8730,13 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
86918730
}
86928731
unsigned LocMemOffset = VA.getLocMemOffset();
86938732
int32_t Offset = LocMemOffset + BEAlign;
8694-
SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
8695-
PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
86968733

86978734
if (IsTailCall) {
8735+
// When the frame pointer is perfectly aligned for the tail call and the
8736+
// same stack argument is passed down intact, we can reuse it.
8737+
if (!FPDiff && !shouldLowerTailCallStackArg(MF, VA, Arg, Flags, Offset))
8738+
continue;
8739+
86988740
Offset = Offset + FPDiff;
86998741
int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
87008742

‎llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@
2424
#include "llvm/CodeGen/Analysis.h"
2525
#include "llvm/CodeGen/CallingConvLower.h"
2626
#include "llvm/CodeGen/FunctionLoweringInfo.h"
27+
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
2728
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
2829
#include "llvm/CodeGen/GlobalISel/Utils.h"
2930
#include "llvm/CodeGen/LowLevelTypeUtils.h"
@@ -34,6 +35,7 @@
3435
#include "llvm/CodeGen/MachineMemOperand.h"
3536
#include "llvm/CodeGen/MachineOperand.h"
3637
#include "llvm/CodeGen/MachineRegisterInfo.h"
38+
#include "llvm/CodeGen/TargetOpcodes.h"
3739
#include "llvm/CodeGen/TargetRegisterInfo.h"
3840
#include "llvm/CodeGen/TargetSubtargetInfo.h"
3941
#include "llvm/CodeGen/ValueTypes.h"
@@ -296,10 +298,57 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
296298
MIRBuilder.buildCopy(PhysReg, ExtReg);
297299
}
298300

301+
/// Check whether a stack argument requires lowering in a tail call.
302+
static bool shouldLowerTailCallStackArg(const MachineFunction &MF,
303+
const CCValAssign &VA,
304+
Register ValVReg,
305+
Register StoreAddr) {
306+
const MachineRegisterInfo &MRI = MF.getRegInfo();
307+
// Print the defining instruction for the value.
308+
auto *DefMI = MRI.getVRegDef(ValVReg);
309+
assert(DefMI && "No defining instruction");
310+
for (;;) {
311+
// Look through nodes that don't alter the bits of the incoming value.
312+
unsigned Op = DefMI->getOpcode();
313+
if (Op == TargetOpcode::G_ZEXT || Op == TargetOpcode::G_ANYEXT ||
314+
Op == TargetOpcode::G_BITCAST || isAssertMI(*DefMI)) {
315+
DefMI = MRI.getVRegDef(DefMI->getOperand(1).getReg());
316+
continue;
317+
}
318+
break;
319+
}
320+
321+
auto *Load = dyn_cast<GLoad>(DefMI);
322+
if (!Load)
323+
return true;
324+
Register LoadReg = Load->getPointerReg();
325+
auto *LoadAddrDef = MRI.getVRegDef(LoadReg);
326+
if (LoadAddrDef->getOpcode() != TargetOpcode::G_FRAME_INDEX)
327+
return true;
328+
const MachineFrameInfo &MFI = MF.getFrameInfo();
329+
int LoadFI = LoadAddrDef->getOperand(1).getIndex();
330+
331+
auto *StoreAddrDef = MRI.getVRegDef(StoreAddr);
332+
if (StoreAddrDef->getOpcode() != TargetOpcode::G_FRAME_INDEX)
333+
return true;
334+
int StoreFI = StoreAddrDef->getOperand(1).getIndex();
335+
336+
if (!MFI.isImmutableObjectIndex(LoadFI))
337+
return true;
338+
if (MFI.getObjectOffset(LoadFI) != MFI.getObjectOffset(StoreFI))
339+
return true;
340+
if (Load->getMemSize() != MFI.getObjectSize(StoreFI))
341+
return true;
342+
343+
return false;
344+
}
345+
299346
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
300347
const MachinePointerInfo &MPO,
301348
const CCValAssign &VA) override {
302349
MachineFunction &MF = MIRBuilder.getMF();
350+
if (!FPDiff && !shouldLowerTailCallStackArg(MF, VA, ValVReg, Addr))
351+
return;
303352
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
304353
inferAlignFromPtrInfo(MF, MPO));
305354
MIRBuilder.buildStore(ValVReg, Addr, *MMO);

‎llvm/test/CodeGen/AArch64/darwinpcs-tail.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@
55

66
; CHECK-LABEL: __ZThn16_N1C3addEPKcz:
77
; CHECK: b __ZN1C3addEPKcz
8+
89
; CHECK-LABEL: _tailTest:
910
; CHECK: b __ZN1C3addEPKcz
11+
1012
; CHECK-LABEL: __ZThn8_N1C1fEiiiiiiiiiz:
11-
; CHECK: ldr w9, [sp, #4]
12-
; CHECK: str w9, [sp, #4]
1313
; CHECK: b __ZN1C1fEiiiiiiiiiz
1414

1515
%class.C = type { %class.A.base, [4 x i8], %class.B.base, [4 x i8] }

‎llvm/test/CodeGen/AArch64/scavenge-large-call.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; CHECK: add {{x[0-9]+}}, sp,
55

66
define void @caller(ptr %0, i16 %1, i16 %2, i8 %3, double %4, i16 %5, i8 %6, ptr %7, double %8, i32 %9, ptr %10, double %11, double %12, [2 x i64] %13, [2 x i64] %14, [2 x i64] %15, double %16, double %17, [2 x i64] %18, [2 x i64] %19, i16 %20, i32 %21, double %22, i8 %23, [2 x i64] %24, [2 x i64] %25, [2 x i64] %26, i8 %27, i16 %28, i16 %29, i16 %30, i32 %31, [2 x i64] %32, [2 x i64] %33, [2 x i64] %34, [2 x i64] %35, [2 x i64] %36, i32 %37, i32 %38) {
7-
tail call void @callee(ptr %0, i16 %1, i16 %2, i8 %3, double 0.000000e+00, i16 %5, i8 %6, ptr %7, double 0.000000e+00, i32 %9, ptr %10, double 0.000000e+00, double 0.000000e+00, [2 x i64] %13, [2 x i64] %14, [2 x i64] %15, double 0.000000e+00, double 0.000000e+00, [2 x i64] %18, [2 x i64] %19, i16 %20, i32 %21, double 0.000000e+00, i8 %23, [2 x i64] %24, [2 x i64] %25, [2 x i64] zeroinitializer, i8 %27, i16 0, i16 0, i16 %28, i32 0, [2 x i64] zeroinitializer, [2 x i64] zeroinitializer, [2 x i64] zeroinitializer, [2 x i64] %35, [2 x i64] %36, i32 0, i32 0)
7+
call void @callee(ptr %0, i16 %1, i16 %2, i8 %3, double 0.000000e+00, i16 %5, i8 %6, ptr %7, double 0.000000e+00, i32 %9, ptr %10, double 0.000000e+00, double 0.000000e+00, [2 x i64] %13, [2 x i64] %14, [2 x i64] %15, double 0.000000e+00, double 0.000000e+00, [2 x i64] %18, [2 x i64] %19, i16 %20, i32 %21, double 0.000000e+00, i8 %23, [2 x i64] %24, [2 x i64] %25, [2 x i64] zeroinitializer, i8 %27, i16 0, i16 0, i16 %28, i32 0, [2 x i64] zeroinitializer, [2 x i64] zeroinitializer, [2 x i64] zeroinitializer, [2 x i64] %35, [2 x i64] %36, i32 0, i32 0)
88
ret void
99
}
1010

‎llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll

Lines changed: 51 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -11,67 +11,66 @@ target triple = "aarch64-unknown-linux-gnu"
1111
define dso_local void @func1(ptr %v1, ptr %v2, ptr %v3, ptr %v4, ptr %v5, ptr %v6, ptr %v7, ptr %v8,
1212
; CHECK-LABEL: func1:
1313
; CHECK: // %bb.0:
14-
; CHECK-NEXT: str x29, [sp, #-48]! // 8-byte Folded Spill
15-
; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
16-
; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
17-
; CHECK-NEXT: .cfi_def_cfa_offset 48
18-
; CHECK-NEXT: .cfi_offset w19, -8
19-
; CHECK-NEXT: .cfi_offset w20, -16
20-
; CHECK-NEXT: .cfi_offset w21, -24
21-
; CHECK-NEXT: .cfi_offset w22, -32
22-
; CHECK-NEXT: .cfi_offset w29, -48
14+
; CHECK-NEXT: sub sp, sp, #368
15+
; CHECK-NEXT: stp x29, x30, [sp, #336] // 16-byte Folded Spill
16+
; CHECK-NEXT: str x28, [sp, #352] // 8-byte Folded Spill
17+
; CHECK-NEXT: add x29, sp, #336
18+
; CHECK-NEXT: .cfi_def_cfa w29, 32
19+
; CHECK-NEXT: .cfi_offset w28, -16
20+
; CHECK-NEXT: .cfi_offset w30, -24
21+
; CHECK-NEXT: .cfi_offset w29, -32
2322
; CHECK-NEXT: ptrue p0.d
24-
; CHECK-NEXT: add x10, sp, #176
25-
; CHECK-NEXT: add x8, sp, #48
26-
; CHECK-NEXT: add x9, sp, #144
27-
; CHECK-NEXT: add x20, sp, #176
28-
; CHECK-NEXT: ldr x15, [sp, #104]
29-
; CHECK-NEXT: ld1d { z3.d }, p0/z, [x10]
23+
; CHECK-NEXT: add x8, x29, #32
24+
; CHECK-NEXT: add x9, x29, #136
25+
; CHECK-NEXT: mov x12, #32 // =0x20
26+
; CHECK-NEXT: ldp x10, x11, [x29, #336]
3027
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8]
31-
; CHECK-NEXT: add x8, sp, #112
32-
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x9]
28+
; CHECK-NEXT: add x8, x29, #72
29+
; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]
3330
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x8]
34-
; CHECK-NEXT: ldur q4, [sp, #88]
35-
; CHECK-NEXT: ldp x9, x8, [sp, #328]
36-
; CHECK-NEXT: ldr x19, [sp, #272]
37-
; CHECK-NEXT: ldp x11, x10, [sp, #312]
38-
; CHECK-NEXT: ldp x13, x12, [sp, #296]
39-
; CHECK-NEXT: ldp x18, x14, [sp, #280]
40-
; CHECK-NEXT: ldp x16, x17, [sp, #208]
41-
; CHECK-NEXT: ldp x21, x22, [sp, #352]
42-
; CHECK-NEXT: st1d { z3.d }, p0, [x20]
43-
; CHECK-NEXT: add x20, sp, #144
44-
; CHECK-NEXT: st1d { z2.d }, p0, [x20]
45-
; CHECK-NEXT: add x20, sp, #112
46-
; CHECK-NEXT: st1d { z1.d }, p0, [x20]
47-
; CHECK-NEXT: add x20, sp, #48
48-
; CHECK-NEXT: st1d { z0.d }, p0, [x20]
49-
; CHECK-NEXT: stp x21, x22, [sp, #352]
50-
; CHECK-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
51-
; CHECK-NEXT: stp x19, x18, [sp, #272]
52-
; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
53-
; CHECK-NEXT: stp x16, x17, [sp, #208]
54-
; CHECK-NEXT: stur q4, [sp, #88]
55-
; CHECK-NEXT: str x15, [sp, #104]
56-
; CHECK-NEXT: stp x14, x13, [sp, #288]
57-
; CHECK-NEXT: stp x12, x11, [sp, #304]
58-
; CHECK-NEXT: stp x10, x9, [sp, #320]
59-
; CHECK-NEXT: str x8, [sp, #336]
60-
; CHECK-NEXT: ldr x29, [sp], #48 // 8-byte Folded Reload
61-
; CHECK-NEXT: b func2
31+
; CHECK-NEXT: add x8, x29, #104
32+
; CHECK-NEXT: add x9, x29, #288
33+
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x8]
34+
; CHECK-NEXT: add x8, x29, #168
35+
; CHECK-NEXT: ld1d { z6.d }, p0/z, [x9]
36+
; CHECK-NEXT: ld1d { z4.d }, p0/z, [x8]
37+
; CHECK-NEXT: add x8, x29, #256
38+
; CHECK-NEXT: ldr x9, [x29, #320]
39+
; CHECK-NEXT: ld1d { z5.d }, p0/z, [x8]
40+
; CHECK-NEXT: ldr x8, [x29, #200]
41+
; CHECK-NEXT: st1d { z6.d }, p0, [sp, x12, lsl #3]
42+
; CHECK-NEXT: mov x12, #28 // =0x1c
43+
; CHECK-NEXT: st1d { z5.d }, p0, [sp, x12, lsl #3]
44+
; CHECK-NEXT: mov x12, #17 // =0x11
45+
; CHECK-NEXT: st1d { z4.d }, p0, [sp, x12, lsl #3]
46+
; CHECK-NEXT: mov x12, #13 // =0xd
47+
; CHECK-NEXT: st1d { z3.d }, p0, [sp, x12, lsl #3]
48+
; CHECK-NEXT: mov x12, #9 // =0x9
49+
; CHECK-NEXT: st1d { z2.d }, p0, [sp, x12, lsl #3]
50+
; CHECK-NEXT: mov x12, #5 // =0x5
51+
; CHECK-NEXT: st1d { z1.d }, p0, [sp, x12, lsl #3]
52+
; CHECK-NEXT: st1d { z0.d }, p0, [sp]
53+
; CHECK-NEXT: stp x10, x11, [sp, #304]
54+
; CHECK-NEXT: str x9, [sp, #288]
55+
; CHECK-NEXT: str x8, [sp, #168]
56+
; CHECK-NEXT: bl func2
57+
; CHECK-NEXT: ldp x29, x30, [sp, #336] // 16-byte Folded Reload
58+
; CHECK-NEXT: ldr x28, [sp, #352] // 8-byte Folded Reload
59+
; CHECK-NEXT: add sp, sp, #368
60+
; CHECK-NEXT: ret
6261
ptr %v9, ptr %v10, ptr %v11, ptr %v12, ptr %v13, ptr %v14, ptr %v15, ptr %v16,
6362
ptr %v17, ptr %v18, ptr %v19, ptr %v20, ptr %v21, ptr %v22, ptr %v23, ptr %v24,
6463
ptr %v25, ptr %v26, ptr %v27, ptr %v28, ptr %v29, ptr %v30, ptr %v31, ptr %v32,
6564
ptr %v33, ptr %v34, ptr %v35, ptr %v36, ptr %v37, ptr %v38, ptr %v39, ptr %v40,
6665
ptr %v41, ptr %v42, ptr %v43, ptr %v44, ptr %v45, ptr %v46, ptr %v47, ptr %v48,
6766
i64 %v49) #0 {
68-
tail call void @func2(ptr %v1, ptr %v2, ptr %v3, ptr %v4, ptr %v5, ptr %v6, ptr %v7, ptr %v8,
69-
ptr %v9, ptr %v10, ptr %v11, ptr %v12, ptr undef, ptr %v14, ptr %v15, ptr %v16,
70-
ptr %v17, ptr %v18, ptr %v19, ptr %v20, ptr %v21, ptr %v22, ptr %v23, ptr %v24,
71-
ptr %v25, ptr %v26, ptr %v27, ptr %v28, ptr %v29, ptr %v30, ptr undef, ptr undef,
72-
ptr undef, ptr undef, ptr undef, ptr undef, ptr %v37, ptr %v38, ptr %v39, ptr %v40,
73-
ptr %v41, ptr %v42, ptr %v43, ptr %v44, ptr %v45, ptr undef, ptr %v47, ptr %v48,
74-
i64 undef)
67+
call void @func2(ptr %v1, ptr %v2, ptr %v3, ptr %v4, ptr %v5, ptr %v6, ptr %v7, ptr %v8,
68+
ptr %v9, ptr %v10, ptr %v11, ptr %v12, ptr undef, ptr %v14, ptr %v15, ptr %v16,
69+
ptr %v17, ptr %v18, ptr %v19, ptr %v20, ptr %v21, ptr %v22, ptr %v23, ptr %v24,
70+
ptr %v25, ptr %v26, ptr %v27, ptr %v28, ptr %v29, ptr %v30, ptr undef, ptr undef,
71+
ptr undef, ptr undef, ptr undef, ptr undef, ptr %v37, ptr %v38, ptr %v39, ptr %v40,
72+
ptr %v41, ptr %v42, ptr %v43, ptr %v44, ptr %v45, ptr undef, ptr %v47, ptr %v48,
73+
i64 undef)
7574
ret void
7675
}
7776

‎llvm/test/CodeGen/AArch64/tail-call-stack-args.ll

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc %s -mtriple=aarch64 -o - | FileCheck %s --check-prefixes=CHECK,SDAG
3+
; RUN: llc %s -mtriple=aarch64 -global-isel -o - | FileCheck %s --check-prefixes=CHECK,GI
4+
5+
; Tail calls which have stack arguments in the same offsets as the caller do not
6+
; need to load and store the arguments from the stack.
7+
8+
declare void @func(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j)
9+
10+
define void @wrapper_func(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j) {
11+
; CHECK-LABEL: wrapper_func:
12+
; CHECK: // %bb.0:
13+
; CHECK-NEXT: b func
14+
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tail call void @func(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j)
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ret void
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}
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define void @wrapper_func_zero_arg(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j) {
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; CHECK-LABEL: wrapper_func_zero_arg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str wzr, [sp, #8]
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; CHECK-NEXT: b func
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tail call void @func(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 0)
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ret void
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}
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define void @wrapper_func_overriden_arg(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j) {
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; CHECK-LABEL: wrapper_func_overriden_arg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [sp]
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; CHECK-NEXT: str wzr, [sp]
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; CHECK-NEXT: str w8, [sp, #8]
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; CHECK-NEXT: b func
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tail call void @func(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 0, i32 %i)
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ret void
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}
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declare void @func_i1(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i1 %j)
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; FIXME: Support i1 passthrough stack arguments in GlobalISel.
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define void @wrapper_func_i1(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i1 %j) {
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; SDAG-LABEL: wrapper_func_i1:
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; SDAG: // %bb.0:
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; SDAG-NEXT: b func_i1
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;
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; GI-LABEL: wrapper_func_i1:
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; GI: // %bb.0:
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; GI-NEXT: ldrb w8, [sp, #8]
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; GI-NEXT: strb w8, [sp, #8]
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; GI-NEXT: b func_i1
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tail call void @func_i1(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i1 %j)
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ret void
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}
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declare void @func_signext_i1(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i1 signext %j)
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; FIXME: Support zero/sign-extended stack arguments.
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define void @wrapper_func_i8(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i1 signext %j) {
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; CHECK-LABEL: wrapper_func_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrsb w8, [sp, #8]
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; CHECK-NEXT: strb w8, [sp, #8]
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; CHECK-NEXT: b func_signext_i1
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tail call void @func_signext_i1(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i1 signext %j)
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ret void
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}

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