From d69a2f815e44f6ea90a4687033f5128ef4f38e1a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 2 Dec 2020 18:27:34 +0100 Subject: [PATCH 1/3] [F3] Update STM32F3xx HAL Drivers to v1.5.5 Included in STM32CubeF3 FW v1.11.2 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 187 ++- .../Inc/stm32f3xx_hal_adc_ex.h | 8 +- .../Inc/stm32f3xx_hal_cec.h | 4 +- .../Inc/stm32f3xx_hal_def.h | 28 +- .../Inc/stm32f3xx_hal_exti.h | 22 +- .../Inc/stm32f3xx_hal_hrtim.h | 139 ++- .../Inc/stm32f3xx_hal_i2s.h | 14 +- .../Inc/stm32f3xx_hal_i2s_ex.h | 10 + .../Inc/stm32f3xx_hal_irda.h | 60 +- .../Inc/stm32f3xx_hal_irda_ex.h | 2 +- .../Inc/stm32f3xx_hal_nand.h | 96 +- .../Inc/stm32f3xx_hal_nor.h | 52 +- .../Inc/stm32f3xx_hal_pccard.h | 25 +- .../Inc/stm32f3xx_hal_rtc.h | 16 +- .../Inc/stm32f3xx_hal_smartcard.h | 126 +- .../Inc/stm32f3xx_hal_spi.h | 48 +- .../Inc/stm32f3xx_hal_sram.h | 65 +- .../Inc/stm32f3xx_hal_tim.h | 289 +++-- .../Inc/stm32f3xx_hal_tim_ex.h | 29 +- .../Inc/stm32f3xx_hal_tsc.h | 4 + .../Inc/stm32f3xx_hal_uart.h | 198 ++-- .../Inc/stm32f3xx_hal_uart_ex.h | 6 +- .../Inc/stm32f3xx_hal_usart.h | 79 +- .../Inc/stm32f3xx_hal_usart_ex.h | 8 +- .../Inc/stm32f3xx_hal_wwdg.h | 21 +- .../Inc/stm32f3xx_ll_adc.h | 113 +- .../Inc/stm32f3xx_ll_comp.h | 6 +- .../Inc/stm32f3xx_ll_exti.h | 2 +- .../Inc/stm32f3xx_ll_fmc.h | 230 ++-- .../Inc/stm32f3xx_ll_hrtim.h | 992 ++++++++-------- .../Inc/stm32f3xx_ll_opamp.h | 8 +- .../Inc/stm32f3xx_ll_rcc.h | 4 + .../Inc/stm32f3xx_ll_rtc.h | 16 +- .../Inc/stm32f3xx_ll_spi.h | 22 +- .../Inc/stm32f3xx_ll_tim.h | 126 +- .../Inc/stm32f3xx_ll_usart.h | 222 ++-- .../Inc/stm32f3xx_ll_utils.h | 3 + system/Drivers/STM32F3xx_HAL_Driver/README.md | 1 + .../STM32F3xx_HAL_Driver/Release_Notes.html | 319 +++++- .../STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c | 4 +- .../Src/stm32f3xx_hal_adc_ex.c | 105 +- .../Src/stm32f3xx_hal_cec.c | 12 +- .../Src/stm32f3xx_hal_hrtim.c | 8 +- .../Src/stm32f3xx_hal_i2s.c | 225 +++- .../Src/stm32f3xx_hal_i2s_ex.c | 33 +- .../Src/stm32f3xx_hal_irda.c | 55 +- .../Src/stm32f3xx_hal_iwdg.c | 44 +- .../Src/stm32f3xx_hal_nand.c | 734 ++++++------ .../Src/stm32f3xx_hal_nor.c | 485 +++++--- .../Src/stm32f3xx_hal_opamp.c | 4 +- .../Src/stm32f3xx_hal_pccard.c | 141 ++- .../Src/stm32f3xx_hal_rcc_ex.c | 2 +- .../Src/stm32f3xx_hal_rtc.c | 78 +- .../Src/stm32f3xx_hal_smartcard.c | 279 +++-- .../Src/stm32f3xx_hal_smartcard_ex.c | 6 - .../Src/stm32f3xx_hal_spi.c | 153 ++- .../Src/stm32f3xx_hal_sram.c | 194 ++-- .../Src/stm32f3xx_hal_tim.c | 1012 ++++++++++++++--- .../Src/stm32f3xx_hal_tim_ex.c | 481 +++++++- ...tm32f3xx_hal_timebase_rtc_alarm_template.c | 159 +-- ...m32f3xx_hal_timebase_rtc_wakeup_template.c | 129 ++- .../Src/stm32f3xx_hal_timebase_tim_template.c | 49 +- .../Src/stm32f3xx_hal_tsc.c | 4 +- .../Src/stm32f3xx_hal_uart.c | 662 ++++++++--- .../Src/stm32f3xx_hal_uart_ex.c | 281 ++++- .../Src/stm32f3xx_hal_usart.c | 76 +- .../Src/stm32f3xx_hal_wwdg.c | 58 +- .../Src/stm32f3xx_ll_adc.c | 7 + .../Src/stm32f3xx_ll_fmc.c | 133 ++- .../Src/stm32f3xx_ll_rcc.c | 6 +- .../Src/stm32f3xx_ll_spi.c | 19 +- .../Src/stm32f3xx_ll_tim.c | 2 +- .../Src/stm32f3xx_ll_usart.c | 27 +- .../Src/stm32f3xx_ll_utils.c | 128 ++- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 75 files changed, 6328 insertions(+), 3069 deletions(-) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 53eefa788a..fbda58823f 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -38,7 +38,6 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - /** * @} */ @@ -236,12 +235,12 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) -#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) -#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) +#if defined(STM32G4) || defined(STM32H7) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -306,8 +305,22 @@ #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + #endif /* STM32L4 */ +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + #if defined(STM32H7) #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 @@ -365,6 +378,9 @@ #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + #endif /* STM32H7 */ /** @@ -566,7 +582,14 @@ #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 -#endif + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 @@ -624,6 +647,10 @@ #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL #endif /* STM32G4 */ #if defined(STM32H7) @@ -737,6 +764,66 @@ #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the events that can be selected to configure the + * set/reset crossbar of a timer output + */ +#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) +#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) +#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) +#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) +#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) +#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) +#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) +#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) +#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) + +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) + +/** @brief Constants defining the event filtering applied to external events + * by a timer + */ +#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ /** * @} */ @@ -876,7 +963,7 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -967,6 +1054,16 @@ #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + /** * @} */ @@ -1360,6 +1457,30 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1382,6 +1503,12 @@ #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ /** * @} @@ -1412,16 +1539,18 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */ +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT @@ -1440,6 +1569,13 @@ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown @@ -1512,14 +1648,14 @@ #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ /** * @} */ @@ -3115,9 +3251,8 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3245,7 +3380,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3353,9 +3488,9 @@ #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler @@ -3368,7 +3503,7 @@ #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif -#if defined(STM32H7) +#if defined(STM32H7) || defined(STM32L5) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback @@ -3609,12 +3744,12 @@ * @{ */ #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) -#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT -#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA -#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart -#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT -#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA -#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop #endif /** * @} @@ -3623,9 +3758,9 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32L4) +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif +#endif /* STM32L4 || STM32F4 || STM32F7 */ /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h index 8fdae6ac77..52b941d544 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h @@ -88,8 +88,9 @@ typedef struct New conversion starts only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software. This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. - Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. - Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). + Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). @@ -765,6 +766,7 @@ typedef struct #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_EXTERNALTRIG_T1_CC1 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_EXTERNALTRIG_T1_CC2 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_EXTERNALTRIG_T1_CC3 +#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_EXTERNALTRIG_T2_CC2 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_EXTERNALTRIG_EXT_IT11 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_EXTERNALTRIG_T1_TRGO #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_EXTERNALTRIG_T1_TRGO2 @@ -1633,6 +1635,7 @@ typedef struct #define ADC1_EXTERNALTRIG_T1_CC1 (0x00000000U) #define ADC1_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC1_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) +#define ADC1_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC1_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) #define ADC1_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) @@ -3203,6 +3206,7 @@ typedef struct #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h index ad98f3b8d5..dd1bc99662 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h @@ -121,7 +121,7 @@ typedef struct * b6 Error information * 0 : No Error * 1 : Error - * b5 IP initilisation status + * b5 IP initialization status * 0 : Reset (IP not initialized) * 1 : Init done (IP initialized. HAL CEC Init function already called) * b4-b3 (not used) @@ -138,7 +138,7 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initilisation status + * b5 IP initialization status * 0 : Reset (IP not initialized) * 1 : Init done (IP initialized) * b4-b2 (not used) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h index 4719f4babf..a6f99d18fa 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h @@ -28,9 +28,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" -#if defined USE_LEGACY #include "Legacy/stm32_hal_legacy.h" -#endif #include /* Exported types ------------------------------------------------------------*/ @@ -108,7 +106,14 @@ typedef enum }while (0U) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif + #ifndef __packed + #define __packed __attribute__((packed)) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -119,7 +124,14 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ @@ -131,7 +143,7 @@ typedef enum #define __ALIGN_END #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler */ + #if defined (__CC_ARM) /* ARM Compiler V5*/ #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN @@ -142,9 +154,9 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- */ #define __NOINLINE __attribute__ ( (noinline) ) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h index a86c8d8913..e7560e5fa5 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h @@ -302,21 +302,21 @@ typedef struct /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ -#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ - ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ - (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) -#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ - (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) -#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) -#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) -#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) #if defined(GPIOH) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h index f4f8390dd3..7ddc7bc0db 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h @@ -1017,15 +1017,15 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */ @@ -1137,9 +1137,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< /** * @} */ -/** - * @} - */ /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter * @{ @@ -1147,21 +1144,21 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * by a timer */ #define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */ -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */ -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */ -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */ -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */ -#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */ +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */ +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */ +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */ +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */ +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ /** * @} */ @@ -2229,18 +2226,18 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ - (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ + (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ @@ -2250,31 +2247,31 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ - (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ + (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ @@ -2284,16 +2281,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h index f792842829..1b142dfcbd 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h @@ -182,6 +182,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ /** * @} */ @@ -405,6 +406,15 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to tmpreg_udr = ((__HANDLE__)->Instance->SR);\ UNUSED(tmpreg_udr); \ }while(0U) +/** @brief Flush the I2S DR Register. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ + __IO uint32_t tmpreg_dr = 0x00U;\ + tmpreg_dr = ((__HANDLE__)->Instance->DR);\ + UNUSED(tmpreg_dr); \ + }while(0U) /** * @} */ @@ -490,7 +500,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); */ /** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of I2S SR regsiter. + * @param __SR__ copy of I2S SR register. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2S_FLAG_RXNE: Receive buffer not empty flag @@ -505,7 +515,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of I2S CR2 regsiter. + * @param __CR2__ copy of I2S CR2 register. * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s_ex.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s_ex.h index 5c42e6266f..0d4ebb9937 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s_ex.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s_ex.h @@ -111,6 +111,16 @@ extern "C" { tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\ UNUSED(tmpreg_udr); \ }while(0U) +/** @brief Flush the I2S and I2SExt DR Registers. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2SEXT_FLUSH_RX_DR(__HANDLE__) do{ \ + __IO uint32_t tmpreg_dr = 0x00U; \ + tmpreg_dr = I2SxEXT((__HANDLE__)->Instance)->DR; \ + tmpreg_dr = ((__HANDLE__)->Instance->DR); \ + UNUSED(tmpreg_dr); \ + }while(0U) /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda.h index edd9e915a0..7ef5a07972 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda.h @@ -75,7 +75,8 @@ typedef struct /** * @brief HAL IRDA State definition - * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition). + * @note HAL IRDA State value is a combination of 2 different substates: + * gState and RxState (see @ref IRDA_State_Definition). * - gState contains IRDA state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -86,7 +87,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called) + * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -103,7 +104,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -245,7 +246,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer Value is allowed for RxState only */ #define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Value is result of combination (Or) between + gState and RxState values */ #define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error @@ -257,15 +259,15 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer /** @defgroup IRDA_Error_Definition IRDA Error Code Definition * @{ */ -#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */ +#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /** * @} @@ -549,9 +551,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((__HANDLE__)->Instance->CR3 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__ specifies the IRDA Handle. @@ -565,10 +572,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) - +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -584,8 +595,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -599,9 +610,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \ + & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \ + & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda_ex.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda_ex.h index a5dd66bed3..14c8ccb540 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda_ex.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda_ex.h @@ -52,7 +52,7 @@ extern "C" { #define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */ #elif defined(USART_CR1_M) #define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */ -#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long frame */ +#define IRDA_WORDLENGTH_9B USART_CR1_M /*!< 9-bit long frame */ #endif /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h index 4c895ce5c7..2d446729d6 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h @@ -90,10 +90,10 @@ typedef struct typedef struct { uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ @@ -131,9 +131,9 @@ typedef struct NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */ - void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */ - void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */ + void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ + void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ + void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ #endif } NAND_HandleTypeDef; @@ -146,7 +146,7 @@ typedef enum HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ -}HAL_NAND_CallbackIDTypeDef; +} HAL_NAND_CallbackIDTypeDef; /** * @brief HAL NAND Callback pointer definition @@ -161,8 +161,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup NAND_Exported_Macros NAND Exported Macros - * @{ - */ + * @{ + */ /** @brief Reset NAND handle state * @param __HANDLE__ specifies the NAND handle. @@ -192,7 +192,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); @@ -215,15 +216,23 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /* IO operation functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); - -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); @@ -231,7 +240,8 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressT #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /* NAND callback registering/unregistering */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); #endif @@ -272,34 +282,34 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** @defgroup NAND_Private_Constants NAND Private Constants * @{ */ -#define NAND_DEVICE1 ((uint32_t)0x70000000U) -#define NAND_DEVICE2 ((uint32_t)0x80000000U) -#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U) +#define NAND_DEVICE1 0x70000000UL +#define NAND_DEVICE2 0x80000000UL +#define NAND_WRITE_TIMEOUT 0x01000000UL -#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */ -#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */ +#define CMD_AREA (1UL<<16U) /* A16 = CLE high */ +#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ -#define NAND_CMD_AREA_A ((uint8_t)0x00U) -#define NAND_CMD_AREA_B ((uint8_t)0x01U) -#define NAND_CMD_AREA_C ((uint8_t)0x50U) -#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) +#define NAND_CMD_AREA_A ((uint8_t)0x00) +#define NAND_CMD_AREA_B ((uint8_t)0x01) +#define NAND_CMD_AREA_C ((uint8_t)0x50) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) -#define NAND_CMD_WRITE0 ((uint8_t)0x80U) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) -#define NAND_CMD_ERASE0 ((uint8_t)0x60U) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0U) -#define NAND_CMD_READID ((uint8_t)0x90U) -#define NAND_CMD_STATUS ((uint8_t)0x70U) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) -#define NAND_CMD_RESET ((uint8_t)0xFFU) +#define NAND_CMD_WRITE0 ((uint8_t)0x80) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) +#define NAND_CMD_ERASE0 ((uint8_t)0x60) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0) +#define NAND_CMD_READID ((uint8_t)0x90) +#define NAND_CMD_STATUS ((uint8_t)0x70) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) +#define NAND_CMD_RESET ((uint8_t)0xFF) /* NAND memory status */ -#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U) -#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U) -#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U) -#define NAND_BUSY ((uint32_t)0x00000000U) -#define NAND_ERROR ((uint32_t)0x00000001U) -#define NAND_READY ((uint32_t)0x00000040U) +#define NAND_VALID_ADDRESS 0x00000100UL +#define NAND_INVALID_ADDRESS 0x00000200UL +#define NAND_TIMEOUT_ERROR 0x00000400UL +#define NAND_BUSY 0x00000000UL +#define NAND_ERROR 0x00000001UL +#define NAND_READY 0x00000040UL /** * @} */ @@ -316,7 +326,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) /** * @brief NAND memory Column address computation. diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h index 80cce022fa..86f5ebd64e 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h @@ -121,9 +121,11 @@ typedef struct __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ + uint32_t CommandSet; /*!< NOR algorithm command set and control */ + #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */ - void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */ + void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ + void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ #endif } NOR_HandleTypeDef; @@ -135,7 +137,7 @@ typedef enum { HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ -}HAL_NOR_CallbackIDTypeDef; +} HAL_NOR_CallbackIDTypeDef; /** * @brief HAL NOR Callback pointer definition @@ -178,7 +180,8 @@ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); @@ -197,8 +200,10 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); @@ -206,7 +211,8 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) /* NOR callback registering/unregistering */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); #endif /** @@ -246,29 +252,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @{ */ /* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000U) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) +#define MC_ADDRESS ((uint16_t)0x0000) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) /* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x61U) -#define CFI2_ADDRESS ((uint16_t)0x62U) -#define CFI3_ADDRESS ((uint16_t)0x63U) -#define CFI4_ADDRESS ((uint16_t)0x64U) +#define CFI1_ADDRESS ((uint16_t)0x61) +#define CFI2_ADDRESS ((uint16_t)0x62) +#define CFI3_ADDRESS ((uint16_t)0x63) +#define CFI4_ADDRESS ((uint16_t)0x64) /* NOR operation wait timeout */ -#define NOR_TMEOUT ((uint16_t)0xFFFFU) +#define NOR_TMEOUT ((uint16_t)0xFFFF) /* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0U) -#define NOR_MEMORY_16B ((uint8_t)0x1U) +#define NOR_MEMORY_8B ((uint8_t)0x0) +#define NOR_MEMORY_16B ((uint8_t)0x1) /* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U) -#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U) -#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U) -#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U) +#define NOR_MEMORY_ADRESS1 (0x60000000U) +#define NOR_MEMORY_ADRESS2 (0x64000000U) +#define NOR_MEMORY_ADRESS3 (0x68000000U) +#define NOR_MEMORY_ADRESS4 (0x6C000000U) /** * @} */ @@ -285,7 +291,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @retval NOR shifted address value */ #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ - ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h index bdd1a9e45a..4afc139e9b 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h @@ -65,7 +65,7 @@ typedef enum /** * @brief FMC_PCCARD handle Structure definition */ -#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) +#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) typedef struct __PCCARD_HandleTypeDef #else typedef struct @@ -80,9 +80,9 @@ typedef struct HAL_LockTypeDef Lock; /*!< PCCARD Lock */ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp Init callback */ - void (* MspDeInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp DeInit callback */ - void (* ItCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD IT callback */ + void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */ + void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */ #endif } PCCARD_HandleTypeDef; @@ -95,7 +95,7 @@ typedef enum HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */ HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */ HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */ -}HAL_PCCARD_CallbackIDTypeDef; +} HAL_PCCARD_CallbackIDTypeDef; /** * @brief HAL PCCARD Callback pointer definition @@ -137,7 +137,8 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard); * @{ */ /* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); +HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, + FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard); @@ -150,8 +151,10 @@ void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard); */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus); -HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus); -HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus); +HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus); +HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus); HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus); HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard); @@ -159,8 +162,10 @@ void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard); #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) /* PCCARD callback registering/unregistering */ -HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId); +HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, + pPCCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, + HAL_PCCARD_CallbackIDTypeDef CallbackId); #endif /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h index 508f15f29c..aa4881ef63 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h @@ -106,12 +106,11 @@ typedef struct with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function */ - uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. - This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ + uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight + Saving Time, please use HAL_RTC_DST_xxx functions */ - uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit - in CR register to store the operation. - This parameter can be a value of @ref RTC_StoreOperation_Definitions */ + uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight + Saving Time, please use HAL_RTC_DST_xxx functions */ } RTC_TimeTypeDef; /** @@ -705,6 +704,13 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); + +/* RTC Daylight Saving Time functions *****************************************/ +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h index 24d6228ad6..8bba672564 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h @@ -52,7 +52,8 @@ typedef struct where usart_ker_ckpres is the USART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ + This parameter @ref SMARTCARD_Word_Length can only be + set to 9 (8 data + 1 parity bits). */ uint32_t StopBits; /*!< Specifies the number of stop bits. This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ @@ -76,13 +77,14 @@ typedef struct data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref SMARTCARD_Last_Bit */ - uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote + is selected. Selecting the single sample method increases + the receiver tolerance to clock deviations. This parameter can be a value + of @ref SMARTCARD_OneBit_Sampling. */ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. - This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied - by 2 to give the division factor of the source clock frequency */ + This parameter can be any value from 0x01 to 0x1F. Prescaler value is + multiplied by 2 to give the division factor of the source clock frequency */ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ @@ -108,7 +110,7 @@ typedef struct } SMARTCARD_InitTypeDef; /** - * @brief SMARTCARD advanced features initalization structure definition + * @brief SMARTCARD advanced features initialization structure definition */ typedef struct { @@ -138,14 +140,16 @@ typedef struct uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref SMARTCARD_MSB_First */ - uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when - relevant flag is available) or once guard time period has elapsed. - This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + relevant flag is available) or once guard time period has elapsed. + This parameter can be a value + of @ref SMARTCARDEx_Transmission_Completion_Indication. */ } SMARTCARD_AdvFeatureInitTypeDef; /** * @brief HAL SMARTCARD State definition - * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition). + * @note HAL SMARTCARD State value is a combination of 2 different substates: + * gState and RxState (see @ref SMARTCARD_State_Definition). * - gState contains SMARTCARD state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -156,7 +160,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called) + * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -173,7 +177,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -218,12 +222,14 @@ typedef struct __SMARTCARD_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global + Handle management and also related to Tx operations. + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO uint32_t ErrorCode; /*!< SmartCard Error code */ @@ -297,23 +303,26 @@ typedef enum /** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition * @{ */ -#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ -#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value + is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for + use. Value is allowed for gState + and RxState */ #define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ -#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ +#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception + process is ongoing Not to be used for + neither gState nor RxState. + Value is result of combination (Or) + between gState and RxState values */ #define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ + Value is allowed for gState only */ /** * @} */ @@ -321,15 +330,15 @@ typedef enum /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition * @{ */ -#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */ +#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** * @} @@ -631,9 +640,16 @@ typedef enum * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -649,9 +665,16 @@ typedef enum * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -668,7 +691,9 @@ typedef enum * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) + & (0x01UL << (((__INTERRUPT__)\ + & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U)\ + ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -684,9 +709,15 @@ typedef enum * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x01U)?\ + (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x02U)?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) &\ + (0x01UL << (((uint16_t)(__INTERRUPT__))\ + & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -940,7 +971,8 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h index 63fadeea17..65655bde4a 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h @@ -582,7 +582,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) /** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of SPI SR regsiter. + * @param __SR__ copy of SPI SR register. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag @@ -596,10 +596,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_FLAG_FRLVL: SPI fifo reception level * @retval SET or RESET. */ -#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of SPI CR2 regsiter. + * @param __CR2__ copy of SPI CR2 register. * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable @@ -607,15 +608,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_IT_ERR: Error interrupt enable * @retval SET or RESET. */ -#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. * This parameter can be a value of @ref SPI_Mode * @retval None */ -#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ - ((__MODE__) == SPI_MODE_MASTER)) +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) /** @brief Checks if SPI Direction Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Direction Mode. @@ -663,33 +665,33 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_Clock_Polarity * @retval None */ -#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ - ((__CPOL__) == SPI_POLARITY_HIGH)) +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) /** @brief Checks if SPI Clock Phase parameter is in allowed range. * @param __CPHA__ specifies the SPI Clock Phase. * This parameter can be a value of @ref SPI_Clock_Phase * @retval None */ -#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ - ((__CPHA__) == SPI_PHASE_2EDGE)) +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) /** @brief Checks if SPI Slave Select parameter is in allowed range. * @param __NSS__ specifies the SPI Slave Select management parameter. * This parameter can be a value of @ref SPI_Slave_Select_management * @retval None */ -#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ - ((__NSS__) == SPI_NSS_HARD_INPUT) || \ - ((__NSS__) == SPI_NSS_HARD_OUTPUT)) +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) /** @brief Checks if SPI NSS Pulse parameter is in allowed range. * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. * This parameter can be a value of @ref SPI_NSSP_Mode * @retval None */ -#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ - ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. * @param __PRESCALER__ specifies the SPI Baudrate prescaler. @@ -710,16 +712,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_MSB_LSB_transmission * @retval None */ -#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ - ((__BIT__) == SPI_FIRSTBIT_LSB)) +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) /** @brief Checks if SPI TI mode parameter is in allowed range. * @param __MODE__ specifies the SPI TI mode. * This parameter can be a value of @ref SPI_TI_mode * @retval None */ -#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ - ((__MODE__) == SPI_TIMODE_ENABLE)) +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) /** @brief Checks if SPI CRC calculation enabled state is in allowed range. * @param __CALCULATION__ specifies the SPI CRC calculation enable state. @@ -734,8 +736,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_CRC_length * @retval None */ -#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ - ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. @@ -743,7 +745,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 * @retval None */ -#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ + ((__POLYNOMIAL__) <= 0xFFFFU) && \ + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sram.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sram.h index e82d39cc3b..6b79b5c5b4 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sram.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sram.h @@ -62,7 +62,7 @@ typedef enum typedef struct __SRAM_HandleTypeDef #else typedef struct -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ { FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ @@ -77,10 +77,10 @@ typedef struct DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */ - void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */ - void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */ + void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ + void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ #endif } SRAM_HandleTypeDef; @@ -94,7 +94,7 @@ typedef enum HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ -}HAL_SRAM_CallbackIDTypeDef; +} HAL_SRAM_CallbackIDTypeDef; /** * @brief HAL SRAM Callback pointer definition @@ -110,8 +110,8 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); /* Exported macro ------------------------------------------------------------*/ /** @defgroup SRAM_Exported_Macros SRAM Exported Macros - * @{ - */ + * @{ + */ /** @brief Reset SRAM handle state * @param __HANDLE__ SRAM handle @@ -137,11 +137,12 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); */ /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ + * @{ + */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); @@ -151,27 +152,37 @@ void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); */ /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions - * @{ - */ + * @{ + */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) /* SRAM callback registering/unregistering */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback); #endif /** @@ -179,8 +190,8 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR */ /** @addtogroup SRAM_Exported_Functions_Group3 Control functions - * @{ - */ + * @{ + */ /* SRAM Control functions ****************************************************/ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); @@ -191,8 +202,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); */ /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions - * @{ - */ + * @{ + */ /* SRAM State functions ******************************************************/ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h index c1a684536d..0d7fffe30c 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h @@ -308,6 +308,26 @@ typedef enum HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + /** * @brief HAL Active channel structures definition */ @@ -335,13 +355,16 @@ typedef struct __TIM_HandleTypeDef typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ @@ -383,36 +406,36 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - - ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ - ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ - ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ - ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ #if defined(TIM_BDTR_BK2E) - ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ #endif /* TIM_BDTR_BK2E */ } HAL_TIM_CallbackIDTypeDef; @@ -538,6 +561,17 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +#if defined(TIM_CR1_UIFREMAP) +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +#endif /* TIM_CR1_UIFREMAP */ /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ @@ -896,7 +930,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} @@ -1115,25 +1149,49 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** @@ -1334,6 +1392,33 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) +#if defined(TIM_CR1_UIFREMAP) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) +#endif /* TIM_CR1_UIFREMAP */ /** * @brief Indicates whether or not the TIM Counter is used as downcounter. @@ -1354,6 +1439,8 @@ mode. /** * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None @@ -1778,6 +1865,11 @@ mode. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) +#if defined(TIM_CR1_UIFREMAP) +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENALE)) + +#endif /* TIM_CR1_UIFREMAP */ #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) @@ -2025,15 +2117,15 @@ mode. #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ @@ -2081,6 +2173,71 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) +#else +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + (__HANDLE__)->ChannelState[3]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + } while(0) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) + /** * @} */ @@ -2306,6 +2463,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** * @} */ @@ -2325,7 +2487,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h index a533d175a3..a1aebb19de 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h @@ -152,23 +152,23 @@ typedef struct * @{ */ #if defined(TIM1) && defined(TIM8) && defined(TIM20) && defined(TIM16) -#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ - ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ - || (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ - || (((__INSTANCE__) == TIM20) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ - || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) +#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ + ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM20) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) #elif defined(TIM1) && defined(TIM8) && defined(TIM16) -#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ - ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ - || (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ - || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) +#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ + ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) #elif defined(TIM1) && defined(TIM16) -#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ - ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ - || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) +#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ + ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) #elif defined(TIM14) -#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ - (((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)) +#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ + (((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)) #endif /* TIM1 && TIM8 && TIM20 && TIM16 */ /** @@ -304,6 +304,7 @@ void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tsc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tsc.h index 30242226d6..f83bfbf46b 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tsc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tsc.h @@ -634,6 +634,10 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ ((__VALUE__) == TSC_PG_PRESC_DIV128)) +#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && ((__CTPL__) > TSC_CTPL_2CYCLES)) || \ + (((__PGPSC__) == TSC_PG_PRESC_DIV2) && ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ + (((__PGPSC__) > TSC_PG_PRESC_DIV2) && (((__CTPL__) == TSC_CTPL_1CYCLE) || ((__CTPL__) > TSC_CTPL_1CYCLE)))) + #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ ((__VALUE__) == TSC_MCV_511) || \ ((__VALUE__) == TSC_MCV_1023) || \ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h index ca35deb527..94be787992 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h @@ -76,7 +76,8 @@ typedef struct or disabled. This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). This parameter can be a value of @ref UART_Over_Sampling. */ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. @@ -93,7 +94,8 @@ typedef struct { uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . - This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. This parameter can be a value of @ref UART_Tx_Inv. */ @@ -127,7 +129,8 @@ typedef struct /** * @brief HAL UART State definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). * - gState contains UART state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -138,7 +141,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -155,7 +158,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -179,6 +182,17 @@ typedef enum UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ } UART_ClockSourceTypeDef; +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * It is expected to admit following values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -204,6 +218,8 @@ typedef struct __UART_HandleTypeDef uint16_t Mask; /*!< UART Rx RDR register mask */ + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ @@ -215,11 +231,11 @@ typedef struct __UART_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ __IO uint32_t ErrorCode; /*!< UART Error code */ @@ -233,6 +249,7 @@ typedef struct __UART_HandleTypeDef void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ @@ -265,6 +282,7 @@ typedef enum * @brief HAL UART Callback pointer definition */ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -291,8 +309,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ #define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ #define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error @@ -304,16 +322,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_Error_Definition UART Error Definition * @{ */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -391,10 +409,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ /** * @} */ @@ -556,8 +578,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ /** * @} */ @@ -583,7 +607,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register * @{ */ -#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ /** * @} */ @@ -591,9 +615,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection * @{ */ -#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ /** * @} */ @@ -610,7 +635,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ /** * @} */ @@ -618,7 +644,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ /** * @} */ @@ -687,22 +714,22 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ -#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ -#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ /** * @} */ @@ -725,6 +752,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @} */ +/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ /** * @} @@ -858,10 +895,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) - +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Disable the specified UART interrupt. * @param __HANDLE__ specifies the UART Handle. @@ -880,9 +922,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Check whether the specified UART interrupt has occurred or not. * @param __HANDLE__ specifies the UART Handle. @@ -921,9 +969,13 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. @@ -989,8 +1041,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1007,8 +1060,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1025,8 +1079,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1043,8 +1098,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1304,8 +1360,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. @@ -1388,6 +1445,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** @@ -1426,6 +1486,8 @@ void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + /** * @} */ @@ -1471,13 +1533,15 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); * @{ */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h index 869f9c9f08..15f05d6da5 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h @@ -119,7 +119,6 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); - /** * @} */ @@ -136,6 +135,11 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + + /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h index d360a19164..2b30fbe2fa 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h @@ -48,11 +48,14 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. The baud rate is computed using the following formula: - Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[15:4] = ((2 * fclk_pres) / + ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 + Baud Rate Register[2:0] = (((2 * fclk_pres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 where fclk_pres is the USART input clock frequency - @note Oversampling by 8 is systematically applied to achieve high baud rates. */ + @note Oversampling by 8 is systematically applied to + achieve high baud rates. */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USARTEx_Word_Length. */ @@ -200,15 +203,16 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin /** @defgroup USART_Error_Definition USART Error Definition * @{ */ -#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ /** * @} */ @@ -244,15 +248,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @} */ -/** @defgroup USART_Over_Sampling USART Over Sampling - * @{ - */ -#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - /** @defgroup USART_Clock USART Clock * @{ */ @@ -311,6 +306,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define USART_FLAG_CTSIF USART_ISR_CTSIF /*!< USART clear to send interrupt flag */ #define USART_FLAG_LBDF USART_ISR_LBDF /*!< USART LIN break detection flag */ #define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ #define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ #define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */ #define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ @@ -357,6 +353,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ /** * @} */ @@ -416,6 +413,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_FLAG_TXE Transmit data register empty flag * @arg @ref USART_FLAG_TC Transmission Complete flag * @arg @ref USART_FLAG_RXNE Receive data register not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag * @arg @ref USART_FLAG_IDLE Idle Line detection flag * @arg @ref USART_FLAG_ORE OverRun Error flag * @arg @ref USART_FLAG_NE Noise Error flag @@ -435,6 +433,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref USART_CLEAR_CTSF * @retval None */ @@ -484,9 +483,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -500,10 +502,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) - +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -520,7 +524,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) + & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -536,10 +541,13 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) - +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + USART_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the USART Handle. @@ -551,6 +559,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag * @retval None @@ -641,14 +650,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) -/** - * @brief Ensure that USART oversampling is valid. - * @param __SAMPLING__ USART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == USART_OVERSAMPLING_8)) - /** * @brief Ensure that USART clock state is valid. * @param __CLOCK__ USART clock state. diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart_ex.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart_ex.h index 4aff5429e9..3e83414276 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart_ex.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart_ex.h @@ -46,12 +46,12 @@ extern "C" { * @{ */ #if defined(USART_CR1_M0)&& defined(USART_CR1_M1) -#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ #define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ #elif defined(USART_CR1_M) -#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M) /*!< 9-bit long USART frame */ #endif /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h index 145c3bc05c..1c8bb706c2 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h @@ -56,7 +56,7 @@ typedef struct uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ - uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. + uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not. This parameter can be a value of @ref WWDG_EWI_Mode */ } WWDG_InitTypeDef; @@ -68,17 +68,17 @@ typedef struct typedef struct __WWDG_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ { WWDG_TypeDef *Instance; /*!< Register base address */ WWDG_InitTypeDef Init; /*!< WWDG required parameters */ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) - void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ + void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ - void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ -#endif + void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ } WWDG_HandleTypeDef; #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) @@ -87,8 +87,8 @@ typedef struct */ typedef enum { - HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */ - HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */ + HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */ + HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */ } HAL_WWDG_CallbackIDTypeDef; /** @@ -96,7 +96,7 @@ typedef enum */ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */ -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} */ @@ -260,9 +260,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h index ed6c87e1c6..c2ea323b7d 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h @@ -934,6 +934,7 @@ typedef struct #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ @@ -2491,7 +2492,7 @@ typedef struct #if defined(ADC_MULTIMODE_SUPPORT) __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { - register uint32_t data_reg_addr = 0U; + uint32_t data_reg_addr = 0U; if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { @@ -2791,9 +2792,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -2844,9 +2848,12 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -2951,7 +2958,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, @@ -3024,7 +3031,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); } @@ -3050,7 +3057,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); } @@ -3083,7 +3090,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { - register __IO uint32_t *preg = (__IO uint32_t *)((uint32_t) + __IO uint32_t *preg = (__IO uint32_t *)((uint32_t) ((uint32_t)(&ADCx->OFR1) + (Offsety*4U))); MODIFY_REG(*preg, @@ -3110,7 +3117,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); } @@ -3283,11 +3290,11 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { - register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); + uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); + uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ @@ -3613,11 +3620,11 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), - (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK))); + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } /** @@ -3714,11 +3721,11 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); - return (uint32_t) (READ_BIT(*preg, + return (uint32_t) ((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) - << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } @@ -4038,11 +4045,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) { - register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); + uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); + uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ @@ -4263,8 +4270,8 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ MODIFY_REG(ADCx->JSQR, - ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)), - (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))); + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); } /** @@ -4333,9 +4340,9 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - return (uint32_t)(READ_BIT(ADCx->JSQR, - ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))) - << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + return (uint32_t)((READ_BIT(ADCx->JSQR, + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } @@ -4817,7 +4824,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), @@ -4901,7 +4908,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) @@ -5173,7 +5180,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, @@ -5305,12 +5312,12 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to */ /* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK. */ - register uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK)); + uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK)); /* Set variable of AWD1 monitored channel according to AWD1 features */ /* and ADC channel definition: */ @@ -5319,9 +5326,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint /* - AWD1 single or all channels */ /* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of */ /* AWD2 or AWD3 selected). */ - register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS); + uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS); - register uint32_t AWD1ChannelGroup = ( ( AWD123ChannelGroup + uint32_t AWD1ChannelGroup = ( ( AWD123ChannelGroup | ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle) | (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & ((uint32_t)0x00000001U))) ) @@ -5340,9 +5347,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint /* is activated, therefore the channel monitoring value channel "3" */ /* is not not supported by this function, there is no risk of */ /* conflict. */ - register uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */ + uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */ - register uint32_t AWD23ChannelGroup = ((( AWD123ChannelGroup + uint32_t AWD23ChannelGroup = ((( AWD123ChannelGroup | ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | ((ADC_CFGR_AWD1SGL) >> ((((uint32_t)0x00000001U) >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U)) | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) @@ -5407,7 +5414,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, @@ -5471,7 +5478,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); MODIFY_REG(*preg, AWDThresholdsHighLow, @@ -5508,7 +5515,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) @@ -6202,7 +6209,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6229,7 +6236,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6256,7 +6263,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6283,7 +6290,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6310,7 +6317,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -9278,7 +9285,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), @@ -9368,7 +9375,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); return (uint32_t) (READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -9834,7 +9841,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_JOFR1_JOFFSET1, @@ -9861,7 +9868,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_JOFR1_JOFFSET1) @@ -9954,7 +9961,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), @@ -10023,7 +10030,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) @@ -10247,7 +10254,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); MODIFY_REG(*preg, ADC_HTR_HT, @@ -10270,7 +10277,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); } @@ -10493,7 +10500,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -10520,7 +10527,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_comp.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_comp.h index b0ae03d49c..d94864cbde 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_comp.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_comp.h @@ -283,7 +283,7 @@ typedef struct #define LL_COMP_OUTPUT_TIM2_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */ #define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */ #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */ -#define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ /* Note: Output redirection specific to COMP instance: COMP4 */ #define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */ #define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */ @@ -325,7 +325,7 @@ typedef struct #define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */ #define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */ #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */ -#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ /* Note: Output redirection specific to COMP instance: COMP4 */ #define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */ #define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */ @@ -384,7 +384,7 @@ typedef struct /* Note: Output redirection specific to COMP instance: COMP1, COMP2 */ #define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */ #define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */ -#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ #if defined(STM32F303xE) || defined(STM32F398xx) #define LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM20 OCREF clear (specific to COMP instance: COMP2) */ #endif diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h index d20bcfd5b1..daf139b438 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h @@ -1139,7 +1139,7 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) #if defined(EXTI_32_63_SUPPORT) /** * @brief Generate a software Interrupt Event for Lines in range 32 to 63 - * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 * resulting in an interrupt request generation. * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h index 039f42e102..c65af5ea31 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h @@ -62,7 +62,7 @@ extern "C" { #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FMC_WRAP_MODE_ENABLE)) + ((__MODE__) == FMC_WRAP_MODE_ENABLE)) #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ @@ -92,9 +92,9 @@ extern "C" { #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) + ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16)) + ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16)) #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ ((__STATE__) == FMC_NAND_ECC_ENABLE)) @@ -208,7 +208,7 @@ typedef struct This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. This parameter can be a value of @ref FMC_Continous_Clock */ -}FMC_NORSRAM_InitTypeDef; +} FMC_NORSRAM_InitTypeDef; /** * @brief FMC NORSRAM Timing parameters structure definition @@ -251,7 +251,7 @@ typedef struct uint32_t AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FMC_Access_Mode */ -}FMC_NORSRAM_TimingTypeDef; +} FMC_NORSRAM_TimingTypeDef; #endif /* FMC_BANK1 */ #if defined(FMC_BANK3) @@ -282,7 +282,7 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FMC_NAND_InitTypeDef; +} FMC_NAND_InitTypeDef; #endif #if defined(FMC_BANK3)||defined(FMC_BANK4) @@ -315,13 +315,13 @@ typedef struct write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ -}FMC_NAND_PCC_TimingTypeDef; +} FMC_NAND_PCC_TimingTypeDef; #endif /* FMC_BANK3 */ #if defined(FMC_BANK4) -/** +/** * @brief FMC PCCARD Configuration Structure definition - */ + */ typedef struct { uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. @@ -354,10 +354,10 @@ typedef struct /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank * @{ */ -#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) -#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) -#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) -#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) +#define FMC_NORSRAM_BANK1 (0x00000000U) +#define FMC_NORSRAM_BANK2 (0x00000002U) +#define FMC_NORSRAM_BANK3 (0x00000004U) +#define FMC_NORSRAM_BANK4 (0x00000006U) /** * @} */ @@ -365,8 +365,8 @@ typedef struct /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing * @{ */ -#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) -#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) +#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) /** * @} */ @@ -374,9 +374,9 @@ typedef struct /** @defgroup FMC_Memory_Type FMC Memory Type * @{ */ -#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) -#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) -#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) +#define FMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FMC_MEMORY_TYPE_NOR (0x00000008U) /** * @} */ @@ -384,9 +384,9 @@ typedef struct /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width * @{ */ -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) -#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -394,8 +394,8 @@ typedef struct /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access * @{ */ -#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) /** * @} */ @@ -403,8 +403,8 @@ typedef struct /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode * @{ */ -#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) -#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) +#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) /** * @} */ @@ -412,17 +412,17 @@ typedef struct /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity * @{ */ -#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) -#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) +#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) /** * @} */ -/** @defgroup FMC_Wrap_Mode FMC Wrap Mode +/** @defgroup FMC_Wrap_Mode FMC Wrap Mode * @{ */ -#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U) -#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U) +#define FMC_WRAP_MODE_DISABLE (0x00000000U) +#define FMC_WRAP_MODE_ENABLE (0x00000400U) /** * @} */ @@ -430,8 +430,8 @@ typedef struct /** @defgroup FMC_Wait_Timing FMC Wait Timing * @{ */ -#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) -#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) +#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS (0x00000800U) /** * @} */ @@ -439,8 +439,8 @@ typedef struct /** @defgroup FMC_Write_Operation FMC Write Operation * @{ */ -#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) -#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) +#define FMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE (0x00001000U) /** * @} */ @@ -448,8 +448,8 @@ typedef struct /** @defgroup FMC_Wait_Signal FMC Wait Signal * @{ */ -#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) -#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) +#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) /** * @} */ @@ -457,8 +457,8 @@ typedef struct /** @defgroup FMC_Extended_Mode FMC Extended Mode * @{ */ -#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) -#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) +#define FMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE (0x00004000U) /** * @} */ @@ -466,8 +466,8 @@ typedef struct /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait * @{ */ -#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) -#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) +#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) /** * @} */ @@ -475,8 +475,8 @@ typedef struct /** @defgroup FMC_Write_Burst FMC Write Burst * @{ */ -#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) -#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) +#define FMC_WRITE_BURST_DISABLE (0x00000000U) +#define FMC_WRITE_BURST_ENABLE (0x00080000U) /** * @} */ @@ -484,19 +484,19 @@ typedef struct /** @defgroup FMC_Continous_Clock FMC Continuous Clock * @{ */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) -#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) /** * @} */ - /** @defgroup FMC_Access_Mode FMC Access Mode +/** @defgroup FMC_Access_Mode FMC Access Mode * @{ */ -#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) -#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U) -#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U) -#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U) +#define FMC_ACCESS_MODE_A (0x00000000U) +#define FMC_ACCESS_MODE_B (0x10000000U) +#define FMC_ACCESS_MODE_C (0x20000000U) +#define FMC_ACCESS_MODE_D (0x30000000U) /** * @} */ @@ -514,8 +514,8 @@ typedef struct /** @defgroup FMC_NAND_Bank FMC NAND Bank * @{ */ -#define FMC_NAND_BANK2 ((uint32_t)0x00000010U) -#define FMC_NAND_BANK3 ((uint32_t)0x00000100U) +#define FMC_NAND_BANK2 (0x00000010U) +#define FMC_NAND_BANK3 (0x00000100U) /** * @} */ @@ -523,8 +523,8 @@ typedef struct /** @defgroup FMC_Wait_feature FMC Wait feature * @{ */ -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) /** * @} */ @@ -533,9 +533,9 @@ typedef struct * @{ */ #if defined(FMC_BANK4) -#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U) +#define FMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) #endif -#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U) +#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) /** * @} */ @@ -543,8 +543,8 @@ typedef struct /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width * @{ */ -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) /** * @} */ @@ -552,8 +552,8 @@ typedef struct /** @defgroup FMC_ECC FMC ECC * @{ */ -#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) -#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U) +#define FMC_NAND_ECC_DISABLE (0x00000000U) +#define FMC_NAND_ECC_ENABLE (0x00000040U) /** * @} */ @@ -561,12 +561,12 @@ typedef struct /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size * @{ */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) -#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U) -#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U) -#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U) -#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U) -#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U) +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) /** * @} */ @@ -581,9 +581,9 @@ typedef struct * @{ */ #if defined(FMC_BANK3)||defined(FMC_BANK4) -#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U) -#define FMC_IT_LEVEL ((uint32_t)0x00000010U) -#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U) +#define FMC_IT_RISING_EDGE (0x00000008U) +#define FMC_IT_LEVEL (0x00000010U) +#define FMC_IT_FALLING_EDGE (0x00000020U) #endif /* FMC_BANK3 */ /** * @} @@ -593,10 +593,10 @@ typedef struct * @{ */ #if defined(FMC_BANK3)||defined(FMC_BANK4) -#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U) -#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U) -#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U) -#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U) +#define FMC_FLAG_RISING_EDGE (0x00000001U) +#define FMC_FLAG_LEVEL (0x00000002U) +#define FMC_FLAG_FALLING_EDGE (0x00000004U) +#define FMC_FLAG_FEMPT (0x00000040U) #endif /* FMC_BANK3 */ /** * @} @@ -609,7 +609,7 @@ typedef struct /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros * @{ @@ -626,7 +626,8 @@ typedef struct * @param __BANK__ FMC_NORSRAM Bank * @retval None */ -#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN) +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FMC_BCRx_MBKEN) /** * @brief Disable the NORSRAM device access. @@ -634,7 +635,8 @@ typedef struct * @param __BANK__ FMC_NORSRAM Bank * @retval None */ -#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN) +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FMC_BCRx_MBKEN) /** * @} @@ -643,9 +645,9 @@ typedef struct #if defined(FMC_BANK3) /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ + * @brief macros to handle NAND device enable/disable + * @{ + */ /** * @brief Enable the NAND device access. @@ -672,21 +674,21 @@ typedef struct #if defined(FMC_BANK4) /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros - * @brief macros to handle PCCARD read/write operations - * @{ - */ + * @brief macros to handle PCCARD read/write operations + * @{ + */ /** * @brief Enable the PCCARD device access. - * @param __INSTANCE__ FMC_PCCARD Instance + * @param __INSTANCE__ FMC_PCCARD Instance * @retval None - */ + */ #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN) /** * @brief Disable the PCCARD device access. - * @param __INSTANCE__ FMC_PCCARD Instance + * @param __INSTANCE__ FMC_PCCARD Instance * @retval None - */ + */ #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN) /** * @} @@ -725,7 +727,7 @@ typedef struct * @retval None */ #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) + ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) /** * @brief Get flag status of the NAND device. @@ -770,50 +772,50 @@ typedef struct /** * @brief Enable the PCCARD device interrupt. - * @param __INSTANCE__ FMC_PCCARD instance - * @param __INTERRUPT__ FMC_PCCARD interrupt + * @param __INSTANCE__ FMC_PCCARD instance + * @param __INTERRUPT__ FMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None - */ + */ #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) /** * @brief Disable the PCCARD device interrupt. - * @param __INSTANCE__ FMC_PCCARD instance - * @param __INTERRUPT__ FMC_PCCARD interrupt + * @param __INSTANCE__ FMC_PCCARD instance + * @param __INTERRUPT__ FMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None - */ -#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) + */ +#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) /** * @brief Get flag status of the PCCARD device. - * @param __INSTANCE__ FMC_PCCARD instance + * @param __INSTANCE__ FMC_PCCARD instance * @param __FLAG__ FMC_PCCARD flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. * @retval The state of FLAG (SET or RESET). */ #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) /** * @brief Clear flag status of the PCCARD device. - * @param __INSTANCE__ FMC_PCCARD instance + * @param __INSTANCE__ FMC_PCCARD instance * @param __FLAG__ FMC_PCCARD flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. * @retval None */ #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) @@ -843,10 +845,14 @@ typedef struct /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); /** * @} */ @@ -872,8 +878,10 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic * @{ */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -884,7 +892,8 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); /** * @} */ @@ -901,9 +910,12 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u * @{ */ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init); -HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h index ae22beab35..ce85fbdb72 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h @@ -2000,8 +2000,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src) { - register uint32_t shift = ((3U * ADCTrig) & 0x1FU); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + + uint32_t shift = ((3U * ADCTrig) & 0x1FU); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + REG_OFFSET_TAB_ADCxR[ADCTrig])); MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); WRITE_REG(*pReg, Src); @@ -2033,7 +2033,7 @@ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCT */ __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update) { - register uint32_t shift = ((3U * ADCTrig) & 0x1FU); + uint32_t shift = ((3U * ADCTrig) & 0x1FU); MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); } @@ -2059,7 +2059,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t A */ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { - register const uint32_t shift = ((3U * ADCTrig) & 0x1FU); + const uint32_t shift = ((3U * ADCTrig) & 0x1FU); return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift); } @@ -2276,7 +2276,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) { - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + REG_OFFSET_TAB_ADCxR[ADCTrig])); WRITE_REG(*pReg, Src); } @@ -2493,7 +2493,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT */ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + REG_OFFSET_TAB_ADCxR[ADCTrig])); return (*pReg); @@ -2635,8 +2635,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler); } @@ -2664,8 +2664,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC)); } @@ -2691,8 +2691,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode); } @@ -2717,8 +2717,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT))); } @@ -2741,8 +2741,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_HALF); } @@ -2762,8 +2762,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_HALF); } @@ -2783,8 +2783,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL); } @@ -2804,8 +2804,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); } @@ -2825,8 +2825,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); } @@ -2846,8 +2846,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL); } @@ -2868,8 +2868,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx */ __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM); } @@ -2889,8 +2889,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM); } @@ -2910,8 +2910,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL); } @@ -2937,8 +2937,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx */ __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig); } @@ -2962,8 +2962,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC)); } @@ -2986,8 +2986,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_PREEN); } @@ -3007,8 +3007,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_PREEN); } @@ -3028,8 +3028,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL); } @@ -3072,8 +3072,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]); } @@ -3113,8 +3113,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]); } @@ -3151,8 +3151,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer])); } @@ -3188,8 +3188,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]); } @@ -3207,8 +3207,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3227,8 +3227,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3247,8 +3247,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL); } @@ -3278,10 +3278,10 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIM __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); - register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); + uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); } @@ -3307,10 +3307,10 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); - register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); + uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); } @@ -3337,8 +3337,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); } @@ -3359,8 +3359,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); } @@ -3382,8 +3382,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); } @@ -3404,8 +3404,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MPER_MPER)); } @@ -3427,8 +3427,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); } @@ -3449,8 +3449,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MREP_MREP)); } @@ -3474,8 +3474,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); } @@ -3498,8 +3498,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); } @@ -3523,8 +3523,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); } @@ -3547,8 +3547,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); } @@ -3572,8 +3572,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); } @@ -3596,8 +3596,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); } @@ -3621,8 +3621,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); } @@ -3645,8 +3645,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); } @@ -3732,8 +3732,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + REG_OFFSET_TAB_TIMER[iTimer])); WRITE_REG(*pReg, ResetTrig); } @@ -3812,8 +3812,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3832,8 +3832,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3852,8 +3852,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3940,8 +3940,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit, uint32_t CaptureTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); WRITE_REG(*pReg, CaptureTrig); } @@ -4026,8 +4026,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); return (READ_REG(*pReg)); } @@ -4046,8 +4046,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4066,8 +4066,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4086,8 +4086,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL); @@ -4131,8 +4131,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); } @@ -4172,8 +4172,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); } @@ -4193,8 +4193,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4214,8 +4214,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4234,8 +4234,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL); } @@ -4264,8 +4264,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, Faults); } @@ -4294,8 +4294,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, Faults); } @@ -4324,8 +4324,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); @@ -4346,8 +4346,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); } @@ -4376,7 +4376,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption) { - register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); + uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer); } @@ -4402,7 +4402,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); + uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer); } @@ -4489,8 +4489,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + (4U * iTimer))); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + (4U * iTimer))); WRITE_REG(*pReg, Registers); } @@ -4511,8 +4511,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); } @@ -4533,8 +4533,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HR */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); } @@ -4592,9 +4592,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIM */ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4649,9 +4649,9 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4695,9 +4695,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t LatchStatus) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4738,9 +4738,9 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4773,8 +4773,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, */ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); } @@ -4802,8 +4802,8 @@ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, u */ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); } @@ -4830,8 +4830,8 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); } @@ -4851,8 +4851,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); } @@ -4871,8 +4871,8 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTR)); } @@ -4894,8 +4894,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); } @@ -4916,8 +4916,8 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); } @@ -4937,8 +4937,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); } @@ -4957,8 +4957,8 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); } @@ -4980,8 +4980,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); } @@ -5002,8 +5002,8 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); } @@ -5022,8 +5022,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRLK); } @@ -5042,8 +5042,8 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRSLK); } @@ -5062,8 +5062,8 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFLK); } @@ -5082,8 +5082,8 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFSLK); } @@ -5118,8 +5118,8 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); } @@ -5158,8 +5158,8 @@ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, */ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); } @@ -5194,8 +5194,8 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); } @@ -5226,8 +5226,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); } @@ -5254,8 +5254,8 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); } @@ -5293,8 +5293,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); } @@ -5329,8 +5329,8 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); } @@ -5458,8 +5458,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, SetSrc); } @@ -5578,8 +5578,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5699,8 +5699,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, ResetSrc); } @@ -5819,8 +5819,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5862,8 +5862,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); @@ -5892,8 +5892,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, */ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5920,8 +5920,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -5950,8 +5950,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput]))); } @@ -5978,8 +5978,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6009,8 +6009,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6037,8 +6037,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6070,8 +6070,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6100,8 +6100,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6130,8 +6130,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6158,8 +6158,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6188,8 +6188,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6216,8 +6216,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6245,8 +6245,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1STAT_Pos); @@ -6283,8 +6283,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */ }; - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); SET_BIT(*pReg, HRTIM_SET1R_SST); } @@ -6311,8 +6311,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1CPY_Pos); @@ -6392,8 +6392,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t O */ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); @@ -6432,8 +6432,8 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u */ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6470,8 +6470,8 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u */ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6509,8 +6509,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Even */ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6545,8 +6545,8 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve */ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6585,8 +6585,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6623,8 +6623,8 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6656,8 +6656,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6687,8 +6687,8 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve */ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6728,7 +6728,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6767,7 +6767,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event */ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6)); return (READ_BIT(HRTIMx->sCommonRegs.EECR3, (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6839,8 +6839,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]), (Configuration << REG_SHIFT_TAB_FLTxE[iFault])); @@ -6868,8 +6868,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, */ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6894,8 +6894,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6922,8 +6922,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fau */ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6948,8 +6948,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6990,8 +6990,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7030,8 +7030,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); @@ -7086,8 +7086,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7110,8 +7110,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) */ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7134,8 +7134,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) */ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7158,8 +7158,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == (HRTIM_IER_FLT1)) ? 1UL : 0UL); @@ -7856,8 +7856,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MUPD); } @@ -7878,8 +7878,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL); @@ -7901,8 +7901,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MREP); @@ -7924,8 +7924,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL); @@ -7947,8 +7947,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP1); } @@ -7969,8 +7969,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL); @@ -7992,8 +7992,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP2); } @@ -8014,8 +8014,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL); @@ -8037,8 +8037,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP3); } @@ -8059,8 +8059,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL); @@ -8082,8 +8082,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP4); } @@ -8104,8 +8104,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL); @@ -8125,8 +8125,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); } @@ -8145,8 +8145,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL); @@ -8166,8 +8166,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); } @@ -8186,8 +8186,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL); @@ -8207,8 +8207,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET1C); } @@ -8227,8 +8227,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL); @@ -8248,8 +8248,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST1C); } @@ -8268,8 +8268,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL); @@ -8289,8 +8289,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET2C); } @@ -8309,8 +8309,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL); @@ -8330,8 +8330,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST2C); } @@ -8350,8 +8350,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL); @@ -8371,8 +8371,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RSTC); } @@ -8391,8 +8391,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL); @@ -8412,8 +8412,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC); } @@ -8432,8 +8432,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL); @@ -8760,8 +8760,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8782,8 +8782,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8804,8 +8804,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL); @@ -8827,8 +8827,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8849,8 +8849,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer */ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8871,8 +8871,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL); @@ -8894,8 +8894,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8916,8 +8916,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8938,8 +8938,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL); @@ -8961,8 +8961,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8983,8 +8983,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -9005,8 +9005,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL); @@ -9028,8 +9028,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -9050,8 +9050,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -9072,8 +9072,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL); @@ -9095,8 +9095,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -9117,8 +9117,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -9139,8 +9139,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL); @@ -9160,8 +9160,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9180,8 +9180,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9200,8 +9200,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL); @@ -9221,8 +9221,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9241,8 +9241,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9261,8 +9261,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL); @@ -9282,8 +9282,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9302,8 +9302,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9322,8 +9322,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL); @@ -9343,8 +9343,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9363,8 +9363,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9383,8 +9383,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL); @@ -9404,8 +9404,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9424,8 +9424,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9444,8 +9444,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL); @@ -9465,8 +9465,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9485,8 +9485,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9505,8 +9505,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL); @@ -9526,8 +9526,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9546,8 +9546,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer */ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9566,8 +9566,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL); @@ -9587,8 +9587,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9607,8 +9607,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9627,8 +9627,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL); @@ -9691,8 +9691,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9713,8 +9713,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9735,8 +9735,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL); @@ -9758,8 +9758,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9780,8 +9780,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9802,8 +9802,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL); @@ -9825,8 +9825,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9847,8 +9847,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9869,8 +9869,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL); @@ -9892,8 +9892,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9914,8 +9914,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9936,8 +9936,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL); @@ -9959,8 +9959,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9981,8 +9981,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -10003,8 +10003,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL); @@ -10026,8 +10026,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -10048,8 +10048,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -10070,8 +10070,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL); @@ -10091,8 +10091,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -10111,8 +10111,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -10131,8 +10131,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL); @@ -10152,8 +10152,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10172,8 +10172,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10192,8 +10192,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL); @@ -10213,8 +10213,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10233,8 +10233,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10253,8 +10253,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL); @@ -10274,8 +10274,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10294,8 +10294,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10314,8 +10314,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL); @@ -10335,8 +10335,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10355,8 +10355,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10375,8 +10375,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL); @@ -10396,8 +10396,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10416,8 +10416,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10436,8 +10436,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL); @@ -10457,8 +10457,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10477,8 +10477,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10497,8 +10497,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL); @@ -10518,8 +10518,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10538,8 +10538,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10558,8 +10558,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_opamp.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_opamp.h index 086168c67c..08fe062511 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_opamp.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_opamp.h @@ -160,8 +160,8 @@ typedef struct */ #define LL_OPAMP_INPUT_NONINVERT_IO0 (OPAMP_CSR_VPSEL) /*!< OPAMP non inverting input connected to GPIO pin (pin PA1 for OPAMP1, pin PA7 for OPAMP2, pin PB0 for OPAMP3, pin PB13 for OPAMP4) */ #define LL_OPAMP_INPUT_NONINVERT_IO1 (0x00000000) /*!< OPAMP non inverting input connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */ -#define LL_OPAMP_INPUT_NONINVERT_IO2 (OPAMP_CSR_VPSEL_1) /*!< OPAMP non inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PB11 for OPAMP4) */ -#define LL_OPAMP_INPUT_NONINVERT_IO3 (OPAMP_CSR_VPSEL_0) /*!< OPAMP non inverting input connected to GPIO pin (pin PA5 for OPAMP1, pin PB14 for OPAMP2, pin PA5 for OPAMP3, pin PA4 for OPAMP4) */ +#define LL_OPAMP_INPUT_NONINVERT_IO2 (OPAMP_CSR_VPSEL_1) /*!< OPAMP non inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PA4 for OPAMP4) */ +#define LL_OPAMP_INPUT_NONINVERT_IO3 (OPAMP_CSR_VPSEL_0) /*!< OPAMP non inverting input connected to GPIO pin (pin PA5 for OPAMP1, pin PB14 for OPAMP2, pin PA5 for OPAMP3, pin PB11 for OPAMP4) */ #define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */ #define LL_OPAMP_INPUT_NONINV_DAC1_CH2 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */ /** @@ -504,7 +504,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t */ __STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx) { - register uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL); + uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL); /* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting */ /* input not connected. */ @@ -689,7 +689,7 @@ __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uin */ __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) { - register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); + uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); return (CalibrationSelection | (((CalibrationSelection & OPAMP_CSR_CALSEL) == 0UL) ? OPAMP_CSR_TRIMOFFSETN : OPAMP_CSR_TRIMOFFSETP)); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h index d4f1e00a2d..988869d514 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h @@ -132,6 +132,10 @@ typedef struct #if !defined (LSI_VALUE) #define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h index d191d95b24..3e002dee5f 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h @@ -1296,7 +1296,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp = 0U; + uint32_t temp = 0U; temp = Format12_24 | \ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ @@ -1324,7 +1324,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; + uint32_t temp = 0U; temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ @@ -1626,7 +1626,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) { - register uint32_t temp = 0U; + uint32_t temp = 0U; temp = (WeekDay << RTC_DR_WDU_Pos) | \ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ @@ -1654,7 +1654,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; + uint32_t temp = 0U; temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ @@ -1954,7 +1954,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp = 0U; + uint32_t temp = 0U; temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ @@ -2320,7 +2320,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp = 0U; + uint32_t temp = 0U; temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ @@ -3010,7 +3010,7 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) { - register uint32_t tmp = 0U; + uint32_t tmp = 0U; tmp = (uint32_t)(&(RTCx->BKP0R)); tmp += (BackupRegister * 4U); @@ -3062,7 +3062,7 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe */ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) { - register uint32_t tmp = 0U; + uint32_t tmp = 0U; tmp = (uint32_t)(&(RTCx->BKP0R)); tmp += (BackupRegister * 4U); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h index 5684990de6..2d475f9271 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h @@ -266,8 +266,8 @@ typedef struct /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold * @{ */ -#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ -#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */ /** * @} */ @@ -848,8 +848,8 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) */ __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) { - register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); - register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); return (Ssm | Ssoe); } @@ -1501,10 +1501,10 @@ typedef struct /** @defgroup I2S_LL_EC_DATA_FORMAT Data format * @{ */ -#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ -#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ -#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ -#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */ /** * @} */ @@ -1839,7 +1839,7 @@ __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) } /** - * @brief Enable the master clock ouput (Pin MCK) + * @brief Enable the master clock output (Pin MCK) * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock * @param SPIx SPI Instance * @retval None @@ -1850,7 +1850,7 @@ __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) } /** - * @brief Disable the master clock ouput (Pin MCK) + * @brief Disable the master clock output (Pin MCK) * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock * @param SPIx SPI Instance * @retval None @@ -1861,7 +1861,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) } /** - * @brief Check if the master clock ouput (Pin MCK) is enabled + * @brief Check if the master clock output (Pin MCK) is enabled * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock * @param SPIx SPI Instance * @retval State of bit (1 or 0). diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h index 2c5fd2e0aa..b15432be7e 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h @@ -240,13 +240,14 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ - uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; @@ -602,8 +603,8 @@ typedef struct */ #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR1, TIM_CR1_DIR | TIM_CR1_CMS)); + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; } /** @@ -1685,7 +1695,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_SetRepetitionCounter * @param TIMx Timer instance - * @param RepetitionCounter between Min_Data=0 and Max_Data=255 + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. * @retval None */ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) @@ -1730,6 +1740,16 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); } +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + #endif /* TIM_CR1_UIFREMAP */ /** * @} @@ -1970,8 +1990,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); @@ -2031,8 +2051,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } @@ -2086,8 +2106,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } @@ -2121,7 +2141,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2154,7 +2174,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -2192,7 +2212,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann */ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); } @@ -2225,7 +2245,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); } @@ -2260,8 +2280,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2296,8 +2316,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2332,9 +2352,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2368,8 +2388,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha */ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2403,8 +2423,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2438,9 +2458,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2477,8 +2497,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2514,8 +2534,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2553,9 +2573,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2873,8 +2893,8 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G */ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), @@ -2901,8 +2921,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 */ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2925,8 +2945,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2951,8 +2971,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch */ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2976,8 +2996,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -3014,8 +3034,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -3051,8 +3071,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui */ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -3080,7 +3100,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]); } @@ -3108,7 +3128,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_usart.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_usart.h index eb21c9c780..186e8f546b 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_usart.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_usart.h @@ -66,37 +66,44 @@ typedef struct uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. - This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref USART_LL_EC_STOPBITS. - This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref USART_LL_EC_PARITY. - This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_DIRECTION. - This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_HWCONTROL. - This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. - This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ } LL_USART_InitTypeDef; @@ -115,20 +122,23 @@ typedef struct uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. This parameter can be a value of @ref USART_LL_EC_POLARITY. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). For more details, refer to description of this function. */ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref USART_LL_EC_PHASE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). For more details, refer to description of this function. */ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function. */ } LL_USART_ClockInitTypeDef; @@ -553,7 +563,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) * @brief USART enabled in STOP Mode. * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that * USART clock selection is HSI or LSE in RCC. - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_EnableInStopMode * @param USARTx USART Instance @@ -567,7 +577,7 @@ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) /** * @brief USART disabled in STOP Mode. * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_DisableInStopMode * @param USARTx USART Instance @@ -580,7 +590,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) /** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode * @param USARTx USART Instance @@ -827,7 +837,7 @@ __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) /** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput * @param USARTx USART Instance @@ -844,7 +854,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 /** * @brief Retrieve Clock pulse of the last data bit output configuration * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput * @param USARTx USART Instance @@ -859,7 +869,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) /** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_SetClockPhase * @param USARTx USART Instance @@ -875,7 +885,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc /** * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_GetClockPhase * @param USARTx USART Instance @@ -890,7 +900,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) /** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_SetClockPolarity * @param USARTx USART Instance @@ -906,7 +916,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C /** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_GetClockPolarity * @param USARTx USART Instance @@ -921,7 +931,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) /** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function @@ -949,7 +959,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, /** * @brief Enable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput * @param USARTx USART Instance @@ -962,7 +972,7 @@ __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Disable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput * @param USARTx USART Instance @@ -975,7 +985,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput * @param USARTx USART Instance @@ -1196,7 +1206,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx) /** * @brief Enable Auto Baud-Rate Detection - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate * @param USARTx USART Instance @@ -1209,7 +1219,7 @@ __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) /** * @brief Disable Auto Baud-Rate Detection - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate * @param USARTx USART Instance @@ -1222,7 +1232,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) /** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud * @param USARTx USART Instance @@ -1235,7 +1245,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) /** * @brief Set Auto Baud-Rate mode bits - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode * @param USARTx USART Instance @@ -1253,7 +1263,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_ /** * @brief Return Auto Baud-Rate mode - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode * @param USARTx USART Instance @@ -1360,7 +1370,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx) /** * @brief Enable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl * @param USARTx USART Instance @@ -1373,7 +1383,7 @@ __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl * @param USARTx USART Instance @@ -1386,7 +1396,7 @@ __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Enable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl * @param USARTx USART Instance @@ -1399,7 +1409,7 @@ __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl * @param USARTx USART Instance @@ -1412,7 +1422,7 @@ __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n * CR3 CTSE LL_USART_SetHWFlowCtrl @@ -1431,7 +1441,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard /** * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n * CR3 CTSE LL_USART_GetHWFlowCtrl @@ -1515,7 +1525,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) /** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUS LL_USART_SetWKUPType * @param USARTx USART Instance @@ -1532,7 +1542,7 @@ __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) /** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUS LL_USART_GetWKUPType * @param USARTx USART Instance @@ -1566,7 +1576,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph uint32_t BaudRate) { uint32_t usartdiv; - register uint32_t brrtemp; + uint32_t brrtemp; if (OverSampling == LL_USART_OVERSAMPLING_8) { @@ -1596,8 +1606,8 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph */ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) { - register uint32_t usartdiv; - register uint32_t brrresult = 0x0U; + uint32_t usartdiv; + uint32_t brrresult = 0x0U; usartdiv = USARTx->BRR; @@ -1679,7 +1689,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) /** * @brief Enable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_EnableIrda * @param USARTx USART Instance @@ -1692,7 +1702,7 @@ __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) /** * @brief Disable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_DisableIrda * @param USARTx USART Instance @@ -1705,7 +1715,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) /** * @brief Indicate if IrDA mode is enabled - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_IsEnabledIrda * @param USARTx USART Instance @@ -1718,7 +1728,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) /** * @brief Configure IrDA Power Mode (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode * @param USARTx USART Instance @@ -1734,7 +1744,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P /** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode * @param USARTx USART Instance @@ -1750,7 +1760,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) /** * @brief Set Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler * @param USARTx USART Instance @@ -1765,7 +1775,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P /** * @brief Return Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler * @param USARTx USART Instance @@ -1786,7 +1796,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) /** * @brief Enable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK * @param USARTx USART Instance @@ -1799,7 +1809,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Disable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK * @param USARTx USART Instance @@ -1812,7 +1822,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard NACK transmission is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK * @param USARTx USART Instance @@ -1825,7 +1835,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Enable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_EnableSmartcard * @param USARTx USART Instance @@ -1838,7 +1848,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) /** * @brief Disable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_DisableSmartcard * @param USARTx USART Instance @@ -1851,7 +1861,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard mode is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard * @param USARTx USART Instance @@ -1864,7 +1874,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) /** * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. * In transmission mode, it specifies the number of automatic retransmission retries, before @@ -1883,7 +1893,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, /** * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount * @param USARTx USART Instance @@ -1897,7 +1907,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR /** * @brief Set Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler * @param USARTx USART Instance @@ -1912,7 +1922,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler * @param USARTx USART Instance @@ -1926,7 +1936,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) /** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime * @param USARTx USART Instance @@ -1941,7 +1951,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime * @param USARTx USART Instance @@ -1962,7 +1972,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) /** * @brief Enable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex * @param USARTx USART Instance @@ -1975,7 +1985,7 @@ __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Disable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex * @param USARTx USART Instance @@ -1988,7 +1998,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex * @param USARTx USART Instance @@ -2009,7 +2019,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) /** * @brief Set LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen * @param USARTx USART Instance @@ -2025,7 +2035,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 /** * @brief Return LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen * @param USARTx USART Instance @@ -2040,7 +2050,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) /** * @brief Enable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_EnableLIN * @param USARTx USART Instance @@ -2053,7 +2063,7 @@ __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) /** * @brief Disable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_DisableLIN * @param USARTx USART Instance @@ -2066,7 +2076,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) /** * @brief Indicate if LIN mode is enabled - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN * @param USARTx USART Instance @@ -2087,7 +2097,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) /** * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime * @param USARTx USART Instance @@ -2101,7 +2111,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32 /** * @brief Return DEDT (Driver Enable De-Assertion Time) - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime * @param USARTx USART Instance @@ -2114,7 +2124,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) /** * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime * @param USARTx USART Instance @@ -2128,7 +2138,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t /** * @brief Return DEAT (Driver Enable Assertion Time) - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime * @param USARTx USART Instance @@ -2141,7 +2151,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) /** * @brief Enable Driver Enable (DE) Mode - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_EnableDEMode * @param USARTx USART Instance @@ -2154,7 +2164,7 @@ __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) /** * @brief Disable Driver Enable (DE) Mode - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_DisableDEMode * @param USARTx USART Instance @@ -2167,7 +2177,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) /** * @brief Indicate if Driver Enable (DE) Mode is enabled - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode * @param USARTx USART Instance @@ -2180,7 +2190,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) /** * @brief Select Driver Enable Polarity - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity * @param USARTx USART Instance @@ -2196,7 +2206,7 @@ __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_ /** * @brief Return Driver Enable Polarity - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity * @param USARTx USART Instance @@ -2260,7 +2270,7 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the USART in Synchronous mode. - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2299,7 +2309,7 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also set the UART/USART in LIN mode. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function @@ -2340,7 +2350,7 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - IREN bit in the USART_CR3 register, * This function also sets the UART/USART in Half Duplex mode. - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2380,7 +2390,7 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) * This function also configures Stop bits to 1.5 bits and * sets the USART in Smartcard mode (SCEN bit). * Clock Output is also enabled (CLKEN). - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2423,7 +2433,7 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the UART/USART in IRDA mode (IREN bit). - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2591,7 +2601,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) /** * @brief Check if the USART LIN Break Detection Flag is set or not - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD * @param USARTx USART Instance @@ -2604,7 +2614,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) /** * @brief Check if the USART CTS interrupt Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS * @param USARTx USART Instance @@ -2617,7 +2627,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) /** * @brief Check if the USART CTS Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS * @param USARTx USART Instance @@ -2641,7 +2651,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) /** * @brief Check if the USART End Of Block Flag is set or not - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB * @param USARTx USART Instance @@ -2654,7 +2664,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) /** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE * @param USARTx USART Instance @@ -2667,7 +2677,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) /** * @brief Check if the USART Auto-Baud Rate Flag is set or not - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR * @param USARTx USART Instance @@ -2724,7 +2734,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) /** * @brief Check if the USART Wake Up from stop mode Flag is set or not - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP * @param USARTx USART Instance @@ -2826,7 +2836,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) /** * @brief Clear LIN Break Detection Flag - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD * @param USARTx USART Instance @@ -2839,7 +2849,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) /** * @brief Clear CTS Interrupt Flag - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS * @param USARTx USART Instance @@ -2863,7 +2873,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) /** * @brief Clear End Of Block Flag - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB * @param USARTx USART Instance @@ -2887,7 +2897,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) /** * @brief Clear Wake Up from stop mode Flag - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP * @param USARTx USART Instance @@ -2985,7 +2995,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) /** * @brief Enable End Of Block Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB * @param USARTx USART Instance @@ -2998,7 +3008,7 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) /** * @brief Enable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD * @param USARTx USART Instance @@ -3026,7 +3036,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Enable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS * @param USARTx USART Instance @@ -3039,7 +3049,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) /** * @brief Enable Wake Up from Stop Mode Interrupt - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP * @param USARTx USART Instance @@ -3130,7 +3140,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) /** * @brief Disable End Of Block Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB * @param USARTx USART Instance @@ -3143,7 +3153,7 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) /** * @brief Disable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD * @param USARTx USART Instance @@ -3171,7 +3181,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Disable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS * @param USARTx USART Instance @@ -3184,7 +3194,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) /** * @brief Disable Wake Up from Stop Mode Interrupt - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP * @param USARTx USART Instance @@ -3275,7 +3285,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) /** * @brief Check if the USART End Of Block Interrupt is enabled or disabled. - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB * @param USARTx USART Instance @@ -3288,7 +3298,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) /** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD * @param USARTx USART Instance @@ -3312,7 +3322,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) /** * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS * @param USARTx USART Instance @@ -3325,7 +3335,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) /** * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP * @param USARTx USART Instance @@ -3456,7 +3466,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx */ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) { @@ -3536,7 +3546,7 @@ __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Valu /** * @brief Request an Automatic Baud Rate measurement on next received data frame - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate * @param USARTx USART Instance @@ -3584,7 +3594,7 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) /** * @brief Request a Transmit data flush - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush * @param USARTx USART Instance diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h index 27940510fb..7d0d1754d3 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h @@ -249,6 +249,9 @@ void LL_mDelay(uint32_t Delay); */ void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +#if defined(FLASH_ACR_LATENCY) +ErrorStatus LL_SetFlashLatency(uint32_t Frequency); +#endif /* FLASH_ACR_LATENCY */ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, diff --git a/system/Drivers/STM32F3xx_HAL_Driver/README.md b/system/Drivers/STM32F3xx_HAL_Driver/README.md index 11241447d4..7bbe19c61e 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/README.md +++ b/system/Drivers/STM32F3xx_HAL_Driver/README.md @@ -41,6 +41,7 @@ HAL Driver F3 | CMSIS Device F3 | CMSIS Core | Was delivered in the full MCU pac Tag v1.5.2 | Tag v2.3.3 | Tag v4.5_cm4 | Tag v1.10.0 (and following, if any, till next new tag) Tag v1.5.3 | Tag v2.3.4 | Tag v5.4.0_cm4 | Tag v1.11.0 (and following, if any, till next new tag) Tag v1.5.4 | Tag v2.3.4 | Tag v5.4.0_cm4 | Tag v1.11.1 (and following, if any, till next new tag) +Tag v1.5.5 | Tag v2.3.5 | Tag v5.4.0_cm4 | Tag v1.11.2 (and following, if any, till next new tag) The full **STM32CubeF3** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF3). diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html index 17a12a8065..1e93633096 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html @@ -5,7 +5,7 @@ Release Notes for STM32F3xx HAL Drivers -