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Update SystemClock_Config
Signed-off-by: Frederic.Pillon <[email protected]>
1 parent c5394fd commit 9ac7db1

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+11
-22
lines changed

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+11
-22
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variants/STEVAL_MKSBOX1V1/variant.cpp

Lines changed: 11 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -148,20 +148,15 @@ WEAK void SystemClock_Config(void)
148148
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) {
149149
Error_Handler();
150150
}
151-
/* Configure LSE Drive Capability */
152-
HAL_PWR_EnableBkUpAccess();
153-
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
154151
/* Initializes the CPU, AHB and APB busses clocks */
155-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
156-
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
157-
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
158-
RCC_OscInitStruct.MSICalibrationValue = 0;
159-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
152+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
153+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
154+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
160155
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
161-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
162-
RCC_OscInitStruct.PLL.PLLM = 1;
156+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
157+
RCC_OscInitStruct.PLL.PLLM = 4;
163158
RCC_OscInitStruct.PLL.PLLN = 60;
164-
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
159+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV5;
165160
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
166161
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
167162
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
@@ -178,20 +173,14 @@ WEAK void SystemClock_Config(void)
178173
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
179174
Error_Handler();
180175
}
181-
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
182-
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
183-
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
184-
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
185-
PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
186-
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV2;
187-
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
188-
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
189-
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
176+
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_USB
177+
| RCC_PERIPHCLK_SDMMC1;
178+
PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK;
179+
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
180+
PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLLP;
190181
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
191182
Error_Handler();
192183
}
193-
/* Enable MSI Auto calibration */
194-
HAL_RCCEx_EnableMSIPLLMode();
195184
}
196185

197186
#ifdef __cplusplus

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