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Merge pull request #2117 from fpistm/feat-nucleo-h503rb
variant(H5): add generic H503RB and Nucelo H503RB
2 parents d07fcaf + 4677fab commit 1409baa

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‎README.md‎

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Original file line numberDiff line numberDiff line change
@@ -126,6 +126,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :green_heart: | STM32G0B1RE | [Nucleo G0B1RE](https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html) | *2.1.0* | |
127127
| :green_heart: | STM32G431RB | [Nucleo G431RB](https://www.st.com/en/evaluation-tools/nucleo-g431rb.html) | *1.7.0* | |
128128
| :green_heart: | STM32G474RE | [Nucleo G474RE](https://www.st.com/en/evaluation-tools/nucleo-g474re.html) | *1.7.0* | |
129+
| :yellow_heart: | STM32H503RB | [Nucleo H503RB](https://www.st.com/en/evaluation-tools/nucleo-h503rb.html) | **2.7.0** | |
129130
| :green_heart: | STM32L010RB | [Nucleo L010RB](https://www.st.com/en/evaluation-tools/nucleo-l010rb.html) | *2.1.0* | |
130131
| :green_heart: | STM32L053R8 | [Nucleo L053R8](http://www.st.com/en/evaluation-tools/nucleo-l053r8.html) | *0.1.0* | |
131132
| :green_heart: | STM32L073RZ | [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) | *1.4.0* | |
@@ -523,6 +524,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
523524

524525
| Status | Device(s) | Name | Release | Notes |
525526
| :----: | :-------: | ---- | :-----: | :---- |
527+
| :yellow_heart: | STM32H503RB | Generic Board | **2.7.0** | |
526528
| :green_heart: | STM32H563IIKxQ | Generic Board | *2.6.0* | |
527529
| :green_heart: | STM32H563ZG<br>STM32H563ZI | Generic Board | *2.6.0* | |
528530
| :green_heart: | STM32H573IIKxQ | Generic Board | *2.6.0* | |

‎boards.txt‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -501,6 +501,19 @@ Nucleo_64.menu.pnum.NUCLEO_G474RE.build.series=STM32G4xx
501501
Nucleo_64.menu.pnum.NUCLEO_G474RE.build.product_line=STM32G474xx
502502
Nucleo_64.menu.pnum.NUCLEO_G474RE.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET
503503

504+
# NUCLEO H503RB
505+
Nucleo_64.menu.pnum.NUCLEO_H503RB=Nucleo H503RB
506+
Nucleo_64.menu.pnum.NUCLEO_H503RB.node=NOD_H503RB
507+
Nucleo_64.menu.pnum.NUCLEO_H503RB.upload.maximum_size=131072
508+
Nucleo_64.menu.pnum.NUCLEO_H503RB.upload.maximum_data_size=32768
509+
Nucleo_64.menu.pnum.NUCLEO_H503RB.build.mcu=cortex-m33
510+
Nucleo_64.menu.pnum.NUCLEO_H503RB.build.fpu=-mfpu=fpv4-sp-d16
511+
Nucleo_64.menu.pnum.NUCLEO_H503RB.build.float-abi=-mfloat-abi=hard
512+
Nucleo_64.menu.pnum.NUCLEO_H503RB.build.board=NUCLEO_H503RB
513+
Nucleo_64.menu.pnum.NUCLEO_H503RB.build.series=STM32H5xx
514+
Nucleo_64.menu.pnum.NUCLEO_H503RB.build.product_line=STM32H503xx
515+
Nucleo_64.menu.pnum.NUCLEO_H503RB.build.variant=STM32H5xx/H503RBT
516+
504517
# NUCLEO_L010RB board
505518
Nucleo_64.menu.pnum.NUCLEO_L010RB=Nucleo L010RB
506519
Nucleo_64.menu.pnum.NUCLEO_L010RB.node=NODE_L010RB
@@ -7265,6 +7278,14 @@ GenH5.build.flash_offset=0x0
72657278
GenH5.upload.maximum_size=0
72667279
GenH5.upload.maximum_data_size=0
72677280

7281+
# Generic H503RBTx
7282+
GenH5.menu.pnum.GENERIC_H503RBTX=Generic H503RBTx
7283+
GenH5.menu.pnum.GENERIC_H503RBTX.upload.maximum_size=131072
7284+
GenH5.menu.pnum.GENERIC_H503RBTX.upload.maximum_data_size=32768
7285+
GenH5.menu.pnum.GENERIC_H503RBTX.build.board=GENERIC_H503RBTX
7286+
GenH5.menu.pnum.GENERIC_H503RBTX.build.product_line=STM32H503xx
7287+
GenH5.menu.pnum.GENERIC_H503RBTX.build.variant=STM32H5xx/H503RBT
7288+
72687289
# Generic H563IIKxQ
72697290
GenH5.menu.pnum.GENERIC_H563IIKXQ=Generic H563IIKxQ
72707291
GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152

‎cmake/boards_db.cmake‎

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Original file line numberDiff line numberDiff line change
@@ -71230,6 +71230,91 @@ target_compile_options(GENERIC_G4A1VETX_xusb_HSFS INTERFACE
7123071230
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
7123171231
)
7123271232

71233+
# GENERIC_H503RBTX
71234+
# -----------------------------------------------------------------------------
71235+
71236+
set(GENERIC_H503RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503RBT")
71237+
set(GENERIC_H503RBTX_MAXSIZE 131072)
71238+
set(GENERIC_H503RBTX_MAXDATASIZE 32768)
71239+
set(GENERIC_H503RBTX_MCU cortex-m33)
71240+
set(GENERIC_H503RBTX_FPCONF "-")
71241+
add_library(GENERIC_H503RBTX INTERFACE)
71242+
target_compile_options(GENERIC_H503RBTX INTERFACE
71243+
"SHELL:-DSTM32H503xx "
71244+
"SHELL:"
71245+
"SHELL:"
71246+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
71247+
-mcpu=${GENERIC_H503RBTX_MCU}
71248+
)
71249+
target_compile_definitions(GENERIC_H503RBTX INTERFACE
71250+
"STM32H5xx"
71251+
"ARDUINO_GENERIC_H503RBTX"
71252+
"BOARD_NAME=\"GENERIC_H503RBTX\""
71253+
"BOARD_ID=GENERIC_H503RBTX"
71254+
"VARIANT_H=\"variant_generic.h\""
71255+
)
71256+
target_include_directories(GENERIC_H503RBTX INTERFACE
71257+
${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
71258+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
71259+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
71260+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
71261+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
71262+
${GENERIC_H503RBTX_VARIANT_PATH}
71263+
)
71264+
71265+
target_link_options(GENERIC_H503RBTX INTERFACE
71266+
"LINKER:--default-script=${GENERIC_H503RBTX_VARIANT_PATH}/ldscript.ld"
71267+
"LINKER:--defsym=LD_FLASH_OFFSET=0x0"
71268+
"LINKER:--defsym=LD_MAX_SIZE=131072"
71269+
"LINKER:--defsym=LD_MAX_DATA_SIZE=32768"
71270+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
71271+
-mcpu=${GENERIC_H503RBTX_MCU}
71272+
)
71273+
target_link_libraries(GENERIC_H503RBTX INTERFACE
71274+
arm_ARMv8MMLlfsp_math
71275+
)
71276+
71277+
add_library(GENERIC_H503RBTX_serial_disabled INTERFACE)
71278+
target_compile_options(GENERIC_H503RBTX_serial_disabled INTERFACE
71279+
"SHELL:"
71280+
)
71281+
add_library(GENERIC_H503RBTX_serial_generic INTERFACE)
71282+
target_compile_options(GENERIC_H503RBTX_serial_generic INTERFACE
71283+
"SHELL:-DHAL_UART_MODULE_ENABLED"
71284+
)
71285+
add_library(GENERIC_H503RBTX_serial_none INTERFACE)
71286+
target_compile_options(GENERIC_H503RBTX_serial_none INTERFACE
71287+
"SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
71288+
)
71289+
add_library(GENERIC_H503RBTX_usb_CDC INTERFACE)
71290+
target_compile_options(GENERIC_H503RBTX_usb_CDC INTERFACE
71291+
"SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
71292+
)
71293+
add_library(GENERIC_H503RBTX_usb_CDCgen INTERFACE)
71294+
target_compile_options(GENERIC_H503RBTX_usb_CDCgen INTERFACE
71295+
"SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
71296+
)
71297+
add_library(GENERIC_H503RBTX_usb_HID INTERFACE)
71298+
target_compile_options(GENERIC_H503RBTX_usb_HID INTERFACE
71299+
"SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
71300+
)
71301+
add_library(GENERIC_H503RBTX_usb_none INTERFACE)
71302+
target_compile_options(GENERIC_H503RBTX_usb_none INTERFACE
71303+
"SHELL:"
71304+
)
71305+
add_library(GENERIC_H503RBTX_xusb_FS INTERFACE)
71306+
target_compile_options(GENERIC_H503RBTX_xusb_FS INTERFACE
71307+
"SHELL:"
71308+
)
71309+
add_library(GENERIC_H503RBTX_xusb_HS INTERFACE)
71310+
target_compile_options(GENERIC_H503RBTX_xusb_HS INTERFACE
71311+
"SHELL:-DUSE_USB_HS"
71312+
)
71313+
add_library(GENERIC_H503RBTX_xusb_HSFS INTERFACE)
71314+
target_compile_options(GENERIC_H503RBTX_xusb_HSFS INTERFACE
71315+
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
71316+
)
71317+
7123371318
# GENERIC_H563IIKXQ
7123471319
# -----------------------------------------------------------------------------
7123571320

@@ -98518,6 +98603,91 @@ target_compile_options(NUCLEO_G474RE_xusb_HSFS INTERFACE
9851898603
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
9851998604
)
9852098605

98606+
# NUCLEO_H503RB
98607+
# -----------------------------------------------------------------------------
98608+
98609+
set(NUCLEO_H503RB_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503RBT")
98610+
set(NUCLEO_H503RB_MAXSIZE 131072)
98611+
set(NUCLEO_H503RB_MAXDATASIZE 32768)
98612+
set(NUCLEO_H503RB_MCU cortex-m33)
98613+
set(NUCLEO_H503RB_FPCONF "fpv4-sp-d16-hard")
98614+
add_library(NUCLEO_H503RB INTERFACE)
98615+
target_compile_options(NUCLEO_H503RB INTERFACE
98616+
"SHELL:-DSTM32H503xx "
98617+
"SHELL:"
98618+
"SHELL:"
98619+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
98620+
-mcpu=${NUCLEO_H503RB_MCU}
98621+
)
98622+
target_compile_definitions(NUCLEO_H503RB INTERFACE
98623+
"STM32H5xx"
98624+
"ARDUINO_NUCLEO_H503RB"
98625+
"BOARD_NAME=\"NUCLEO_H503RB\""
98626+
"BOARD_ID=NUCLEO_H503RB"
98627+
"VARIANT_H=\"variant_NUCLEO_H503RB.h\""
98628+
)
98629+
target_include_directories(NUCLEO_H503RB INTERFACE
98630+
${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
98631+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
98632+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
98633+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
98634+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
98635+
${NUCLEO_H503RB_VARIANT_PATH}
98636+
)
98637+
98638+
target_link_options(NUCLEO_H503RB INTERFACE
98639+
"LINKER:--default-script=${NUCLEO_H503RB_VARIANT_PATH}/ldscript.ld"
98640+
"LINKER:--defsym=LD_FLASH_OFFSET=0x0"
98641+
"LINKER:--defsym=LD_MAX_SIZE=131072"
98642+
"LINKER:--defsym=LD_MAX_DATA_SIZE=32768"
98643+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
98644+
-mcpu=${NUCLEO_H503RB_MCU}
98645+
)
98646+
target_link_libraries(NUCLEO_H503RB INTERFACE
98647+
98648+
)
98649+
98650+
add_library(NUCLEO_H503RB_serial_disabled INTERFACE)
98651+
target_compile_options(NUCLEO_H503RB_serial_disabled INTERFACE
98652+
"SHELL:"
98653+
)
98654+
add_library(NUCLEO_H503RB_serial_generic INTERFACE)
98655+
target_compile_options(NUCLEO_H503RB_serial_generic INTERFACE
98656+
"SHELL:-DHAL_UART_MODULE_ENABLED"
98657+
)
98658+
add_library(NUCLEO_H503RB_serial_none INTERFACE)
98659+
target_compile_options(NUCLEO_H503RB_serial_none INTERFACE
98660+
"SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
98661+
)
98662+
add_library(NUCLEO_H503RB_usb_CDC INTERFACE)
98663+
target_compile_options(NUCLEO_H503RB_usb_CDC INTERFACE
98664+
"SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
98665+
)
98666+
add_library(NUCLEO_H503RB_usb_CDCgen INTERFACE)
98667+
target_compile_options(NUCLEO_H503RB_usb_CDCgen INTERFACE
98668+
"SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
98669+
)
98670+
add_library(NUCLEO_H503RB_usb_HID INTERFACE)
98671+
target_compile_options(NUCLEO_H503RB_usb_HID INTERFACE
98672+
"SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
98673+
)
98674+
add_library(NUCLEO_H503RB_usb_none INTERFACE)
98675+
target_compile_options(NUCLEO_H503RB_usb_none INTERFACE
98676+
"SHELL:"
98677+
)
98678+
add_library(NUCLEO_H503RB_xusb_FS INTERFACE)
98679+
target_compile_options(NUCLEO_H503RB_xusb_FS INTERFACE
98680+
"SHELL:"
98681+
)
98682+
add_library(NUCLEO_H503RB_xusb_HS INTERFACE)
98683+
target_compile_options(NUCLEO_H503RB_xusb_HS INTERFACE
98684+
"SHELL:-DUSE_USB_HS"
98685+
)
98686+
add_library(NUCLEO_H503RB_xusb_HSFS INTERFACE)
98687+
target_compile_options(NUCLEO_H503RB_xusb_HSFS INTERFACE
98688+
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
98689+
)
98690+
9852198691
# NUCLEO_H563ZI
9852298692
# -----------------------------------------------------------------------------
9852398693

‎variants/STM32H5xx/H503RBT/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
2222
generic_clock.c
2323
PeripheralPins.c
2424
variant_generic.cpp
25+
variant_NUCLEO_H503RB.cpp
2526
)
2627
target_link_libraries(variant_bin PUBLIC variant_usage)
2728

‎variants/STM32H5xx/H503RBT/generic_clock.c‎

Lines changed: 49 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,55 @@
2020
*/
2121
WEAK void SystemClock_Config(void)
2222
{
23-
/* SystemClock_Config can be generated by STM32CubeMX */
24-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
23+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
24+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
25+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
26+
27+
/* Configure the main internal regulator output voltage */
28+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
29+
30+
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
31+
32+
/* Initializes the RCC Oscillators according to the specified parameters
33+
* in the RCC_OscInitTypeDef structure.
34+
*/
35+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_CSI;
36+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
37+
RCC_OscInitStruct.CSIState = RCC_CSI_ON;
38+
RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
39+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
40+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
41+
RCC_OscInitStruct.PLL.PLLM = 1;
42+
RCC_OscInitStruct.PLL.PLLN = 125;
43+
RCC_OscInitStruct.PLL.PLLP = 2;
44+
RCC_OscInitStruct.PLL.PLLQ = 2;
45+
RCC_OscInitStruct.PLL.PLLR = 2;
46+
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
47+
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
48+
RCC_OscInitStruct.PLL.PLLFRACN = 0;
49+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
50+
Error_Handler();
51+
}
52+
/* Initializes the CPU, AHB and APB buses clocks */
53+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
54+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
55+
| RCC_CLOCKTYPE_PCLK3;
56+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
57+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
58+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
59+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
60+
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
61+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
62+
Error_Handler();
63+
}
64+
65+
/* Initializes the peripherals clock */
66+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB;
67+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
68+
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_CSI;
69+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
70+
Error_Handler();
71+
}
2572
}
2673

2774
#endif /* ARDUINO_GENERIC_* */

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