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Merged
merged 3 commits into from
May 10, 2020
Merged

Update stm32f3 to v0.11.0 #97

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f1622db
Update stm32f3
Sh3Rm4n Apr 25, 2020
e3da244
Remove unsafe from flash wait state
Sh3Rm4n Apr 25, 2020
30d667a
Cleanup CHANGELOG.md
Sh3Rm4n Apr 26, 2020
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10 changes: 7 additions & 3 deletions CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -13,8 +13,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

### Changed

- **Breaking** The feature gate requires you to select a subvaraint if possible. ([#67](https://github.com/stm32-rs/stm32f3xx-hal/pull/67))
- **Breaking** Split up `stm32f302` into sub-targets `stm32f302xb`,`stm32f302xc`,`stm32f302xd`,`stm32f302xe`
- The system clock calculation is more fine grained now. ([#67](https://github.com/stm32-rs/stm32f3xx-hal/pull/67))
Now the system clock can be some value, like 14 MHz, which can not a
be represented as a multiple of the oscillator clock:
Expand All @@ -34,6 +32,12 @@ let clocks = rcc
external oscillator clock on most devices. Some devices have even the
possibility to divide the internal oscillator clock.

### Breaking changes

- The feature gate requires you to select a subvariant if possible. ([#75](https://github.com/stm32-rs/stm32f3xx-hal/pull/75))
- Split up `stm32f302` into sub-targets `stm32f302xb`,`stm32f302xc`,`stm32f302xd`,`stm32f302xe`
- Bump `stm32f3` dependency to `0.11.0` ([#97](https://github.com/stm32-rs/stm32f3xx-hal/pull/97))

## [v0.4.3] - 2020-04-11

### Added
Expand Down Expand Up @@ -134,7 +138,7 @@ let clocks = rcc

- Various peripheral mappings for some devices ([#12](https://github.com/stm32-rs/stm32f3xx-hal/pull/12))

### Breaking changers
### Breaking changes

- Switch to the `embedded-hal` v2 digital pin trait.

Expand Down
2 changes: 1 addition & 1 deletion Cargo.toml
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Expand Up @@ -23,7 +23,7 @@ cortex-m = "0.6"
cortex-m-rt = "0.6"
embedded-hal = "0.2"
nb = "0.1"
stm32f3 = "0.10"
stm32f3 = "0.11"

[dependencies.bare-metal]
version = "0.2"
Expand Down
23 changes: 11 additions & 12 deletions src/rcc.rs
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Expand Up @@ -524,18 +524,17 @@ impl CFGR {

assert!(pclk2 <= 72_000_000);

// adjust flash wait states
unsafe {
acr.acr().modify(|_, w| {
w.latency().bits(if sysclk <= 24_000_000 {
0b000
} else if sysclk <= 48_000_000 {
0b001
} else {
0b010
})
})
}
// Adjust flash wait states according to the
// HCLK frequency (cpu core clock)
acr.acr().modify(|_, w| {
if hclk <= 24_000_000 {
w.latency().ws0()
} else if hclk <= 48_000_000 {
w.latency().ws1()
Comment on lines +529 to +533
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@strom-und-spiele strom-und-spiele Apr 26, 2020

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All those magic numbers make me nervous.
I'm not sure if it helps that they are documented but not explained in stm32f3

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@Sh3Rm4n Sh3Rm4n Apr 27, 2020

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Yeah, the documentation of the stm32f3 is always very brief. But more detailed explanation is not the intent of the stm32f3 crate, as this is auto-generated code from svd files. A more detailed explanation is always in the reference manual. However, it does not hurt to add documentation here, to explain, why this is needed.

} else {
w.latency().ws2()
}
});

let (usbpre, usbclk_valid) = usb_clocking::is_valid(sysclk, self.hse, pclk1, &pll_config);

Expand Down