Update docs

Author: Piroro-hs

CHANGELOG.md

@@ -11,10 +11,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Make `Clocks` `ppre1()` and `ppre2()` methods public, to get the current
   Prescaler value. ([#210])
-- Implement `into_xxx` methods for partially erased pins ([#189])
 - Enable better GPIO internal resistor configuration ([#189])
 - Support for GPIO output slew rate configuration ([#189])
 - Support for GPIO interrupts ([#189])
+- Implement `into_xxx` methods for erased pins ([#213])
 
 ### Changed
 
@@ -59,6 +59,7 @@ let clocks = rcc
   in alternate function mode ([#189])
 - GPIO internal resistor configuration is no longer encoded into pin typestate
   in input mode ([#189])
+- GPIO configuration functions no longer require registers as arguments ([#213])
 
 ## [v0.6.1] - 2020-12-10
 
@@ -313,6 +314,7 @@ let clocks = rcc
 [defmt]: https://github.com/knurling-rs/defmt
 [filter]: https://defmt.ferrous-systems.com/filtering.html
 
+[#213]: https://github.com/stm32-rs/stm32f3xx-hal/pull/213
 [#211]: https://github.com/stm32-rs/stm32f3xx-hal/pull/211
 [#210]: https://github.com/stm32-rs/stm32f3xx-hal/pull/210
 [#208]: https://github.com/stm32-rs/stm32f3xx-hal/pull/208

src/gpio.rs

@@ -7,7 +7,7 @@
 //! let dp = pac::Peripherals::take().unwrap();
 //! let rcc = dp.RCC.constrain();
 //!
-//! let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);
+//! let gpioa = dp.GPIOA.split(&mut rcc.ahb);
 //! ```
 //!
 //! The resulting [Parts](gpioa::Parts) struct contains one field for each pin. Every pin type is a

src/pwm.rs

@@ -47,12 +47,12 @@
   the channels have pins connected they can be enabled.
 
   ```
-    let mut gpioa = dp.GPIOB.split(&mut rcc.ahb);
-    let pa6 = gpioa.pa6.into_af2(&mut gpioa.moder, &mut gpioa.afrl);
+    let gpioa = dp.GPIOB.split(&mut rcc.ahb);
+    let pa6 = gpioa.pa6.into_af2_push_pull();
 
-    let mut gpiob = dp.GPIOB.split(&mut rcc.ahb);
-    let pb1 = gpiob.pb1.into_af2(&mut gpiob.moder, &mut gpiob.afrl);
-    let pb4 = gpiob.pb4.into_af2(&mut gpiob.moder, &mut gpiob.afrl);
+    let gpiob = dp.GPIOB.split(&mut rcc.ahb);
+    let pb1 = gpiob.pb1.into_af2_push_pull();
+    let pb4 = gpiob.pb4.into_af2_open_drain();
 
     let mut ch1 = ch1_no_pins
         .output_to_pa6(pa6)
@@ -121,8 +121,8 @@
     // 50Hz.
     let mut (ch1_no_pins, _, _, _) = tim1(device.TIM3, 9000, 50.Hz(), clocks);
 
-    let mut gpioa = dp.GPIOB.split(&mut rcc.ahb);
-    let pa7 = gpioa.pa7.into_af6(&mut gpioa.moder, &mut gpioa.afrl);
+    let gpioa = dp.GPIOB.split(&mut rcc.ahb);
+    let pa7 = gpioa.pa7.into_af6_push_pull();
 
     let mut ch1 = ch1_no_pins.output_to(pa7);
     ch1.enable();
@@ -136,9 +136,9 @@
   ```
     ...
 
-    let mut gpioa = dp.GPIOB.split(&mut rcc.ahb);
-    let pa7 = gpioa.pa7.into_af6(&mut gpioa.moder, &mut gpioa.afrl);
-    let pa8 = gpioa.pa8.into_af6(&mut gpioa.moder, &mut gpioa.afrl);
+    let gpioa = dp.GPIOB.split(&mut rcc.ahb);
+    let pa7 = gpioa.pa7.into_af6_push_pull();
+    let pa8 = gpioa.pa8.into_af6_push_pull();
 
     let mut ch1 = ch1_no_pins
         .output_to(pa7)