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AmanieuAmanieu
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Add stricter validation of const arguments on x86 intrinsics (#1025)
1 parent 8efa2f1 commit dab4581

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4 files changed

+79
-48
lines changed

4 files changed

+79
-48
lines changed

‎crates/core_arch/src/x86/avx2.rs

+40-24
Original file line numberDiff line numberDiff line change
@@ -2929,9 +2929,11 @@ pub unsafe fn _mm256_sll_epi64(a: __m256i, count: __m128i) -> __m256i {
29292929
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_slli_epi16)
29302930
#[inline]
29312931
#[target_feature(enable = "avx2")]
2932-
#[cfg_attr(test, assert_instr(vpsllw))]
2932+
#[cfg_attr(test, assert_instr(vpsllw, imm8 = 7))]
2933+
#[rustc_legacy_const_generics(1)]
29332934
#[stable(feature = "simd_x86", since = "1.27.0")]
2934-
pub unsafe fn _mm256_slli_epi16(a: __m256i, imm8: i32) -> __m256i {
2935+
pub unsafe fn _mm256_slli_epi16<const imm8: i32>(a: __m256i) -> __m256i {
2936+
static_assert_imm8!(imm8);
29352937
transmute(pslliw(a.as_i16x16(), imm8))
29362938
}
29372939

@@ -2941,9 +2943,11 @@ pub unsafe fn _mm256_slli_epi16(a: __m256i, imm8: i32) -> __m256i {
29412943
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_slli_epi32)
29422944
#[inline]
29432945
#[target_feature(enable = "avx2")]
2944-
#[cfg_attr(test, assert_instr(vpslld))]
2946+
#[cfg_attr(test, assert_instr(vpslld, imm8 = 7))]
2947+
#[rustc_legacy_const_generics(1)]
29452948
#[stable(feature = "simd_x86", since = "1.27.0")]
2946-
pub unsafe fn _mm256_slli_epi32(a: __m256i, imm8: i32) -> __m256i {
2949+
pub unsafe fn _mm256_slli_epi32<const imm8: i32>(a: __m256i) -> __m256i {
2950+
static_assert_imm8!(imm8);
29472951
transmute(psllid(a.as_i32x8(), imm8))
29482952
}
29492953

@@ -2953,9 +2957,11 @@ pub unsafe fn _mm256_slli_epi32(a: __m256i, imm8: i32) -> __m256i {
29532957
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_slli_epi64)
29542958
#[inline]
29552959
#[target_feature(enable = "avx2")]
2956-
#[cfg_attr(test, assert_instr(vpsllq))]
2960+
#[cfg_attr(test, assert_instr(vpsllq, imm8 = 7))]
2961+
#[rustc_legacy_const_generics(1)]
29572962
#[stable(feature = "simd_x86", since = "1.27.0")]
2958-
pub unsafe fn _mm256_slli_epi64(a: __m256i, imm8: i32) -> __m256i {
2963+
pub unsafe fn _mm256_slli_epi64<const imm8: i32>(a: __m256i) -> __m256i {
2964+
static_assert_imm8!(imm8);
29592965
transmute(pslliq(a.as_i64x4(), imm8))
29602966
}
29612967

@@ -3077,9 +3083,11 @@ pub unsafe fn _mm256_sra_epi32(a: __m256i, count: __m128i) -> __m256i {
30773083
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srai_epi16)
30783084
#[inline]
30793085
#[target_feature(enable = "avx2")]
3080-
#[cfg_attr(test, assert_instr(vpsraw))]
3086+
#[cfg_attr(test, assert_instr(vpsraw, imm8 = 7))]
3087+
#[rustc_legacy_const_generics(1)]
30813088
#[stable(feature = "simd_x86", since = "1.27.0")]
3082-
pub unsafe fn _mm256_srai_epi16(a: __m256i, imm8: i32) -> __m256i {
3089+
pub unsafe fn _mm256_srai_epi16<const imm8: i32>(a: __m256i) -> __m256i {
3090+
static_assert_imm8!(imm8);
30833091
transmute(psraiw(a.as_i16x16(), imm8))
30843092
}
30853093

@@ -3089,9 +3097,11 @@ pub unsafe fn _mm256_srai_epi16(a: __m256i, imm8: i32) -> __m256i {
30893097
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srai_epi32)
30903098
#[inline]
30913099
#[target_feature(enable = "avx2")]
3092-
#[cfg_attr(test, assert_instr(vpsrad))]
3100+
#[cfg_attr(test, assert_instr(vpsrad, imm8 = 7))]
3101+
#[rustc_legacy_const_generics(1)]
30933102
#[stable(feature = "simd_x86", since = "1.27.0")]
3094-
pub unsafe fn _mm256_srai_epi32(a: __m256i, imm8: i32) -> __m256i {
3103+
pub unsafe fn _mm256_srai_epi32<const imm8: i32>(a: __m256i) -> __m256i {
3104+
static_assert_imm8!(imm8);
30953105
transmute(psraid(a.as_i32x8(), imm8))
30963106
}
30973107

@@ -3197,9 +3207,11 @@ pub unsafe fn _mm256_srl_epi64(a: __m256i, count: __m128i) -> __m256i {
31973207
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srli_epi16)
31983208
#[inline]
31993209
#[target_feature(enable = "avx2")]
3200-
#[cfg_attr(test, assert_instr(vpsrlw))]
3210+
#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 7))]
3211+
#[rustc_legacy_const_generics(1)]
32013212
#[stable(feature = "simd_x86", since = "1.27.0")]
3202-
pub unsafe fn _mm256_srli_epi16(a: __m256i, imm8: i32) -> __m256i {
3213+
pub unsafe fn _mm256_srli_epi16<const imm8: i32>(a: __m256i) -> __m256i {
3214+
static_assert_imm8!(imm8);
32033215
transmute(psrliw(a.as_i16x16(), imm8))
32043216
}
32053217

@@ -3209,9 +3221,11 @@ pub unsafe fn _mm256_srli_epi16(a: __m256i, imm8: i32) -> __m256i {
32093221
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srli_epi32)
32103222
#[inline]
32113223
#[target_feature(enable = "avx2")]
3212-
#[cfg_attr(test, assert_instr(vpsrld))]
3224+
#[cfg_attr(test, assert_instr(vpsrld, imm8 = 7))]
3225+
#[rustc_legacy_const_generics(1)]
32133226
#[stable(feature = "simd_x86", since = "1.27.0")]
3214-
pub unsafe fn _mm256_srli_epi32(a: __m256i, imm8: i32) -> __m256i {
3227+
pub unsafe fn _mm256_srli_epi32<const imm8: i32>(a: __m256i) -> __m256i {
3228+
static_assert_imm8!(imm8);
32153229
transmute(psrlid(a.as_i32x8(), imm8))
32163230
}
32173231

@@ -3221,9 +3235,11 @@ pub unsafe fn _mm256_srli_epi32(a: __m256i, imm8: i32) -> __m256i {
32213235
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srli_epi64)
32223236
#[inline]
32233237
#[target_feature(enable = "avx2")]
3224-
#[cfg_attr(test, assert_instr(vpsrlq))]
3238+
#[cfg_attr(test, assert_instr(vpsrlq, imm8 = 7))]
3239+
#[rustc_legacy_const_generics(1)]
32253240
#[stable(feature = "simd_x86", since = "1.27.0")]
3226-
pub unsafe fn _mm256_srli_epi64(a: __m256i, imm8: i32) -> __m256i {
3241+
pub unsafe fn _mm256_srli_epi64<const imm8: i32>(a: __m256i) -> __m256i {
3242+
static_assert_imm8!(imm8);
32273243
transmute(psrliq(a.as_i64x4(), imm8))
32283244
}
32293245

@@ -5204,23 +5220,23 @@ mod tests {
52045220
#[simd_test(enable = "avx2")]
52055221
unsafe fn test_mm256_slli_epi16() {
52065222
assert_eq_m256i(
5207-
_mm256_slli_epi16(_mm256_set1_epi16(0xFF), 4),
5223+
_mm256_slli_epi16::<4>(_mm256_set1_epi16(0xFF)),
52085224
_mm256_set1_epi16(0xFF0),
52095225
);
52105226
}
52115227

52125228
#[simd_test(enable = "avx2")]
52135229
unsafe fn test_mm256_slli_epi32() {
52145230
assert_eq_m256i(
5215-
_mm256_slli_epi32(_mm256_set1_epi32(0xFFFF), 4),
5231+
_mm256_slli_epi32::<4>(_mm256_set1_epi32(0xFFFF)),
52165232
_mm256_set1_epi32(0xFFFF0),
52175233
);
52185234
}
52195235

52205236
#[simd_test(enable = "avx2")]
52215237
unsafe fn test_mm256_slli_epi64() {
52225238
assert_eq_m256i(
5223-
_mm256_slli_epi64(_mm256_set1_epi64x(0xFFFFFFFF), 4),
5239+
_mm256_slli_epi64::<4>(_mm256_set1_epi64x(0xFFFFFFFF)),
52245240
_mm256_set1_epi64x(0xFFFFFFFF0),
52255241
);
52265242
}
@@ -5287,15 +5303,15 @@ mod tests {
52875303
#[simd_test(enable = "avx2")]
52885304
unsafe fn test_mm256_srai_epi16() {
52895305
assert_eq_m256i(
5290-
_mm256_srai_epi16(_mm256_set1_epi16(-1), 1),
5306+
_mm256_srai_epi16::<1>(_mm256_set1_epi16(-1)),
52915307
_mm256_set1_epi16(-1),
52925308
);
52935309
}
52945310

52955311
#[simd_test(enable = "avx2")]
52965312
unsafe fn test_mm256_srai_epi32() {
52975313
assert_eq_m256i(
5298-
_mm256_srai_epi32(_mm256_set1_epi32(-1), 1),
5314+
_mm256_srai_epi32::<1>(_mm256_set1_epi32(-1)),
52995315
_mm256_set1_epi32(-1),
53005316
);
53015317
}
@@ -5365,23 +5381,23 @@ mod tests {
53655381
#[simd_test(enable = "avx2")]
53665382
unsafe fn test_mm256_srli_epi16() {
53675383
assert_eq_m256i(
5368-
_mm256_srli_epi16(_mm256_set1_epi16(0xFF), 4),
5384+
_mm256_srli_epi16::<4>(_mm256_set1_epi16(0xFF)),
53695385
_mm256_set1_epi16(0xF),
53705386
);
53715387
}
53725388

53735389
#[simd_test(enable = "avx2")]
53745390
unsafe fn test_mm256_srli_epi32() {
53755391
assert_eq_m256i(
5376-
_mm256_srli_epi32(_mm256_set1_epi32(0xFFFF), 4),
5392+
_mm256_srli_epi32::<4>(_mm256_set1_epi32(0xFFFF)),
53775393
_mm256_set1_epi32(0xFFF),
53785394
);
53795395
}
53805396

53815397
#[simd_test(enable = "avx2")]
53825398
unsafe fn test_mm256_srli_epi64() {
53835399
assert_eq_m256i(
5384-
_mm256_srli_epi64(_mm256_set1_epi64x(0xFFFFFFFF), 4),
5400+
_mm256_srli_epi64::<4>(_mm256_set1_epi64x(0xFFFFFFFF)),
53855401
_mm256_set1_epi64x(0xFFFFFFF),
53865402
);
53875403
}

‎crates/core_arch/src/x86/avx512bw.rs

+6-6
Original file line numberDiff line numberDiff line change
@@ -5166,7 +5166,7 @@ pub unsafe fn _mm512_maskz_slli_epi16(k: __mmask32, a: __m512i, imm8: u32) -> __
51665166
pub unsafe fn _mm256_mask_slli_epi16(src: __m256i, k: __mmask16, a: __m256i, imm8: u32) -> __m256i {
51675167
macro_rules! call {
51685168
($imm8:expr) => {
5169-
_mm256_slli_epi16(a, $imm8)
5169+
_mm256_slli_epi16::<$imm8>(a)
51705170
};
51715171
}
51725172
let shf = constify_imm8_sae!(imm8, call);
@@ -5183,7 +5183,7 @@ pub unsafe fn _mm256_mask_slli_epi16(src: __m256i, k: __mmask16, a: __m256i, imm
51835183
pub unsafe fn _mm256_maskz_slli_epi16(k: __mmask16, a: __m256i, imm8: u32) -> __m256i {
51845184
macro_rules! call {
51855185
($imm8:expr) => {
5186-
_mm256_slli_epi16(a, $imm8)
5186+
_mm256_slli_epi16::<$imm8>(a)
51875187
};
51885188
}
51895189
let shf = constify_imm8_sae!(imm8, call);
@@ -5495,7 +5495,7 @@ pub unsafe fn _mm512_maskz_srli_epi16(k: __mmask32, a: __m512i, imm8: i32) -> __
54955495
pub unsafe fn _mm256_mask_srli_epi16(src: __m256i, k: __mmask16, a: __m256i, imm8: i32) -> __m256i {
54965496
macro_rules! call {
54975497
($imm8:expr) => {
5498-
_mm256_srli_epi16(a, $imm8)
5498+
_mm256_srli_epi16::<$imm8>(a)
54995499
};
55005500
}
55015501
let shf = constify_imm8_sae!(imm8, call);
@@ -5512,7 +5512,7 @@ pub unsafe fn _mm256_mask_srli_epi16(src: __m256i, k: __mmask16, a: __m256i, imm
55125512
pub unsafe fn _mm256_maskz_srli_epi16(k: __mmask16, a: __m256i, imm8: i32) -> __m256i {
55135513
macro_rules! call {
55145514
($imm8:expr) => {
5515-
_mm256_srli_epi16(a, $imm8)
5515+
_mm256_srli_epi16::<$imm8>(a)
55165516
};
55175517
}
55185518
let shf = constify_imm8_sae!(imm8, call);
@@ -5823,7 +5823,7 @@ pub unsafe fn _mm512_maskz_srai_epi16(k: __mmask32, a: __m512i, imm8: u32) -> __
58235823
pub unsafe fn _mm256_mask_srai_epi16(src: __m256i, k: __mmask16, a: __m256i, imm8: u32) -> __m256i {
58245824
macro_rules! call {
58255825
($imm8:expr) => {
5826-
_mm256_srai_epi16(a, $imm8)
5826+
_mm256_srai_epi16::<$imm8>(a)
58275827
};
58285828
}
58295829
let shf = constify_imm8_sae!(imm8, call);
@@ -5840,7 +5840,7 @@ pub unsafe fn _mm256_mask_srai_epi16(src: __m256i, k: __mmask16, a: __m256i, imm
58405840
pub unsafe fn _mm256_maskz_srai_epi16(k: __mmask16, a: __m256i, imm8: u32) -> __m256i {
58415841
macro_rules! call {
58425842
($imm8:expr) => {
5843-
_mm256_srai_epi16(a, $imm8)
5843+
_mm256_srai_epi16::<$imm8>(a)
58445844
};
58455845
}
58465846
let shf = constify_imm8_sae!(imm8, call);

‎crates/core_arch/src/x86/avx512f.rs

+10-10
Original file line numberDiff line numberDiff line change
@@ -18149,7 +18149,7 @@ pub unsafe fn _mm512_maskz_slli_epi32(k: __mmask16, a: __m512i, imm8: u32) -> __
1814918149
pub unsafe fn _mm256_mask_slli_epi32(src: __m256i, k: __mmask8, a: __m256i, imm8: u32) -> __m256i {
1815018150
macro_rules! call {
1815118151
($imm8:expr) => {
18152-
_mm256_slli_epi32(a, $imm8)
18152+
_mm256_slli_epi32::<$imm8>(a)
1815318153
};
1815418154
}
1815518155
let shf = constify_imm8_sae!(imm8, call);
@@ -18166,7 +18166,7 @@ pub unsafe fn _mm256_mask_slli_epi32(src: __m256i, k: __mmask8, a: __m256i, imm8
1816618166
pub unsafe fn _mm256_maskz_slli_epi32(k: __mmask8, a: __m256i, imm8: u32) -> __m256i {
1816718167
macro_rules! call {
1816818168
($imm8:expr) => {
18169-
_mm256_slli_epi32(a, $imm8)
18169+
_mm256_slli_epi32::<$imm8>(a)
1817018170
};
1817118171
}
1817218172
let shf = constify_imm8_sae!(imm8, call);
@@ -18274,7 +18274,7 @@ pub unsafe fn _mm512_maskz_srli_epi32(k: __mmask16, a: __m512i, imm8: u32) -> __
1827418274
pub unsafe fn _mm256_mask_srli_epi32(src: __m256i, k: __mmask8, a: __m256i, imm8: u32) -> __m256i {
1827518275
macro_rules! call {
1827618276
($imm8:expr) => {
18277-
_mm256_srli_epi32(a, $imm8)
18277+
_mm256_srli_epi32::<$imm8>(a)
1827818278
};
1827918279
}
1828018280
let shf = constify_imm8_sae!(imm8, call);
@@ -18291,7 +18291,7 @@ pub unsafe fn _mm256_mask_srli_epi32(src: __m256i, k: __mmask8, a: __m256i, imm8
1829118291
pub unsafe fn _mm256_maskz_srli_epi32(k: __mmask8, a: __m256i, imm8: u32) -> __m256i {
1829218292
macro_rules! call {
1829318293
($imm8:expr) => {
18294-
_mm256_srli_epi32(a, $imm8)
18294+
_mm256_srli_epi32::<$imm8>(a)
1829518295
};
1829618296
}
1829718297
let shf = constify_imm8_sae!(imm8, call);
@@ -18399,7 +18399,7 @@ pub unsafe fn _mm512_maskz_slli_epi64(k: __mmask8, a: __m512i, imm8: u32) -> __m
1839918399
pub unsafe fn _mm256_mask_slli_epi64(src: __m256i, k: __mmask8, a: __m256i, imm8: u32) -> __m256i {
1840018400
macro_rules! call {
1840118401
($imm8:expr) => {
18402-
_mm256_slli_epi64(a, $imm8)
18402+
_mm256_slli_epi64::<$imm8>(a)
1840318403
};
1840418404
}
1840518405
let shf = constify_imm8_sae!(imm8, call);
@@ -18416,7 +18416,7 @@ pub unsafe fn _mm256_mask_slli_epi64(src: __m256i, k: __mmask8, a: __m256i, imm8
1841618416
pub unsafe fn _mm256_maskz_slli_epi64(k: __mmask8, a: __m256i, imm8: u32) -> __m256i {
1841718417
macro_rules! call {
1841818418
($imm8:expr) => {
18419-
_mm256_slli_epi64(a, $imm8)
18419+
_mm256_slli_epi64::<$imm8>(a)
1842018420
};
1842118421
}
1842218422
let shf = constify_imm8_sae!(imm8, call);
@@ -18524,7 +18524,7 @@ pub unsafe fn _mm512_maskz_srli_epi64(k: __mmask8, a: __m512i, imm8: u32) -> __m
1852418524
pub unsafe fn _mm256_mask_srli_epi64(src: __m256i, k: __mmask8, a: __m256i, imm8: u32) -> __m256i {
1852518525
macro_rules! call {
1852618526
($imm8:expr) => {
18527-
_mm256_srli_epi64(a, $imm8)
18527+
_mm256_srli_epi64::<$imm8>(a)
1852818528
};
1852918529
}
1853018530
let shf = constify_imm8_sae!(imm8, call);
@@ -18541,7 +18541,7 @@ pub unsafe fn _mm256_mask_srli_epi64(src: __m256i, k: __mmask8, a: __m256i, imm8
1854118541
pub unsafe fn _mm256_maskz_srli_epi64(k: __mmask8, a: __m256i, imm8: u32) -> __m256i {
1854218542
macro_rules! call {
1854318543
($imm8:expr) => {
18544-
_mm256_srli_epi64(a, $imm8)
18544+
_mm256_srli_epi64::<$imm8>(a)
1854518545
};
1854618546
}
1854718547
let shf = constify_imm8_sae!(imm8, call);
@@ -19203,7 +19203,7 @@ pub unsafe fn _mm512_maskz_srai_epi32(k: __mmask16, a: __m512i, imm8: u32) -> __
1920319203
pub unsafe fn _mm256_mask_srai_epi32(src: __m256i, k: __mmask8, a: __m256i, imm8: u32) -> __m256i {
1920419204
macro_rules! call {
1920519205
($imm8:expr) => {
19206-
_mm256_srai_epi32(a, $imm8)
19206+
_mm256_srai_epi32::<$imm8>(a)
1920719207
};
1920819208
}
1920919209
let shf = constify_imm8_sae!(imm8, call);
@@ -19220,7 +19220,7 @@ pub unsafe fn _mm256_mask_srai_epi32(src: __m256i, k: __mmask8, a: __m256i, imm8
1922019220
pub unsafe fn _mm256_maskz_srai_epi32(k: __mmask8, a: __m256i, imm8: u32) -> __m256i {
1922119221
macro_rules! call {
1922219222
($imm8:expr) => {
19223-
_mm256_srai_epi32(a, $imm8)
19223+
_mm256_srai_epi32::<$imm8>(a)
1922419224
};
1922519225
}
1922619226
let shf = constify_imm8_sae!(imm8, call);

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