Revert "Use traversal::{preorder, reachable_as_bitset} from basic block cache"

This reverts commit de9e08a.

Author: Noratrieb

compiler/rustc_const_eval/src/transform/validate.rs

@@ -93,7 +93,7 @@ struct TypeChecker<'a, 'tcx> {
     param_env: ParamEnv<'tcx>,
     mir_phase: MirPhase,
     unwind_edge_count: usize,
-    reachable_blocks: &'a BitSet<BasicBlock>,
+    reachable_blocks: BitSet<BasicBlock>,
     storage_liveness: ResultsCursor<'a, 'tcx, MaybeStorageLive<'static>>,
     place_cache: Vec<PlaceRef<'tcx>>,
     value_cache: Vec<u128>,

compiler/rustc_middle/src/mir/basic_blocks.rs

@@ -6,13 +6,10 @@ use rustc_data_structures::graph;
 use rustc_data_structures::graph::dominators::{dominators, Dominators};
 use rustc_data_structures::stable_hasher::{HashStable, StableHasher};
 use rustc_data_structures::sync::OnceCell;
-use rustc_index::bit_set::BitSet;
 use rustc_index::{IndexSlice, IndexVec};
 use rustc_serialize::{Decodable, Decoder, Encodable, Encoder};
 use smallvec::SmallVec;
 
-use super::traversal::Preorder;
-
 #[derive(Clone, TyEncodable, TyDecodable, Debug, HashStable, TypeFoldable, TypeVisitable)]
 pub struct BasicBlocks<'tcx> {
     basic_blocks: IndexVec<BasicBlock, BasicBlockData<'tcx>>,
@@ -29,7 +26,6 @@ struct Cache {
     predecessors: OnceCell<Predecessors>,
     switch_sources: OnceCell<SwitchSources>,
     is_cyclic: OnceCell<bool>,
-    preorder: OnceCell<(Vec<BasicBlock>, BitSet<BasicBlock>)>,
     postorder: OnceCell<Vec<BasicBlock>>,
     dominators: OnceCell<Dominators<BasicBlock>>,
 }
@@ -74,18 +70,6 @@ impl<'tcx> BasicBlocks<'tcx> {
         })
     }
 
-    /// Returns basic blocks in a preorder.
-    #[inline]
-    pub fn preorder_and_reachable_bitset(&self) -> (&[BasicBlock], &BitSet<BasicBlock>) {
-        let (preorder, reachable) = self.cache.preorder.get_or_init(|| {
-            let mut result = Vec::new();
-            let mut preorder = Preorder::new(&self.basic_blocks, START_BLOCK);
-            result.extend(preorder.by_ref().map(|(bb, _)| bb));
-            (result, preorder.into_visited())
-        });
-        (preorder, reachable)
-    }
-
     /// `switch_sources()[&(target, switch)]` returns a list of switch
     /// values that lead to a `target` block from a `switch` block.
     #[inline]

compiler/rustc_middle/src/mir/traversal.rs

@@ -22,41 +22,27 @@ use super::*;
 /// A preorder traversal of this graph is either `A B D C` or `A C D B`
 #[derive(Clone)]
 pub struct Preorder<'a, 'tcx> {
-    basic_blocks: &'a IndexSlice<BasicBlock, BasicBlockData<'tcx>>,
+    body: &'a Body<'tcx>,
     visited: BitSet<BasicBlock>,
     worklist: Vec<BasicBlock>,
     root_is_start_block: bool,
 }
 
 impl<'a, 'tcx> Preorder<'a, 'tcx> {
-    pub fn new(
-        basic_blocks: &'a IndexSlice<BasicBlock, BasicBlockData<'tcx>>,
-        root: BasicBlock,
-    ) -> Preorder<'a, 'tcx> {
+    pub fn new(body: &'a Body<'tcx>, root: BasicBlock) -> Preorder<'a, 'tcx> {
         let worklist = vec![root];
 
         Preorder {
-            basic_blocks,
-            visited: BitSet::new_empty(basic_blocks.len()),
+            body,
+            visited: BitSet::new_empty(body.basic_blocks.len()),
             worklist,
             root_is_start_block: root == START_BLOCK,
         }
     }
-
-    pub(super) fn into_visited(self) -> BitSet<BasicBlock> {
-        self.visited
-    }
 }
 
-pub type PreorderIter<'a, 'tcx: 'a> =
-    impl Iterator<Item = (BasicBlock, &'a BasicBlockData<'tcx>)> + ExactSizeIterator;
-
-pub fn preorder<'a, 'tcx>(body: &'a Body<'tcx>) -> PreorderIter<'a, 'tcx> {
-    body.basic_blocks
-        .preorder_and_reachable_bitset()
-        .0
-        .iter()
-        .map(|&bb| (bb, &body.basic_blocks[bb]))
+pub fn preorder<'a, 'tcx>(body: &'a Body<'tcx>) -> Preorder<'a, 'tcx> {
+    Preorder::new(body, START_BLOCK)
 }
 
 impl<'a, 'tcx> Iterator for Preorder<'a, 'tcx> {
@@ -68,7 +54,7 @@ impl<'a, 'tcx> Iterator for Preorder<'a, 'tcx> {
                 continue;
             }
 
-            let data = &self.basic_blocks[idx];
+            let data = &self.body[idx];
 
             if let Some(ref term) = data.terminator {
                 self.worklist.extend(term.successors());
@@ -82,7 +68,7 @@ impl<'a, 'tcx> Iterator for Preorder<'a, 'tcx> {
 
     fn size_hint(&self) -> (usize, Option<usize>) {
         // All the blocks, minus the number of blocks we've visited.
-        let upper = self.basic_blocks.len() - self.visited.count();
+        let upper = self.body.basic_blocks.len() - self.visited.count();
 
         let lower = if self.root_is_start_block {
             // We will visit all remaining blocks exactly once.
@@ -299,13 +285,17 @@ impl<'a, 'tcx> ExactSizeIterator for ReversePostorder<'a, 'tcx> {}
 /// order.
 ///
 /// This is clearer than writing `preorder` in cases where the order doesn't matter.
-pub fn reachable<'a, 'tcx>(body: &'a Body<'tcx>) -> PreorderIter<'a, 'tcx> {
+pub fn reachable<'a, 'tcx>(
+    body: &'a Body<'tcx>,
+) -> impl 'a + Iterator<Item = (BasicBlock, &'a BasicBlockData<'tcx>)> {
     preorder(body)
 }
 
 /// Returns a `BitSet` containing all basic blocks reachable from the `START_BLOCK`.
-pub fn reachable_as_bitset<'a>(body: &'a Body<'_>) -> &'a BitSet<BasicBlock> {
-    body.basic_blocks.preorder_and_reachable_bitset().1
+pub fn reachable_as_bitset(body: &Body<'_>) -> BitSet<BasicBlock> {
+    let mut iter = preorder(body);
+    (&mut iter).for_each(drop);
+    iter.visited
 }
 
 #[derive(Clone)]

compiler/rustc_mir_dataflow/src/framework/cursor.rs

@@ -62,7 +62,7 @@ where
             pos: CursorPosition::block_entry(mir::START_BLOCK),
 
             #[cfg(debug_assertions)]
-            reachable_blocks: mir::traversal::reachable_as_bitset(body).clone(),
+            reachable_blocks: mir::traversal::reachable_as_bitset(body),
         }
     }
 

compiler/rustc_mir_dataflow/src/framework/graphviz.rs

@@ -43,7 +43,7 @@ where
     A: Analysis<'tcx>,
 {
     pub fn new(body: &'a Body<'tcx>, results: &'a Results<'tcx, A>, style: OutputStyle) -> Self {
-        let reachable = mir::traversal::reachable_as_bitset(body).clone();
+        let reachable = mir::traversal::reachable_as_bitset(body);
         Formatter { body, results, style, reachable }
     }
 }

compiler/rustc_mir_transform/src/elaborate_drops.rs

@@ -297,7 +297,7 @@ struct ElaborateDropsCtxt<'a, 'tcx> {
     drop_flags: IndexVec<MovePathIndex, Option<Local>>,
     patch: MirPatch<'tcx>,
     un_derefer: UnDerefer<'tcx>,
-    reachable: &'a BitSet<BasicBlock>,
+    reachable: BitSet<BasicBlock>,
 }
 
 impl<'b, 'tcx> ElaborateDropsCtxt<'b, 'tcx> {

compiler/rustc_mir_transform/src/simplify.rs

@@ -336,7 +336,7 @@ pub fn remove_duplicate_unreachable_blocks<'tcx>(tcx: TyCtxt<'tcx>, body: &mut B
 }
 
 pub fn remove_dead_blocks<'tcx>(tcx: TyCtxt<'tcx>, body: &mut Body<'tcx>) {
-    let reachable = traversal::reachable_as_bitset(body).clone();
+    let reachable = traversal::reachable_as_bitset(body);
     let num_blocks = body.basic_blocks.len();
     if num_blocks == reachable.count() {
         return;