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Commit 0b57b47

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tstellartstellar
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Merging r322373:
------------------------------------------------------------------------ r322373 | d0k | 2018-01-12 07:03:24 -0800 (Fri, 12 Jan 2018) | 4 lines [PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate the immediate I'm not even sure if this transform is ever worth it, but this at least stops the bleeding. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@330082 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/PowerPC/PPCInstrInfo.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2445,6 +2445,8 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
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Is64BitLI = Opc != PPC::RLDICL_32;
24462446
NewImm = InVal.getSExtValue();
24472447
SetCR = Opc == PPC::RLDICLo;
2448+
if (SetCR && (SExtImm & NewImm) != NewImm)
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return false;
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break;
24492451
}
24502452
return false;
@@ -2472,6 +2474,8 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
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Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
24732475
NewImm = InVal.getSExtValue();
24742476
SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2477+
if (SetCR && (SExtImm & NewImm) != NewImm)
2478+
return false;
24752479
break;
24762480
}
24772481
return false;

‎test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir

Lines changed: 134 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -561,6 +561,15 @@
561561
}
562562

563563
; Function Attrs: norecurse nounwind readnone
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define i64 @testRLDICLo2(i64 %a, i64 %b) local_unnamed_addr #0 {
565+
entry:
566+
%shr = lshr i64 %a, 11
567+
%and = and i64 %shr, 16777215
568+
%tobool = icmp eq i64 %and, 0
569+
%cond = select i1 %tobool, i64 %b, i64 %and
570+
ret i64 %cond
571+
}
572+
564573
define i64 @testRLDICLo3(i64 %a, i64 %b) local_unnamed_addr #0 {
565574
entry:
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%shr = lshr i64 %a, 11
@@ -611,6 +620,15 @@
611620
ret i32 %cond
612621
}
613622

623+
; Function Attrs: norecurse nounwind readnone
624+
define zeroext i32 @testRLWINMo2(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
625+
entry:
626+
%and = and i32 %a, 255
627+
%tobool = icmp eq i32 %and, 0
628+
%cond = select i1 %tobool, i32 %b, i32 %a
629+
ret i32 %cond
630+
}
631+
614632
; Function Attrs: norecurse nounwind readnone
615633
define i64 @testRLWINM8o(i64 %a, i64 %b) local_unnamed_addr #0 {
616634
entry:
@@ -3912,6 +3930,59 @@ body: |
39123930
%x3 = COPY %4
39133931
BLR8 implicit %lr8, implicit %rm, implicit %x3
39143932
3933+
...
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---
3935+
name: testRLDICLo2
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# CHECK-ALL: name: testRLDICLo2
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
3942+
tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
3947+
- { id: 3, class: crrc, preferred-register: '' }
3948+
- { id: 4, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '%x3', virtual-reg: '%0' }
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- { reg: '%x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
3956+
hasPatchPoint: false
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stackSize: 0
3958+
offsetAdjustment: 0
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maxAlignment: 0
3960+
adjustsStack: false
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hasCalls: false
3962+
stackProtector: ''
3963+
maxCallFrameSize: 4294967295
3964+
hasOpaqueSPAdjustment: false
3965+
hasVAStart: false
3966+
hasMustTailInVarArgFunc: false
3967+
savePoint: ''
3968+
restorePoint: ''
3969+
fixedStack:
3970+
stack:
3971+
constants:
3972+
body: |
3973+
bb.0.entry:
3974+
liveins: %x3, %x4
3975+
3976+
%1 = COPY %x4
3977+
%0 = LI8 200
3978+
%2 = RLDICLo %0, 61, 3, implicit-def %cr0
3979+
; CHECK-NOT: ANDI
3980+
; CHECK-LATE-NOT: andi.
3981+
%3 = COPY killed %cr0
3982+
%4 = ISEL8 %1, %2, %3.sub_eq
3983+
%x3 = COPY %4
3984+
BLR8 implicit %lr8, implicit %rm, implicit %x3
3985+
39153986
...
39163987
---
39173988
name: testRLDICLo3
@@ -4232,6 +4303,69 @@ body: |
42324303
%x3 = COPY %9
42334304
BLR8 implicit %lr8, implicit %rm, implicit %x3
42344305
4306+
...
4307+
---
4308+
name: testRLWINMo2
4309+
# CHECK-ALL: name: testRLWINMo2
4310+
alignment: 4
4311+
exposesReturnsTwice: false
4312+
legalized: false
4313+
regBankSelected: false
4314+
selected: false
4315+
tracksRegLiveness: true
4316+
registers:
4317+
- { id: 0, class: g8rc, preferred-register: '' }
4318+
- { id: 1, class: g8rc, preferred-register: '' }
4319+
- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
4320+
- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
4321+
- { id: 4, class: gprc, preferred-register: '' }
4322+
- { id: 5, class: crrc, preferred-register: '' }
4323+
- { id: 6, class: gprc, preferred-register: '' }
4324+
- { id: 7, class: g8rc, preferred-register: '' }
4325+
- { id: 8, class: g8rc, preferred-register: '' }
4326+
- { id: 9, class: g8rc, preferred-register: '' }
4327+
liveins:
4328+
- { reg: '%x3', virtual-reg: '%0' }
4329+
- { reg: '%x4', virtual-reg: '%1' }
4330+
frameInfo:
4331+
isFrameAddressTaken: false
4332+
isReturnAddressTaken: false
4333+
hasStackMap: false
4334+
hasPatchPoint: false
4335+
stackSize: 0
4336+
offsetAdjustment: 0
4337+
maxAlignment: 0
4338+
adjustsStack: false
4339+
hasCalls: false
4340+
stackProtector: ''
4341+
maxCallFrameSize: 4294967295
4342+
hasOpaqueSPAdjustment: false
4343+
hasVAStart: false
4344+
hasMustTailInVarArgFunc: false
4345+
savePoint: ''
4346+
restorePoint: ''
4347+
fixedStack:
4348+
stack:
4349+
constants:
4350+
body: |
4351+
bb.0.entry:
4352+
liveins: %x3, %x4
4353+
4354+
%1 = COPY %x4
4355+
%0 = COPY %x3
4356+
%2 = COPY %1.sub_32
4357+
%3 = LI -22
4358+
%4 = RLWINMo %3, 5, 24, 31, implicit-def %cr0
4359+
; CHECK-NOT: ANDI
4360+
; CHECK-LATE-NOT: andi.
4361+
%5 = COPY killed %cr0
4362+
%6 = ISEL %2, %3, %5.sub_eq
4363+
%8 = IMPLICIT_DEF
4364+
%7 = INSERT_SUBREG %8, killed %6, 1
4365+
%9 = RLDICL killed %7, 0, 32
4366+
%x3 = COPY %9
4367+
BLR8 implicit %lr8, implicit %rm, implicit %x3
4368+
42354369
...
42364370
---
42374371
name: testRLWINM8o

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