From a2d8f6de9f74592a3fc59793bc845b0426e0aa4b Mon Sep 17 00:00:00 2001 From: Tyler Holmes Date: Thu, 16 Dec 2021 22:16:33 -0800 Subject: [PATCH 1/3] `SCB.ICSR.VECTACTIVE` is 9 bits, not 8 Closes #332 --- src/peripheral/scb.rs | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index eeea0c5b..0e82b731 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -170,9 +170,10 @@ impl SCB { /// Returns the active exception number #[inline] pub fn vect_active() -> VectActive { - let icsr = unsafe { ptr::read(&(*SCB::ptr()).icsr as *const _ as *const u32) }; + let icsr = + unsafe { ptr::read_volatile(&(*SCB::ptr()).icsr as *const _ as *const u32) } & 0x1FF; - match icsr as u8 { + match icsr as u16 { 0 => VectActive::ThreadMode, 2 => VectActive::Exception(Exception::NonMaskableInt), 3 => VectActive::Exception(Exception::HardFault), @@ -274,15 +275,15 @@ pub enum VectActive { /// Device specific exception (external interrupts) Interrupt { - /// Interrupt number. This number is always within half open range `[0, 240)` - irqn: u8, + /// Interrupt number. This number is always within half open range `[0, 512)` (9 bit) + irqn: u16, }, } impl VectActive { - /// Converts a `byte` into `VectActive` + /// Converts a vector number into `VectActive` #[inline] - pub fn from(vect_active: u8) -> Option { + pub fn from(vect_active: u16) -> Option { Some(match vect_active { 0 => VectActive::ThreadMode, 2 => VectActive::Exception(Exception::NonMaskableInt), @@ -300,7 +301,7 @@ impl VectActive { 12 => VectActive::Exception(Exception::DebugMonitor), 14 => VectActive::Exception(Exception::PendSV), 15 => VectActive::Exception(Exception::SysTick), - irqn if irqn >= 16 => VectActive::Interrupt { irqn }, + irqn if irqn >= 16 && irqn < 512 => VectActive::Interrupt { irqn: irqn - 16 }, _ => return None, }) } From 8ef3eb9ea314a4edd9971541aa42696e868f8c7d Mon Sep 17 00:00:00 2001 From: Tyler Holmes Date: Fri, 31 Dec 2021 10:30:19 -0800 Subject: [PATCH 2/3] changelog entry --- CHANGELOG.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index fdb8be9c..7da0459c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,6 +18,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). There is a feature `cm7` to enable access to these. - Added `delay::Delay::with_source`, a constructor that lets you specify the SysTick clock source (#374). +- Added the capability for `DWT` to do cycle count comparison (#367). +- Updated `SCB.ICSR.VECTACTIVE`/`SCB::vect_active()` to be 9 bits instead of 8. + Also fixes `VectActive::from` to take a `u16` and subtract `16` for + `VectActive::Interrupt`s to match `SBC::vect_active()` (#373). ### Deprecated From ccdc7ccf906fd5a2c32ed947c404e41069662d20 Mon Sep 17 00:00:00 2001 From: Tyler Holmes Date: Fri, 31 Dec 2021 10:30:28 -0800 Subject: [PATCH 3/3] clippy cleanup --- src/peripheral/scb.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 0e82b731..650aede3 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -301,7 +301,7 @@ impl VectActive { 12 => VectActive::Exception(Exception::DebugMonitor), 14 => VectActive::Exception(Exception::PendSV), 15 => VectActive::Exception(Exception::SysTick), - irqn if irqn >= 16 && irqn < 512 => VectActive::Interrupt { irqn: irqn - 16 }, + irqn if (16..512).contains(&irqn) => VectActive::Interrupt { irqn: irqn - 16 }, _ => return None, }) }