diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs index d9dc0272..c79ad18e 100644 --- a/src/peripheral/cpuid.rs +++ b/src/peripheral/cpuid.rs @@ -66,6 +66,7 @@ pub struct RegisterBlock { /// Type of cache to select on CSSELR writes. #[cfg(not(armv6m))] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum CsselrCacheType { /// Select DCache or unified cache DataOrUnified = 0, diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 59eedbab..e3f3884a 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -97,7 +97,7 @@ pub struct RegisterBlock { /// FPU access mode #[cfg(has_fpu)] -#[derive(Clone, Copy, Debug)] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] pub enum FpuAccessMode { /// FPU is not accessible Disabled, diff --git a/src/peripheral/syst.rs b/src/peripheral/syst.rs index ecefaeae..c1e97102 100644 --- a/src/peripheral/syst.rs +++ b/src/peripheral/syst.rs @@ -18,7 +18,7 @@ pub struct RegisterBlock { } /// SysTick clock source -#[derive(Clone, Copy, Debug)] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] pub enum SystClkSource { /// Core-provided clock Core,