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Prepare for v0.7.4
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CHANGELOG.md

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@@ -7,18 +7,30 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [Unreleased]
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## [v0.7.4] - 2021-12-31
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### Added
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- Added support for additional DWT counters (#349)
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- CPI counter
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- Exception overhead counter
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- LSU counter
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- Folded-instruction counter
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- Added `DWT.set_cycle_count` (#347).
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- Added support for the Cortex-M7 TCM and cache access control registers.
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There is a feature `cm7` to enable access to these.
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There is a feature `cm7` to enable access to these (#352).
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- Add derives for serde, Hash, and PartialOrd to VectActive behind feature
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gates for host-platform use (#363).
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- Support host platforms besides x86_64 (#369).
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- Added `delay::Delay::with_source`, a constructor that lets you specify
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the SysTick clock source (#374).
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### Fixed
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- Fix incorrect AIRCR PRIGROUP mask (#338, #339).
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- Fix nightly users of inline-asm breaking now that the asm macro is removed
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from the prelude (#372).
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### Deprecated
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- `DWT::get_cycle_count` has been deprecated in favor of `DWT::cycle_count`.
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- Functions to get the vector table
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- Wrappers over miscellaneous instructions like `bkpt`
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[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.7.3...HEAD
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[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.7.4...HEAD
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[v0.7.4]: https://github.com/rust-embedded/cortex-m/compare/v0.7.3...v0.7.4
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[v0.7.3]: https://github.com/rust-embedded/cortex-m/compare/v0.7.2...v0.7.3
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[v0.7.2]: https://github.com/rust-embedded/cortex-m/compare/v0.7.1...v0.7.2
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[v0.7.1]: https://github.com/rust-embedded/cortex-m/compare/v0.7.0...v0.7.1

Cargo.toml

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name = "cortex-m"
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readme = "README.md"
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repository = "https://github.com/rust-embedded/cortex-m"
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version = "0.7.3"
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version = "0.7.4"
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edition = "2018"
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links = "cortex-m" # prevent multiple versions of this crate to be linked together
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