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jonathanpallantjonathanpallant
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Merge pull request #7 from thejpster/add-more-msrs
Add more registers, and MPU support
2 parents c2adc89 + 54e68e3 commit 016cdf9

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‎.github/workflows/build.yml

Lines changed: 24 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,8 @@ jobs:
2828
- name: Build
2929
run: |
3030
cargo build --target ${{ matrix.target }}
31+
cargo build --target ${{ matrix.target }} --no-default-features
32+
cargo build --target ${{ matrix.target }} --all-features
3133
3234
# Build the host tools
3335
build-host:
@@ -69,6 +71,8 @@ jobs:
6971
- name: Build
7072
run: |
7173
cargo build --target ${{ matrix.target }} -Zbuild-std=core
74+
cargo build --target ${{ matrix.target }} -Zbuild-std=core --no-default-features
75+
cargo build --target ${{ matrix.target }} -Zbuild-std=core --all-features
7276
7377
# Gather all the above build jobs together for the purposes of getting an overall pass-fail
7478
build-all:
@@ -99,6 +103,8 @@ jobs:
99103
- name: Build docs
100104
run: |
101105
cargo doc --target ${{ matrix.target }}
106+
cargo doc --target ${{ matrix.target }} --no-default-features
107+
cargo doc --target ${{ matrix.target }} --all-features
102108
103109
# Build the docs for the host tools
104110
docs-host:
@@ -184,6 +190,8 @@ jobs:
184190
- name: Clippy
185191
run: |
186192
cargo clippy --target ${{ matrix.target }}
193+
cargo clippy --target ${{ matrix.target }} --no-default-features
194+
cargo clippy --target ${{ matrix.target }} --all-features
187195
188196
# Run clippy on the host tools
189197
clippy-host:
@@ -211,8 +219,22 @@ jobs:
211219
steps:
212220
- run: /bin/true
213221

222+
# Run the unit tests
223+
unit-test:
224+
runs-on: ubuntu-24.04
225+
steps:
226+
- name: Checkout
227+
uses: actions/checkout@v4
228+
- name: Install rust
229+
run: |
230+
rustup install stable
231+
rustup default stable
232+
- name: Run cargo test
233+
run: |
234+
cargo test --manifest-path cortex-r/Cargo.toml
235+
214236
# Run some programs in QEMU
215-
test:
237+
qemu-test:
216238
runs-on: ubuntu-24.04
217239
needs: [build-all]
218240
steps:
@@ -224,6 +246,6 @@ jobs:
224246
# Gather all the above xxx-all jobs together for the purposes of getting an overall pass-fail
225247
all:
226248
runs-on: ubuntu-24.04
227-
needs: [docs-all, build-all, fmt-all, test] # not gating on clippy-all
249+
needs: [docs-all, build-all, fmt-all, unit-test, qemu-test] # not gating on clippy-all
228250
steps:
229251
- run: /bin/true

‎cortex-r-examples/reference/registers-armv7r-none-eabi.out

Lines changed: 35 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,37 @@
11
MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xc15 rev=0x3 }
22
CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
3-
_stack_top: 0x08000000
4-
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
5-
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
3+
PMSA-v7 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }
4+
DRegion 0: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
5+
DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
6+
DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
7+
DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
8+
DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
9+
DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
10+
DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
11+
DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
12+
DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
13+
DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
14+
DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
15+
DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
16+
DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
17+
DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
18+
DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
19+
DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
20+
DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
21+
DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
22+
DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
23+
DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
24+
DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
25+
DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
26+
DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
27+
DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
28+
DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
29+
DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
30+
DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
31+
DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
32+
DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
33+
DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
34+
DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
35+
DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
36+
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=1 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
37+
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=1 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after

‎cortex-r-examples/reference/registers-armv7r-none-eabihf.out

Lines changed: 35 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,37 @@
11
MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xc15 rev=0x3 }
22
CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
3-
_stack_top: 0x08000000
4-
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
5-
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
3+
PMSA-v7 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }
4+
DRegion 0: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
5+
DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
6+
DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
7+
DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
8+
DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
9+
DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
10+
DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
11+
DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
12+
DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
13+
DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
14+
DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
15+
DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
16+
DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
17+
DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
18+
DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
19+
DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
20+
DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
21+
DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
22+
DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
23+
DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
24+
DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
25+
DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
26+
DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
27+
DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
28+
DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
29+
DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
30+
DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
31+
DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
32+
DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
33+
DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
34+
DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
35+
DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
36+
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=1 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
37+
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=1 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after

‎cortex-r-examples/src/bin/generic_timer.rs

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
//! Generic-timer example for Arm Cortex-R52
2+
3+
#![no_std]
4+
#![no_main]
5+
6+
// pull in our start-up code
7+
use cortex_r_examples as _;
8+
9+
use semihosting::println;
10+
11+
/// The entry-point to the Rust application.
12+
///
13+
/// It is called by the start-up code in `cortex-m-rt`.
14+
#[no_mangle]
15+
pub extern "C" fn kmain() {
16+
main();
17+
semihosting::process::exit(0);
18+
}
19+
20+
/// A placeholder function so that the workspace still builds
21+
#[cfg(not(arm_architecture = "v8-r"))]
22+
fn main() {
23+
println!("No generic timers on this platform");
24+
}
25+
26+
/// Let's test some timers!
27+
#[cfg(arm_architecture = "v8-r")]
28+
fn main() {
29+
use cortex_r::generic_timer::{El1PhysicalTimer, El1VirtualTimer, GenericTimer};
30+
let cntfrq = cortex_r::register::Cntfrq::read().0;
31+
println!("cntfrq = {:.03} MHz", cntfrq as f32 / 1_000_000.0);
32+
33+
let delay_ticks = cntfrq * 2;
34+
35+
let mut pgt = unsafe { El1PhysicalTimer::new() };
36+
let mut vgt = unsafe { El1VirtualTimer::new() };
37+
38+
let pgt_ref: &mut dyn GenericTimer = &mut pgt;
39+
let vgt_ref: &mut dyn GenericTimer = &mut vgt;
40+
41+
for (timer, name) in [(pgt_ref, "physical"), (vgt_ref, "virtual")] {
42+
println!("Using {} timer ************************", name);
43+
44+
println!("Print five, one per second...");
45+
for i in 0..5 {
46+
println!("i = {}", i);
47+
timer.delay_ms(1000);
48+
}
49+
50+
let now = timer.counter();
51+
println!("{} is now: {}", name, now);
52+
println!("Waiting for {} {} ticks to count up...", delay_ticks, name);
53+
timer.counter_compare_set(now + delay_ticks as u64);
54+
timer.enable(true);
55+
while !timer.interrupt_status() {
56+
core::hint::spin_loop();
57+
}
58+
println!("Matched! {} count now {}", name, timer.counter());
59+
60+
println!(
61+
"Waiting for {} {} ticks to count down...",
62+
delay_ticks, name
63+
);
64+
timer.countdown_set(delay_ticks);
65+
while !timer.interrupt_status() {
66+
core::hint::spin_loop();
67+
}
68+
println!(
69+
"{} countdown hit zero! (and is now {})",
70+
name,
71+
timer.countdown() as i32
72+
);
73+
}
74+
}

‎cortex-r-examples/src/bin/gic.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ fn dump_cpsr() {
4242
/// Called by [`kmain`].
4343
fn main() -> Result<(), core::fmt::Error> {
4444
// Get the GIC address by reading CBAR
45-
let periphbase = cortex_r::register::Cbar::read().periphbase();
45+
let periphbase = cortex_r::register::ImpCbar::read().periphbase();
4646
println!("Found PERIPHBASE {:010p}", periphbase);
4747
let gicd_base = periphbase.wrapping_byte_add(GICD_BASE_OFFSET);
4848
let gicr_base = periphbase.wrapping_byte_add(GICR_BASE_OFFSET);

‎cortex-r-examples/src/bin/registers.rs

Lines changed: 114 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -9,27 +9,135 @@ use cortex_r_examples as _;
99

1010
use semihosting::println;
1111

12-
extern "C" {
13-
static _stack_top: u32;
14-
}
15-
1612
/// The entry-point to the Rust application.
1713
///
1814
/// It is called by the start-up code in `cortex-m-rt`.
1915
#[no_mangle]
2016
pub extern "C" fn kmain() {
17+
chip_info();
18+
#[cfg(arm_architecture = "v7-r")]
19+
mpu_pmsa_v7();
20+
#[cfg(arm_architecture = "v8-r")]
21+
mpu_pmsa_v8();
22+
test_changing_sctlr();
23+
semihosting::process::exit(0);
24+
}
25+
26+
fn chip_info() {
2127
println!("{:?}", cortex_r::register::Midr::read());
2228
println!("{:?}", cortex_r::register::Cpsr::read());
2329
#[cfg(arm_architecture = "v8-r")]
2430
{
25-
println!("{:?}", cortex_r::register::Cbar::read());
31+
println!("{:?}", cortex_r::register::ImpCbar::read());
2632
println!("{:?}", cortex_r::register::Vbar::read());
2733
// This only works in EL2 and start-up put us in EL1
2834
// println!("{:?}", cortex_r::register::Hvbar::read());
2935
}
36+
}
37+
38+
#[cfg(arm_architecture = "v7-r")]
39+
fn mpu_pmsa_v7() {
40+
use cortex_r::{
41+
pmsav7::{CacheablePolicy, Config, MemAttr, Mpu, Region, RegionSize},
42+
register::Mpuir,
43+
};
44+
45+
// How many regions?
46+
let mpuir = Mpuir::read();
47+
println!("PMSA-v7 MPUIR: {:?}", mpuir);
48+
49+
// Make an MPU driver
50+
let mut mpu = unsafe { Mpu::new() };
51+
52+
// Look at the existing config
53+
for idx in 0..mpu.num_iregions() {
54+
if let Some(region) = mpu.get_iregion(idx) {
55+
println!("IRegion {}: {:?}", idx, region);
56+
}
57+
}
58+
for idx in 0..mpu.num_dregions() {
59+
if let Some(region) = mpu.get_dregion(idx) {
60+
println!("DRegion {}: {:?}", idx, region);
61+
}
62+
}
3063

31-
println!("_stack_top: {:010p}", core::ptr::addr_of!(_stack_top));
64+
// Load a config (but don't enable it)
65+
mpu.configure(&Config {
66+
background_config: true,
67+
dregions: &[Region {
68+
base: 0x2000_0000 as *mut u8,
69+
size: RegionSize::_16M,
70+
subregion_mask: 0x00,
71+
enabled: true,
72+
no_exec: false,
73+
mem_attr: MemAttr::Cacheable {
74+
inner: CacheablePolicy::WriteThroughNoWriteAllocate,
75+
outer: CacheablePolicy::NonCacheable,
76+
shareable: true,
77+
},
78+
}],
79+
iregions: &[],
80+
})
81+
.unwrap();
3282

83+
// Look at the new config
84+
for idx in 0..mpu.num_dregions() {
85+
if let Some(region) = mpu.get_dregion(idx) {
86+
println!("DRegion {}: {:?}", idx, region);
87+
}
88+
}
89+
}
90+
91+
#[cfg(arm_architecture = "v8-r")]
92+
fn mpu_pmsa_v8() {
93+
use cortex_r::{
94+
pmsav8::{
95+
AccessPerms, Cacheable, Config, El1Mpu, MemAttr, Region, RwAllocPolicy, Shareability,
96+
},
97+
register::Mpuir,
98+
};
99+
100+
// How many regions?
101+
let mpuir = Mpuir::read();
102+
println!("PMSA-v8 MPUIR: {:?}", mpuir);
103+
104+
// Make an MPU driver
105+
let mut mpu = unsafe { El1Mpu::new() };
106+
107+
// Look at the existing config
108+
for idx in 0..mpu.num_regions() {
109+
if let Some(region) = mpu.get_region(idx) {
110+
println!("Region {}: {:?}", idx, region);
111+
}
112+
}
113+
114+
// Load a config (but don't enable it)
115+
mpu.configure(&Config {
116+
background_config: true,
117+
regions: &[Region {
118+
range: 0x0000_0000 as *mut u8..=0x3FFF_FFFF as *mut u8,
119+
shareability: Shareability::OuterShareable,
120+
access: AccessPerms::ReadWrite,
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no_exec: true,
122+
mair: 0,
123+
enable: true,
124+
}],
125+
memory_attributes: &[MemAttr::NormalMemory {
126+
outer: Cacheable::WriteThroughNonTransient(RwAllocPolicy::RW),
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inner: Cacheable::WriteThroughNonTransient(RwAllocPolicy::RW),
128+
}],
129+
})
130+
.unwrap();
131+
132+
// Look at the new config
133+
for idx in 0..mpu.num_regions() {
134+
if let Some(region) = mpu.get_region(idx) {
135+
println!("Region {}: {:?}", idx, region);
136+
}
137+
}
138+
}
139+
140+
fn test_changing_sctlr() {
33141
println!(
34142
"{:?} before setting C, I and Z",
35143
cortex_r::register::Sctlr::read()
@@ -40,6 +148,4 @@ pub extern "C" fn kmain() {
40148
w.set_z(true);
41149
});
42150
println!("{:?} after", cortex_r::register::Sctlr::read());
43-
44-
semihosting::process::exit(0);
45151
}

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