From 5c0801499b61a3c36e5cdb22c3ca4ab6f8d43f0c Mon Sep 17 00:00:00 2001
From: Javi Merino <merino.jav@gmail.com>
Date: Sun, 30 Oct 2022 11:01:04 +0000
Subject: [PATCH] Add all memory barrier variants

The Arm A-profile A64 Instruction Set Architecture[0] specifies many
memory barrier variants.  In the 2022-09 version of the document, they
are in pages 348 and 351 for the DMB and DSB respectively.

The cortex-a crate only supports SY, ISH and ISHST currently.  Add the
rest.

[0] https://developer.arm.com/documentation/ddi0602/
---
 src/asm/barrier.rs | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/asm/barrier.rs b/src/asm/barrier.rs
index 5322d65..dec0e12 100644
--- a/src/asm/barrier.rs
+++ b/src/asm/barrier.rs
@@ -55,12 +55,30 @@ macro_rules! dmb_dsb {
 }
 
 pub struct SY;
+pub struct ST;
+pub struct LD;
 pub struct ISH;
 pub struct ISHST;
+pub struct ISHLD;
+pub struct NSH;
+pub struct NSHST;
+pub struct NSHLD;
+pub struct OSH;
+pub struct OSHST;
+pub struct OSHLD;
 
+dmb_dsb!(SY);
+dmb_dsb!(ST);
+dmb_dsb!(LD);
 dmb_dsb!(ISH);
 dmb_dsb!(ISHST);
-dmb_dsb!(SY);
+dmb_dsb!(ISHLD);
+dmb_dsb!(NSH);
+dmb_dsb!(NSHST);
+dmb_dsb!(NSHLD);
+dmb_dsb!(OSH);
+dmb_dsb!(OSHST);
+dmb_dsb!(OSHLD);
 
 impl sealed::Isb for SY {
     #[inline(always)]