diff --git a/src/registers.rs b/src/registers.rs index ba6c344..2805762 100644 --- a/src/registers.rs +++ b/src/registers.rs @@ -6,6 +6,9 @@ #[macro_use] mod macros; +mod actlr_el1; +mod actlr_el2; +mod actlr_el3; mod ccsidr_el1; mod clidr_el1; mod cntfrq_el0; @@ -19,6 +22,8 @@ mod cntv_tval_el0; mod cntvct_el0; mod cntvoff_el2; mod csselr_el1; +mod cpacr_el1; +mod dacr32_el2; mod currentel; mod daif; mod elr_el1; @@ -61,6 +66,9 @@ mod ttbr1_el1; mod vbar_el1; mod vbar_el2; +pub use actlr_el1::ACTLR_EL1; +pub use actlr_el2::ACTLR_EL2; +pub use actlr_el3::ACTLR_EL3; pub use ccsidr_el1::CCSIDR_EL1; pub use clidr_el1::CLIDR_EL1; pub use cntfrq_el0::CNTFRQ_EL0; @@ -74,6 +82,8 @@ pub use cntv_tval_el0::CNTV_TVAL_EL0; pub use cntvct_el0::CNTVCT_EL0; pub use cntvoff_el2::CNTVOFF_EL2; pub use csselr_el1::CSSELR_EL1; +pub use cpacr_el1::CPACR_EL1; +pub use dacr32_el2::DACR32_EL2; pub use currentel::CurrentEL; pub use daif::DAIF; pub use elr_el1::ELR_EL1; diff --git a/src/registers/actlr_el1.rs b/src/registers/actlr_el1.rs new file mode 100644 index 0000000..af04d58 --- /dev/null +++ b/src/registers/actlr_el1.rs @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2022 by the author(s) +// +// Author(s): +// - Valentin B. + +//! Auxiliary Control Register - EL1 +//! +//! Provides implementation-defined configuration and control options for execution +//! at EL1 and EL0. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ACTLR_EL1", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ACTLR_EL1", "x"); +} + +pub const ACTLR_EL1: Reg = Reg; diff --git a/src/registers/actlr_el2.rs b/src/registers/actlr_el2.rs new file mode 100644 index 0000000..1f1be89 --- /dev/null +++ b/src/registers/actlr_el2.rs @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2022 by the author(s) +// +// Author(s): +// - Valentin B. + +//! Auxiliary Control Register - EL2 +//! +//! Provides implementation-defined configuration and control options for execution +//! at EL2. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ACTLR_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ACTLR_EL2", "x"); +} + +pub const ACTLR_EL2: Reg = Reg; diff --git a/src/registers/actlr_el3.rs b/src/registers/actlr_el3.rs new file mode 100644 index 0000000..fd7700b --- /dev/null +++ b/src/registers/actlr_el3.rs @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2022 by the author(s) +// +// Author(s): +// - Valentin B. + +//! Auxiliary Control Register - EL3 +//! +//! Provides implementation-defined configuration and control options for execution +//! at EL3. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ACTLR_EL3", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ACTLR_EL3", "x"); +} + +pub const ACTLR_EL3: Reg = Reg; diff --git a/src/registers/cpacr_el1.rs b/src/registers/cpacr_el1.rs new file mode 100644 index 0000000..271ed31 --- /dev/null +++ b/src/registers/cpacr_el1.rs @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2022 by the author(s) +// +// Author(s): +// - Valentin B. + +//! Architectural Feature Access Control Register - EL1 +//! +//! Controls access to trace, SVE, and Advanced SIMD and floating-point functionality. + +use tock_registers::{ + interfaces::{Readable, Writeable}, + register_bitfields, +}; + +register_bitfields! {u64, + pub CPACR_EL1 [ + /// Traps EL0 and EL1 System register accesses to all implemented trace + /// registers from both Execution states to EL1, or to EL2 when it is + /// implemented and enabled in the current Security state and HCR_EL2.TGE + /// is 1, as follows: + /// + /// - In AArch64 state, accesses to trace registers are trapped, reported + /// using ESR_ELx.EC value 0x18. + /// + /// - In AArch32 state, MRC and MCR accesses to trace registers are trapped, + /// reported using ESR_ELx.EC value 0x05. + /// + /// - In AArch32 state, MCR and MCRR accesses to trace registers are trapped, + /// reported using ESR_ELx.EC value 0x0C. + /// + /// System register accesses to the trace registers can have side-effects. + /// When a System register access is trapped, any side-effects that are + /// normally associated with the access do not occur before the exception is + /// taken. + /// + /// If System register access to the trace functionality is not implemented, + /// this bit is considered reserved. + /// + /// On a Warm reset, this field resets to an undefined value. + TTA OFFSET(28) NUMBITS(1) [ + /// This control does not cause any instructions to be trapped. + NoTrap = 0b0, + /// This control causes EL0 and EL1 System register accesses to all + /// implemented trace registers to be trapped. + TrapTrace = 0b1 + ], + + /// Traps execution at EL0 and EL1 of instructions that access the Advanced SIMD + /// and floating-point registers from both Execution states to EL1, reported using + /// ESR_ELx.EC value 0x07, or to EL2 reported using ESR_ELx.EC value 0x00 when EL2 + /// is implemented and enabled in the current Security state and HCR_EL2.TGE is 1, + /// as follows: + /// + /// - In AArch64 state, accesses to FPCR, FPSR, any of the SIMD and floating-point + /// registers V0-V31, including their views as D0-31 registers or S0-31 registers. + /// + /// - In AArch32 state, FPSCR, and any of the SIMD and floating-point registers + /// Q0-15, including their views as D0-31 registers or S0-31 registers. + /// + /// Traps execution at EL1 and EL0 of SVE instructions to EL1, or to EL2 when El2 + /// is implemented and enabled for the current Security state and HCR_EL2.TGE is 1. + /// The exception is reported using ESR_ELx.EC value 0x07. + /// + /// A trap taken as a result of [`CPACR_EL1::ZEN`] has precendence over a trap taken + /// as a result of [`CPACR_EL1::FPEN`]. + /// + /// On a Warm reset, this fields resets to an undefined value. + FPEN OFFSET(20) NUMBITS(2) [ + /// This control causes execution of these instructions at EL0 and EL1 to be trapped. + TrapEl0El1 = 0b00, + /// This control causes execution of these instructions at EL0 to be trapped, but + /// does not cause any instructions at EL1 to be trapped. + TrapEl0 = 0b01, + /// This control causes execution of these instructions at EL1 and EL0 to be trapped. + TrapEl1El0 = 0b10, + /// This control does not cause execution of any instructions to be trapped. + TrapNothing = 0b11 + ], + + /// **When FEAT_SVE is implemented:** + /// + /// Traps execution at EL1 and EL0 of SVE instructions and instructions that directly + /// access the ZCR_EL1 Systme register to EL1, or to EL2 when El2 is implemented in the + /// current Security state and HCR_EL2.TGE is 1. + /// + /// The exception is reported using ESR_ELx.EC value 0x19. + /// + /// A trap taken as a result of CPACR_EL1.ZEN has precedence over a trap taken as a result + /// of CPACR_EL1.FPEN. + /// + /// On a Warm reset, this field resets to an undefined value. + /// + /// **Otherwise:** + /// + /// Reserved. + ZEN OFFSET(16) NUMBITS(2) [ + /// This control causes execution of these instructions at EL0 and EL1 to be trapped. + TrapEl0El1 = 0b00, + /// This control causes execution of these instructions at EL0 to be trapped, but + /// does not cause execution of any instructions at EL1 to be trapped. + TrapEl0 = 0b01, + /// This control causes execution of these instructions at EL1 and EL0 to be trapped. + TrapEl1El0 = 0b10, + /// This control does not cause execution of any instructions to be trapped. + TrapNothing = 0b11 + ] + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "CPACR_EL1", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "CPACR_EL1", "x"); +} + +pub const CPACR_EL1: Reg = Reg; diff --git a/src/registers/dacr32_el2.rs b/src/registers/dacr32_el2.rs new file mode 100644 index 0000000..b501a33 --- /dev/null +++ b/src/registers/dacr32_el2.rs @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2022 by the author(s) +// +// Author(s): +// - Valentin B. + +//! Domain Access Control Register - EL2 +//! +//! Allows access to the AArch32 DACR register from AArch64 state only. Its value +//! has no effect on execution in AArch64 state. + +use tock_registers::{ + interfaces::{Readable, Writeable}, + register_bitfields, +}; + +register_bitfields! {u64, + pub DACR32_EL2 [ + /// Domain 15 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D15 OFFSET(30) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 14 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D14 OFFSET(28) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 13 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D13 OFFSET(26) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 12 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D12 OFFSET(24) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 11 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D11 OFFSET(22) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 10 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D10 OFFSET(20) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 9 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D9 OFFSET(18) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 8 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D8 OFFSET(16) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 7 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D7 OFFSET(14) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 6 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D6 OFFSET(12) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 5 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D5 OFFSET(10) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 4 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D4 OFFSET(8) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 3 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D3 OFFSET(6) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 2 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D2 OFFSET(4) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 1 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D1 OFFSET(2) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ], + + /// Domain 0 access permission. + /// + /// Values other than the pre-defined ones are reserved. + /// + /// NOTE: On Warm reset, this field resets to an undefined value. + D0 OFFSET(0) NUMBITS(2) [ + /// No access. Any access to the domain generates a Domain fault. + NoAccess = 0b00, + /// Client access. Accesses are not checked against the permission bits + /// in the translation tables. + Client = 0b01, + /// Manager access. Accesses are not checked against the permission bits + /// in the translation tables. + Manager = 0b11 + ] + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = DACR32_EL2::Register; + + sys_coproc_read_raw!(u64, "DACR32_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = DACR32_EL2::Register; + + sys_coproc_write_raw!(u64, "DACR32_EL2", "x"); +} + +pub const DACR32_EL2: Reg = Reg;