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[LLVM][XTHeadVector] Implement 16.7-16.8 viota/vid (llvm#98)
* [LLVM][XTHeadVector] Implement 16.7-16.8 `viota/vid` * [LLVM][XTHeadVector] Test 16.7-16.8 `viota/vid`
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‎llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

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Original file line numberDiff line numberDiff line change
@@ -924,4 +924,48 @@ let TargetPrefix = "riscv" in {
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// 16.6. vmsof.m set-only-first mask bit
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defm th_vmsof : RISCVMaskedUnaryMOut;
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// 16.7. Vector Iota Operations
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// Output: (vector)
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// Input: (passthru, mask type input, vl)
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def int_riscv_th_viota
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: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_anyint_ty],
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[IntrNoMem]>, RISCVVIntrinsic {
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let VLOperand = 2;
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}
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// Output: (vector)
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// Input: (maskedoff, mask type vector_in, mask, vl)
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def int_riscv_th_viota_mask
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: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_anyint_ty],
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[IntrNoMem]>, RISCVVIntrinsic {
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let VLOperand = 3;
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}
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// 16.8. Vector Element Index Operations
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// Output: (vector)
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// Input: (passthru, vl)
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def int_riscv_th_vid
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: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyint_ty],
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[IntrNoMem]>, RISCVVIntrinsic {
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let VLOperand = 1;
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}
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// Output: (vector)
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// Input: (maskedoff, mask, vl)
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def int_riscv_th_vid_mask
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: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_anyint_ty],
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[IntrNoMem]>, RISCVVIntrinsic {
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let VLOperand = 2;
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}
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} // TargetPrefix = "riscv"

‎llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

Lines changed: 141 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1757,6 +1757,29 @@ class XVPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
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let HasSEWOp = 1;
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}
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class XVPseudoNullaryNoMask<VReg RegClass>:
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Pseudo<(outs RegClass:$rd),
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(ins RegClass:$merge, AVL:$vl, ixlenimm:$sew), []>, RISCVVPseudo {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let Constraints = "$rd = $merge";
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let HasVLOp = 1;
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let HasSEWOp = 1;
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}
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class XVPseudoNullaryMask<VReg RegClass>:
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Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
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(ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, AVL:$vl,
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ixlenimm:$sew), []>, RISCVVPseudo {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let Constraints ="$rd = $merge";
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let HasVLOp = 1;
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let HasSEWOp = 1;
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}
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multiclass XVPseudoBinary<VReg RetClass,
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VReg Op1Class,
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DAGOperand Op2Class,
@@ -2596,6 +2619,38 @@ multiclass XVPseudoVSFS_M {
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}
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}
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multiclass XVPseudoVIOT_M {
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defvar constraint = "@earlyclobber $rd";
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foreach m = MxListXTHeadV in {
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defvar mx = m.MX;
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defvar WriteVMIotV_MX = !cast<SchedWrite>("WriteVMIotV_" # mx);
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defvar ReadVMIotV_MX = !cast<SchedRead>("ReadVMIotV_" # mx);
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let VLMul = m.value in {
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def "_" # m.MX : XVPseudoUnaryNoMask<m.vrclass, VR, constraint>,
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Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
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def "_" # m.MX # "_MASK" : XVPseudoUnaryMask<m.vrclass, VR, constraint>,
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RISCVMaskedPseudo<MaskIdx=2>,
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Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
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}
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}
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}
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multiclass XVPseudoVID_V {
2639+
foreach m = MxListXTHeadV in {
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defvar mx = m.MX;
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defvar WriteVMIdxV_MX = !cast<SchedWrite>("WriteVMIdxV_" # mx);
2642+
defvar ReadVMIdxV_MX = !cast<SchedRead>("ReadVMIdxV_" # mx);
2643+
2644+
let VLMul = m.value in {
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def "_V_" # m.MX : XVPseudoNullaryNoMask<m.vrclass>,
2646+
Sched<[WriteVMIdxV_MX, ReadVMask]>;
2647+
def "_V_" # m.MX # "_MASK" : XVPseudoNullaryMask<m.vrclass>,
2648+
RISCVMaskedPseudo<MaskIdx=1>,
2649+
Sched<[WriteVMIdxV_MX, ReadVMask]>;
2650+
}
2651+
}
2652+
}
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25992654
//===----------------------------------------------------------------------===//
26002655
// Helpers to define the intrinsic patterns for the XTHeadVector extension.
26012656
//===----------------------------------------------------------------------===//
@@ -3066,6 +3121,24 @@ multiclass XVPatBinaryM_MM<string intrinsic, string instruction> {
30663121
mti.Log2SEW, VR, VR>;
30673122
}
30683123

3124+
multiclass XVPatNullaryV<string intrinsic, string instruction> {
3125+
foreach vti = AllIntegerXVectors in {
3126+
let Predicates = GetXVTypePredicates<vti>.Predicates in {
3127+
def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
3128+
(vti.Vector vti.RegClass:$merge),
3129+
VLOpFrag)),
3130+
(!cast<Instruction>(instruction#"_V_" # vti.LMul.MX)
3131+
vti.RegClass:$merge, GPR:$vl, vti.Log2SEW)>;
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def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic # "_mask")
3133+
(vti.Vector vti.RegClass:$merge),
3134+
(vti.Mask V0), VLOpFrag)),
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(!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_MASK")
3136+
vti.RegClass:$merge, (vti.Mask V0),
3137+
GPR:$vl, vti.Log2SEW)>;
3138+
}
3139+
}
3140+
}
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30693142
multiclass XVPatNullaryM<string intrinsic, string inst> {
30703143
foreach mti = AllXMasks in
30713144
def : Pat<(mti.Mask (!cast<Intrinsic>(intrinsic)
@@ -3120,6 +3193,63 @@ multiclass XVPatUnaryM_M<string intrinsic,
31203193
}
31213194
}
31223195

3196+
class XVPatUnaryNoMask<string intrinsic_name,
3197+
string inst,
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string kind,
3199+
ValueType result_type,
3200+
ValueType op2_type,
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int log2sew,
3202+
LMULInfo vlmul,
3203+
VReg result_reg_class,
3204+
VReg op2_reg_class,
3205+
bit isSEWAware = 0> :
3206+
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
3207+
(result_type result_reg_class:$merge),
3208+
(op2_type op2_reg_class:$rs2),
3209+
VLOpFrag)),
3210+
(!cast<Instruction>(
3211+
!if(isSEWAware,
3212+
inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),
3213+
inst#"_"#kind#"_"#vlmul.MX))
3214+
(result_type result_reg_class:$merge),
3215+
(op2_type op2_reg_class:$rs2),
3216+
GPR:$vl, log2sew)>;
3217+
3218+
class XVPatUnaryMask<string intrinsic_name,
3219+
string inst,
3220+
string kind,
3221+
ValueType result_type,
3222+
ValueType op2_type,
3223+
ValueType mask_type,
3224+
int log2sew,
3225+
LMULInfo vlmul,
3226+
VReg result_reg_class,
3227+
VReg op2_reg_class,
3228+
bit isSEWAware = 0> :
3229+
Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
3230+
(result_type result_reg_class:$merge),
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(op2_type op2_reg_class:$rs2),
3232+
(mask_type V0),
3233+
VLOpFrag)),
3234+
(!cast<Instruction>(
3235+
!if(isSEWAware,
3236+
inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
3237+
inst#"_"#kind#"_"#vlmul.MX#"_MASK"))
3238+
(result_type result_reg_class:$merge),
3239+
(op2_type op2_reg_class:$rs2),
3240+
(mask_type V0), GPR:$vl, log2sew)>;
3241+
3242+
multiclass XVPatUnaryV_M<string intrinsic, string instruction> {
3243+
foreach vti = AllIntegerXVectors in {
3244+
let Predicates = GetXVTypePredicates<vti>.Predicates in {
3245+
def : XVPatUnaryNoMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
3246+
vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
3247+
def : XVPatUnaryMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
3248+
vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
3249+
}
3250+
}
3251+
}
3252+
31233253
multiclass XVPatCompare_VI<string intrinsic, string inst,
31243254
ImmLeaf ImmType> {
31253255
foreach vti = AllIntegerXVectors in {
@@ -4069,4 +4199,15 @@ defm : XVPatUnaryM_M<"int_riscv_th_vmsbf", "PseudoTH_VMSBF">;
40694199
defm : XVPatUnaryM_M<"int_riscv_th_vmsif", "PseudoTH_VMSIF">;
40704200
defm : XVPatUnaryM_M<"int_riscv_th_vmsof", "PseudoTH_VMSOF">;
40714201

4202+
//===----------------------------------------------------------------------===//
4203+
// 16.7. Vector Iota Operations
4204+
// 16.8. Vector Element Index Operations
4205+
//===----------------------------------------------------------------------===//
4206+
defm PseudoTH_VIOTA_M: XVPseudoVIOT_M;
4207+
defm PseudoTH_VID : XVPseudoVID_V;
4208+
4209+
// Patterns
4210+
defm : XVPatUnaryV_M<"int_riscv_th_viota", "PseudoTH_VIOTA">;
4211+
defm : XVPatNullaryV<"int_riscv_th_vid", "PseudoTH_VID">;
4212+
40724213
include "RISCVInstrInfoXTHeadVVLPatterns.td"

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