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[LLVM][XTHeadVector] support nvx1i1/nvx2i1/nvx4i1 operands for vector mask operations (llvm#120)
* [LLVM][XTHeadVector] support `vbool16/32/64` for vector mask operations * [LLVM][XTHeadVector] correctly expand pseudos for `vmset/vmclr` * [LLVM][XTHeadVector] update corresponding tests * [LLVM][XTHeadVector] update tests for `vmsof/vmsbf/vmsif` * [LLVM][XTHeadVector] update tests for `vmfirst/vmpopc` * [LLVM][XTHeadVector] update tests for `vmfirst/vmpopc`
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-21
lines changed

17 files changed

+1358
-21
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -146,18 +146,24 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
146146
case RISCV::PseudoVMSET_M_B64:
147147
// vmset.m vd => vmxnor.mm vd, vd, vd
148148
return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
149+
case RISCV::PseudoTH_VMCLR_M_B1:
150+
case RISCV::PseudoTH_VMCLR_M_B2:
151+
case RISCV::PseudoTH_VMCLR_M_B4:
149152
case RISCV::PseudoTH_VMCLR_M_B8:
150153
case RISCV::PseudoTH_VMCLR_M_B16:
151154
case RISCV::PseudoTH_VMCLR_M_B32:
152155
case RISCV::PseudoTH_VMCLR_M_B64:
153-
// th.vmclr.m vd => th.vmxor.mm vd, vd, vd
154-
return expandVMSET_VMCLR(MBB, MBBI, RISCV::TH_VMXOR_MM);
156+
// th.vmclr.m vd => th.vmxor.mm vd, vd, vd
157+
return expandVMSET_VMCLR(MBB, MBBI, RISCV::TH_VMXOR_MM);
158+
case RISCV::PseudoTH_VMSET_M_B1:
159+
case RISCV::PseudoTH_VMSET_M_B2:
160+
case RISCV::PseudoTH_VMSET_M_B4:
155161
case RISCV::PseudoTH_VMSET_M_B8:
156162
case RISCV::PseudoTH_VMSET_M_B16:
157163
case RISCV::PseudoTH_VMSET_M_B32:
158164
case RISCV::PseudoTH_VMSET_M_B64:
159-
// th.vmset.m vd => th.vmxnor.mm vd, vd, vd
160-
return expandVMSET_VMCLR(MBB, MBBI, RISCV::TH_VMXNOR_MM);
165+
// th.vmset.m vd => th.vmxnor.mm vd, vd, vd
166+
return expandVMSET_VMCLR(MBB, MBBI, RISCV::TH_VMXNOR_MM);
161167
}
162168

163169
return false;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

Lines changed: 26 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -145,15 +145,32 @@ defset list<VTypeInfoToWide> AllWidenableIntToFloatXVectors = {
145145
def : VTypeInfoToWide<VI32M4, VF64M8>;
146146
}
147147

148+
class XMTypeInfo<ValueType Mas, int Sew, int Log2Sew, LMULInfo M, string Bx> {
149+
ValueType Mask = Mas;
150+
// {SEW, VLMul} values set a valid VType to deal with this mask type.
151+
int SEW = Sew;
152+
int Log2SEW = Log2Sew;
153+
LMULInfo LMul = M;
154+
string BX = Bx; // Appendix of mask operations.
155+
// The pattern fragment which produces the AVL operand, representing the
156+
// "natural" vector length for this mask type. For scalable masks this is
157+
// VLMax.
158+
OutPatFrag AVL = VLMax;
159+
}
160+
148161
// Redefine `AllMasks` from RISCVInstrInfoVPseudos.td to remove fractionally-grouped register groups.
149-
// TODO: riscv-v-intrinsics.pdf declares there are functions accepting vbool<16,32,64>_t, but they need
150-
// to be connected to MF2, MF4, MF8, which are not supported by the 'V' extension 0.7.1.
151-
defset list<MTypeInfo> AllXMasks = {
162+
defset list<XMTypeInfo> AllXMasks = {
152163
// vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
153-
def : MTypeInfo<vbool8_t, V_M1, "B8">;
154-
def : MTypeInfo<vbool4_t, V_M2, "B16">;
155-
def : MTypeInfo<vbool2_t, V_M4, "B32">;
156-
def : MTypeInfo<vbool1_t, V_M8, "B64">;
164+
def : XMTypeInfo<vbool8_t, 8, 3, V_M1, "B8">;
165+
def : XMTypeInfo<vbool4_t, 8, 3, V_M2, "B16">;
166+
def : XMTypeInfo<vbool2_t, 8, 3, V_M4, "B32">;
167+
def : XMTypeInfo<vbool1_t, 8, 3, V_M8, "B64">;
168+
169+
// Cannot assume SEW=8, as <n> = SEW/LMUL, so LMUL = MF2/MF4/MF8, which is not supported.
170+
// Instead, we assume LMUL=1, so SEW = <n> * LMUL.
171+
def : XMTypeInfo<vbool64_t, 64, 6, V_M1, "B1">;
172+
def : XMTypeInfo<vbool32_t, 32, 5, V_M1, "B2">;
173+
def : XMTypeInfo<vbool16_t, 16, 4, V_M1, "B4">;
157174
}
158175

159176
class GetXVTypePredicates<VTypeInfo vti> {
@@ -3981,7 +3998,7 @@ multiclass XVPatUnaryS_M<string intrinsic_name,
39813998

39823999
class XVPatMaskUnaryNoMask<string intrinsic_name,
39834000
string inst,
3984-
MTypeInfo mti> :
4001+
XMTypeInfo mti> :
39854002
Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name)
39864003
(mti.Mask VR:$rs2),
39874004
VLOpFrag)),
@@ -3992,7 +4009,7 @@ class XVPatMaskUnaryNoMask<string intrinsic_name,
39924009

39934010
class XVPatMaskUnaryMask<string intrinsic_name,
39944011
string inst,
3995-
MTypeInfo mti> :
4012+
XMTypeInfo mti> :
39964013
Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name#"_mask")
39974014
(mti.Mask VR:$merge),
39984015
(mti.Mask VR:$rs2),

‎llvm/test/CodeGen/RISCV/rvv0p71/vmand.ll

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,66 @@
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
55
; RUN: -verify-machineinstrs | FileCheck %s
66

7+
declare <vscale x 1 x i1> @llvm.riscv.th.vmand.nxv1i1(
8+
<vscale x 1 x i1>,
9+
<vscale x 1 x i1>,
10+
iXLen);
11+
12+
define <vscale x 1 x i1> @intrinsic_vmand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
13+
; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1:
14+
; CHECK: # %bb.0: # %entry
15+
; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1
16+
; CHECK-NEXT: th.vmand.mm v0, v0, v8
17+
; CHECK-NEXT: ret
18+
entry:
19+
%a = call <vscale x 1 x i1> @llvm.riscv.th.vmand.nxv1i1(
20+
<vscale x 1 x i1> %0,
21+
<vscale x 1 x i1> %1,
22+
iXLen %2)
23+
24+
ret <vscale x 1 x i1> %a
25+
}
26+
27+
declare <vscale x 2 x i1> @llvm.riscv.th.vmand.nxv2i1(
28+
<vscale x 2 x i1>,
29+
<vscale x 2 x i1>,
30+
iXLen);
31+
32+
define <vscale x 2 x i1> @intrinsic_vmand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
33+
; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1:
34+
; CHECK: # %bb.0: # %entry
35+
; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1
36+
; CHECK-NEXT: th.vmand.mm v0, v0, v8
37+
; CHECK-NEXT: ret
38+
entry:
39+
%a = call <vscale x 2 x i1> @llvm.riscv.th.vmand.nxv2i1(
40+
<vscale x 2 x i1> %0,
41+
<vscale x 2 x i1> %1,
42+
iXLen %2)
43+
44+
ret <vscale x 2 x i1> %a
45+
}
46+
47+
declare <vscale x 4 x i1> @llvm.riscv.th.vmand.nxv4i1(
48+
<vscale x 4 x i1>,
49+
<vscale x 4 x i1>,
50+
iXLen);
51+
52+
define <vscale x 4 x i1> @intrinsic_vmand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
53+
; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1:
54+
; CHECK: # %bb.0: # %entry
55+
; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1
56+
; CHECK-NEXT: th.vmand.mm v0, v0, v8
57+
; CHECK-NEXT: ret
58+
entry:
59+
%a = call <vscale x 4 x i1> @llvm.riscv.th.vmand.nxv4i1(
60+
<vscale x 4 x i1> %0,
61+
<vscale x 4 x i1> %1,
62+
iXLen %2)
63+
64+
ret <vscale x 4 x i1> %a
65+
}
66+
767
declare <vscale x 8 x i1> @llvm.riscv.th.vmand.nxv8i1(
868
<vscale x 8 x i1>,
969
<vscale x 8 x i1>,

‎llvm/test/CodeGen/RISCV/rvv0p71/vmandn.ll

Lines changed: 68 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,73 @@
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
55
; RUN: -verify-machineinstrs | FileCheck %s
66

7+
declare <vscale x 1 x i1> @llvm.riscv.th.vmandnot.nxv1i1(
8+
<vscale x 1 x i1>,
9+
<vscale x 1 x i1>,
10+
iXLen);
11+
12+
define <vscale x 1 x i1> @intrinsic_vmandnot_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
13+
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv1i1:
14+
; CHECK: # %bb.0: # %entry
15+
; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1
16+
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
17+
; CHECK-NEXT: ret
18+
entry:
19+
%a = call <vscale x 1 x i1> @llvm.riscv.th.vmandnot.nxv1i1(
20+
<vscale x 1 x i1> %0,
21+
<vscale x 1 x i1> %1,
22+
iXLen %2)
23+
24+
ret <vscale x 1 x i1> %a
25+
}
26+
27+
declare <vscale x 2 x i1> @llvm.riscv.th.vmandnot.nxv2i1(
28+
<vscale x 2 x i1>,
29+
<vscale x 2 x i1>,
30+
iXLen);
31+
32+
define <vscale x 2 x i1> @intrinsic_vmandnot_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
33+
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv2i1:
34+
; CHECK: # %bb.0: # %entry
35+
; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1
36+
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
37+
; CHECK-NEXT: ret
38+
entry:
39+
%a = call <vscale x 2 x i1> @llvm.riscv.th.vmandnot.nxv2i1(
40+
<vscale x 2 x i1> %0,
41+
<vscale x 2 x i1> %1,
42+
iXLen %2)
43+
44+
ret <vscale x 2 x i1> %a
45+
}
46+
47+
declare <vscale x 4 x i1> @llvm.riscv.th.vmandnot.nxv4i1(
48+
<vscale x 4 x i1>,
49+
<vscale x 4 x i1>,
50+
iXLen);
51+
52+
define <vscale x 4 x i1> @intrinsic_vmandnot_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
53+
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv4i1:
54+
; CHECK: # %bb.0: # %entry
55+
; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1
56+
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
57+
; CHECK-NEXT: ret
58+
entry:
59+
%a = call <vscale x 4 x i1> @llvm.riscv.th.vmandnot.nxv4i1(
60+
<vscale x 4 x i1> %0,
61+
<vscale x 4 x i1> %1,
62+
iXLen %2)
63+
64+
ret <vscale x 4 x i1> %a
65+
}
66+
767
declare <vscale x 8 x i1> @llvm.riscv.th.vmandnot.nxv8i1(
868
<vscale x 8 x i1>,
969
<vscale x 8 x i1>,
1070
iXLen);
1171

12-
define <vscale x 8 x i1> @intrinsic_vmandn_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
13-
; CHECK-LABEL: intrinsic_vmandn_mm_nxv8i1:
72+
define <vscale x 8 x i1> @intrinsic_vmandnot_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
73+
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv8i1:
1474
; CHECK: # %bb.0: # %entry
1575
; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1
1676
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
@@ -29,8 +89,8 @@ declare <vscale x 16 x i1> @llvm.riscv.th.vmandnot.nxv16i1(
2989
<vscale x 16 x i1>,
3090
iXLen);
3191

32-
define <vscale x 16 x i1> @intrinsic_vmandn_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
33-
; CHECK-LABEL: intrinsic_vmandn_mm_nxv16i1:
92+
define <vscale x 16 x i1> @intrinsic_vmandnot_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
93+
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv16i1:
3494
; CHECK: # %bb.0: # %entry
3595
; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1
3696
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
@@ -49,8 +109,8 @@ declare <vscale x 32 x i1> @llvm.riscv.th.vmandnot.nxv32i1(
49109
<vscale x 32 x i1>,
50110
iXLen);
51111

52-
define <vscale x 32 x i1> @intrinsic_vmandn_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
53-
; CHECK-LABEL: intrinsic_vmandn_mm_nxv32i1:
112+
define <vscale x 32 x i1> @intrinsic_vmandnot_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
113+
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv32i1:
54114
; CHECK: # %bb.0: # %entry
55115
; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1
56116
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
@@ -69,8 +129,8 @@ declare <vscale x 64 x i1> @llvm.riscv.th.vmandnot.nxv64i1(
69129
<vscale x 64 x i1>,
70130
iXLen);
71131

72-
define <vscale x 64 x i1> @intrinsic_vmandn_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
73-
; CHECK-LABEL: intrinsic_vmandn_mm_nxv64i1:
132+
define <vscale x 64 x i1> @intrinsic_vmandnot_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
133+
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv64i1:
74134
; CHECK: # %bb.0: # %entry
75135
; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1
76136
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8

‎llvm/test/CodeGen/RISCV/rvv0p71/vmclr.ll

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,54 @@
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
55
; RUN: -verify-machineinstrs | FileCheck %s
66

7+
declare <vscale x 1 x i1> @llvm.riscv.th.vmclr.nxv1i1(
8+
iXLen);
9+
10+
define <vscale x 1 x i1> @intrinsic_vmclr_m_pseudo_nxv1i1(iXLen %0) nounwind {
11+
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv1i1:
12+
; CHECK: # %bb.0: # %entry
13+
; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1
14+
; CHECK-NEXT: th.vmclr.m v0
15+
; CHECK-NEXT: ret
16+
entry:
17+
%a = call <vscale x 1 x i1> @llvm.riscv.th.vmclr.nxv1i1(
18+
iXLen %0)
19+
20+
ret <vscale x 1 x i1> %a
21+
}
22+
23+
declare <vscale x 2 x i1> @llvm.riscv.th.vmclr.nxv2i1(
24+
iXLen);
25+
26+
define <vscale x 2 x i1> @intrinsic_vmclr_m_pseudo_nxv2i1(iXLen %0) nounwind {
27+
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv2i1:
28+
; CHECK: # %bb.0: # %entry
29+
; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1
30+
; CHECK-NEXT: th.vmclr.m v0
31+
; CHECK-NEXT: ret
32+
entry:
33+
%a = call <vscale x 2 x i1> @llvm.riscv.th.vmclr.nxv2i1(
34+
iXLen %0)
35+
36+
ret <vscale x 2 x i1> %a
37+
}
38+
39+
declare <vscale x 4 x i1> @llvm.riscv.th.vmclr.nxv4i1(
40+
iXLen);
41+
42+
define <vscale x 4 x i1> @intrinsic_vmclr_m_pseudo_nxv4i1(iXLen %0) nounwind {
43+
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv4i1:
44+
; CHECK: # %bb.0: # %entry
45+
; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1
46+
; CHECK-NEXT: th.vmclr.m v0
47+
; CHECK-NEXT: ret
48+
entry:
49+
%a = call <vscale x 4 x i1> @llvm.riscv.th.vmclr.nxv4i1(
50+
iXLen %0)
51+
52+
ret <vscale x 4 x i1> %a
53+
}
54+
755
declare <vscale x 8 x i1> @llvm.riscv.th.vmclr.nxv8i1(
856
iXLen);
957

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