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| 1 | +From 23712ff626db16793d428dddcb530f9e5faaa073 Mon Sep 17 00:00:00 2001 |
| 2 | +From: Adrian Lundell < [email protected]> |
| 3 | +Date: Thu, 3 Apr 2025 14:25:52 +0200 |
| 4 | +Subject: [PATCH] Move input_data_sec to NOLOAD area |
| 5 | + |
| 6 | +--- |
| 7 | + targets/corstone-300/platform.ld | 10 ++++++++-- |
| 8 | + targets/corstone-320/platform.ld | 8 ++++++-- |
| 9 | + 2 files changed, 14 insertions(+), 4 deletions(-) |
| 10 | + |
| 11 | +diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld |
| 12 | +index 1733509..3ccce64 100644 |
| 13 | +--- a/targets/corstone-300/platform.ld |
| 14 | ++++ b/targets/corstone-300/platform.ld |
| 15 | +@@ -272,13 +272,12 @@ SECTIONS |
| 16 | + *(.bss.tensor_arena) |
| 17 | + #endif |
| 18 | + |
| 19 | +- . = ALIGN(4); |
| 20 | +- *(input_data_sec) |
| 21 | + . = ALIGN(16); |
| 22 | + #if (ETHOSU_MODEL == 1) |
| 23 | + *(network_model_sec) |
| 24 | + #endif |
| 25 | + * (expected_output_data_sec) |
| 26 | ++ . = ALIGN(16); |
| 27 | + * (sec_command_stream, sec_weight_data, sec_input_data) |
| 28 | + *(.got*) |
| 29 | + *(.rodata*) |
| 30 | +@@ -287,6 +286,13 @@ SECTIONS |
| 31 | + . = ALIGN(4); |
| 32 | + } > DDR :rom_dram |
| 33 | + |
| 34 | ++ .ddr_noload (NOLOAD) : |
| 35 | ++ { |
| 36 | ++ . = ALIGN(16); |
| 37 | ++ *(input_data_sec) |
| 38 | ++ . = ALIGN(16); |
| 39 | ++ } > DDR :null |
| 40 | ++ |
| 41 | + __eddr_data = ALIGN (4) ; |
| 42 | + .sram.data : { |
| 43 | + __sram_data_start__ = .; |
| 44 | +diff --git a/targets/corstone-320/platform.ld b/targets/corstone-320/platform.ld |
| 45 | +index c8261c0..9b7e071 100644 |
| 46 | +--- a/targets/corstone-320/platform.ld |
| 47 | ++++ b/targets/corstone-320/platform.ld |
| 48 | +@@ -268,8 +268,6 @@ SECTIONS |
| 49 | + *(network_model_sec) |
| 50 | + #endif |
| 51 | + |
| 52 | +- . = ALIGN(4); |
| 53 | +- *(input_data_sec) |
| 54 | + *(expected_output_data_sec) |
| 55 | + *(output_data_sec) |
| 56 | + |
| 57 | +@@ -279,6 +277,12 @@ SECTIONS |
| 58 | + __etext = .; |
| 59 | + } > DDR :rom_dram |
| 60 | + |
| 61 | ++ .ddr_noload (NOLOAD) : |
| 62 | ++ { |
| 63 | ++ . = ALIGN(16); |
| 64 | ++ *(input_data_sec) |
| 65 | ++ } > DDR :null |
| 66 | ++ |
| 67 | + .bss : |
| 68 | + { |
| 69 | + . = ALIGN(4); |
| 70 | +-- |
| 71 | +2.43.0 |
| 72 | + |
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