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Support riscv64 architecture for Perf JIT
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Python/perf_jit_trampoline.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -371,6 +371,9 @@ enum {
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#elif defined(__aarch64__) && defined(__AARCH64EL__) && !defined(__ILP32__)
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DWRF_REG_SP = 31,
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DWRF_REG_RA = 30,
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#elif defined(__riscv)
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DWRF_REG_RA = 1,
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DWRF_REG_SP = 2,
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#else
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# error "Unsupported target architecture"
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#endif
@@ -477,7 +480,7 @@ elf_init_ehframe(ELFObjectContext* ctx)
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DWRF_U8(DWRF_CFA_advance_loc | 6);
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DWRF_U8(DWRF_CFA_def_cfa_offset); DWRF_UV(8);
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/* Extra registers saved for JIT-compiled code. */
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#elif defined(__aarch64__) && defined(__AARCH64EL__) && !defined(__ILP32__)
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#elif (defined(__aarch64__) && defined(__AARCH64EL__) && !defined(__ILP32__)) || defined(__riscv)
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DWRF_U8(DWRF_CFA_advance_loc | 1);
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DWRF_U8(DWRF_CFA_def_cfa_offset); DWRF_UV(16);
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DWRF_U8(DWRF_CFA_offset | 29); DWRF_UV(2);

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