Use assembly sequences to enable caches.

See rust-embedded#232, which this partially fixes -- there's still the question of
taking an interrupt in the midst of these sequences.

Author: cbiffle

asm-v7.s

@@ -39,3 +39,33 @@ __faultmask:
   bx lr
   .cfi_endproc
   .size __faultmask, . - __faultmask
+
+  .section .text.__enable_icache
+  .global __enable_icache
+  .thumb_func
+  .cfi_startproc
+__enable_icache:
+  ldr r0, =0xE000ED14       @ CCR
+  ldr r1, [r0]              @ read CCR
+  orr.w r1, r1, #(1 << 17)  @ Set bit 17, IC
+  str r1, [r0]              @ write it back
+  dsb                       @ ensure store completes
+  isb                       @ synchronize pipeline
+  bx lr
+  .cfi_endproc
+  .size __enable_icache, . - __enable_icache
+
+  .section .text.__enable_dcache
+  .global __enable_dcache
+  .thumb_func
+  .cfi_startproc
+__enable_dcache:
+  ldr r0, =0xE000ED14       @ CCR
+  ldr r1, [r0]              @ read CCR
+  orr.w r1, r1, #(1 << 16)  @ Set bit 16, DC
+  str r1, [r0]              @ write it back
+  dsb                       @ ensure store completes
+  isb                       @ synchronize pipeline
+  bx lr
+  .cfi_endproc
+  .size __enable_dcache, . - __enable_dcache

src/peripheral/scb.rs

@@ -331,11 +331,45 @@ impl SCB {
         cbp.iciallu();
 
         // Enable I-cache
-        // NOTE(unsafe): We have synchronised access by &mut self
-        unsafe { self.ccr.modify(|r| r | SCB_CCR_IC_MASK) };
+        match () {
+            #[cfg(not(feature = "inline-asm"))]
+            () => {
+                extern "C" {
+                    // see asm-v7m.s
+                    fn __enable_icache();
+                }
+
+                // NOTE(unsafe): Having &mut self means no ISR, for example, is
+                // going to try to alter this register at the same time. That
+                // being said, this is still unsafe if not executed in a
+                // critical section (TODO).
+                unsafe { __enable_icache(); }
+            }
+            #[cfg(feature = "inline-asm")]
+            () => {
+                // NOTE(unsafe): Having &mut self means no ISR, for example, is
+                // going to try to alter this register at the same time. That
+                // being said, this is still unsafe if not executed in a
+                // critical section (TODO).
+                unsafe {
+                    let _unused_ccr_val: u32;
+                    llvm_asm!("
+                        ldr $0, [$1]
+                        orr.w $0, $0, $2
+                        str $0, [$1]
+                        dsb
+                        isb
+                        "
+                        : "=&r"(_unused_ccr_val)
+                        : "r"(&self.ccr),
+                          "c"(SCB_CCR_IC_MASK)
+                        : "memory"
+                        : "volatile"
+                    );
+                }
+            }
 
-        crate::asm::dsb();
-        crate::asm::isb();
+        }
     }
 
     /// Disables I-cache if currently enabled.
@@ -401,10 +435,44 @@ impl SCB {
 
         // Now turn on the D-cache
         // NOTE(unsafe): We have synchronised access by &mut self
-        unsafe { self.ccr.modify(|r| r | SCB_CCR_DC_MASK) };
-
-        crate::asm::dsb();
-        crate::asm::isb();
+        match () {
+            #[cfg(not(feature = "inline-asm"))]
+            () => {
+                extern "C" {
+                    // see asm-v7m.s
+                    fn __enable_dcache();
+                }
+
+                // NOTE(unsafe): Having &mut self means no ISR, for example, is
+                // going to try to alter this register at the same time. That
+                // being said, this is still unsafe if not executed in a
+                // critical section (TODO).
+                unsafe { __enable_dcache(); }
+            }
+            #[cfg(feature = "inline-asm")]
+            () => {
+                // NOTE(unsafe): Having &mut self means no ISR, for example, is
+                // going to try to alter this register at the same time. That
+                // being said, this is still unsafe if not executed in a
+                // critical section (TODO).
+                unsafe {
+                    let _unused_ccr_val: u32;
+                    llvm_asm!("
+                        ldr $0, [$1]
+                        orr.w $0, $0, $2
+                        str $0, [$1]
+                        dsb
+                        isb
+                        "
+                        : "=&r"(_unused_ccr_val)
+                        : "r"(&self.ccr),
+                          "c"(SCB_CCR_DC_MASK)
+                        : "memory"
+                        : "volatile"
+                    );
+                }
+            }
+        }
     }
 
     /// Disables D-cache if currently enabled.