Use assembly sequences to enable caches.

See rust-embedded#232, which this partially fixes -- there's still the question of
taking an interrupt in the midst of these sequences.

Author: cbiffle

asm-v7.s

@@ -1,3 +1,4 @@
+  .syntax unified
   .cfi_sections .debug_frame
 
   .section .text.__basepri_max
@@ -39,3 +40,39 @@ __faultmask:
   bx lr
   .cfi_endproc
   .size __faultmask, . - __faultmask
+
+  .section .text.__enable_icache
+  .global __enable_icache
+  .thumb_func
+  .cfi_startproc
+__enable_icache:
+  ldr r0, =0xE000ED14       @ CCR
+  mrs r2, PRIMASK           @ save critical nesting info
+  cpsid i                   @ mask interrupts
+  ldr r1, [r0]              @ read CCR
+  orr.w r1, r1, #(1 << 17)  @ Set bit 17, IC
+  str r1, [r0]              @ write it back
+  dsb                       @ ensure store completes
+  isb                       @ synchronize pipeline
+  msr PRIMASK, r2           @ unnest critical section
+  bx lr
+  .cfi_endproc
+  .size __enable_icache, . - __enable_icache
+
+  .section .text.__enable_dcache
+  .global __enable_dcache
+  .thumb_func
+  .cfi_startproc
+__enable_dcache:
+  ldr r0, =0xE000ED14       @ CCR
+  mrs r2, PRIMASK           @ save critical nesting info
+  cpsid i                   @ mask interrupts
+  ldr r1, [r0]              @ read CCR
+  orr.w r1, r1, #(1 << 16)  @ Set bit 16, DC
+  str r1, [r0]              @ write it back
+  dsb                       @ ensure store completes
+  isb                       @ synchronize pipeline
+  msr PRIMASK, r2           @ unnest critical section
+  bx lr
+  .cfi_endproc
+  .size __enable_dcache, . - __enable_dcache

bin/thumbv6m-none-eabi.a

@@ -331,11 +331,17 @@ impl SCB {
         cbp.iciallu();
 
         // Enable I-cache
-        // NOTE(unsafe): We have synchronised access by &mut self
-        unsafe { self.ccr.modify(|r| r | SCB_CCR_IC_MASK) };
+        extern "C" {
+            // see asm-v7m.s
+            fn __enable_icache();
+        }
 
-        crate::asm::dsb();
-        crate::asm::isb();
+        // NOTE(unsafe): Having &mut self means no ISR, for example, is going to
+        // try to alter this register at the same time.
+        unsafe { __enable_icache(); }
+
+        // The asm routine covers both the critical section and barriers we
+        // need.
     }
 
     /// Disables I-cache if currently enabled.
@@ -400,11 +406,17 @@ impl SCB {
         unsafe { self.invalidate_dcache(cpuid) };
 
         // Now turn on the D-cache
-        // NOTE(unsafe): We have synchronised access by &mut self
-        unsafe { self.ccr.modify(|r| r | SCB_CCR_DC_MASK) };
+        extern "C" {
+            // see asm-v7m.s
+            fn __enable_dcache();
+        }
 
-        crate::asm::dsb();
-        crate::asm::isb();
+        // NOTE(unsafe): Having &mut self means no ISR, for example, is going to
+        // try to alter this register at the same time.
+        unsafe { __enable_dcache(); }
+
+        // The asm routine covers both the critical section and barriers we
+        // need.
     }
 
     /// Disables D-cache if currently enabled.