From 385abe8039e3c3a8dcba95a63053b9fa79bc8354 Mon Sep 17 00:00:00 2001 From: Joshua Hursey Date: Tue, 6 Jun 2017 16:41:11 -0500 Subject: [PATCH] atomics/powerpc: Fix WMB instruction * `lwsync` is a write memory barrier. - `eieio` is really not meant for this type of operation. * `lwsync` can also be used for the read memory barrier according to my reading of the of the Power 8 ISA docs (v2.07) - https://www-01.ibm.com/marketing/iwm/iwm/web/reg/download.do?source=swg-opower&S_PKG=dl&lang=en_US&cp=UTF-8 * References https://github.com/pmix/pmix/pull/391 Signed-off-by: Joshua Hursey (cherry picked from commit 4796193cdb324588b7f0e21825c023a1654c6f83) Signed-off-by: Joshua Hursey --- opal/include/opal/sys/powerpc/atomic.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/opal/include/opal/sys/powerpc/atomic.h b/opal/include/opal/sys/powerpc/atomic.h index 019b44edb49..05c155eddbf 100644 --- a/opal/include/opal/sys/powerpc/atomic.h +++ b/opal/include/opal/sys/powerpc/atomic.h @@ -10,7 +10,7 @@ * University of Stuttgart. All rights reserved. * Copyright (c) 2004-2005 The Regents of the University of California. * All rights reserved. - * Copyright (c) 2010 IBM Corporation. All rights reserved. + * Copyright (c) 2010-2017 IBM Corporation. All rights reserved. * Copyright (c) 2015-2016 Los Alamos National Security, LLC. All rights * reserved. * $COPYRIGHT$ @@ -29,10 +29,8 @@ #define MB() __asm__ __volatile__ ("sync" : : : "memory") #define RMB() __asm__ __volatile__ ("lwsync" : : : "memory") -#define WMB() __asm__ __volatile__ ("eieio" : : : "memory") +#define WMB() __asm__ __volatile__ ("lwsync" : : : "memory") #define ISYNC() __asm__ __volatile__ ("isync" : : : "memory") -#define SMP_SYNC "sync \n\t" -#define SMP_ISYNC "\n\tisync" /**********************************************************************