From 21d8aef51529556ec0a547cc1caf7fe5b2321db0 Mon Sep 17 00:00:00 2001 From: Aaron Luft Date: Tue, 4 Oct 2022 18:36:31 -0700 Subject: [PATCH] adding language systemverilog #490 --- languages.yaml | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/languages.yaml b/languages.yaml index efa2d1151..35717b30e 100644 --- a/languages.yaml +++ b/languages.yaml @@ -2195,6 +2195,34 @@ Swift: - '#FC3224' - '#FD2822' chip: '#F05138' +SystemVerilog: + type: programming + ascii: | + {0} _.._ _.._ _.._ _.._ + {0} _.._ _.._ _.._ _.._ + {0} ............................... + {0} . ---- . + {0} . -------------- . + {0} . ---- --------- . + {0} . --- ----- . + {0} . - ##### # # ----- . + {0} . # # # # . + {0} . # # # . + {0} . ##### # # . + {0} . # # # . + {0} . # # # # . + {0} . ----- ##### # - . + {0} . ----- --- . + {0} . --------- ---- . + {0} . -------------- . + {0} . ---- . + {0} ............................... + {0} _.._ _.._ _.._ _.._ + {0} _.._ _.._ _.._ _.._ + colors: + ansi: + - white + chip: '#DAE1C2' Tcl: type: programming ascii: |