diff --git a/2-input.PNG b/2-input.PNG
new file mode 100644
index 0000000..ed2618b
Binary files /dev/null and b/2-input.PNG differ
diff --git a/Block_Based_Circuit_Design/myth_rv64I.xml b/Block_Based_Circuit_Design/myth_rv64I.xml
new file mode 100644
index 0000000..073b97f
--- /dev/null
+++ b/Block_Based_Circuit_Design/myth_rv64I.xml
@@ -0,0 +1,6225 @@
+
+
+ cpu
+ passed
+ reset
+ value
+ failed
+ start
+ instr
+ imem_rd_data
+ pc
+ is_i_instr
+ rf_rd_en1
+ rs1_valid
+ valid_taken_br
+ br_tgt_pc
+ imem_rd_en
+ is_r_instr
+ rf_rd_en2
+ rs2_valid
+ taken_br
+ is_beq
+ valid_jump
+ jalr_tgt_pc
+ imem_rd_addr
+ is_s_instr
+ rf_rd_index1
+ rs1
+ src1_value
+ src2_value
+ is_bne
+ valid
+ dmem_wr_en
+ valid_load
+ is_b_instr
+ rf_rd_index2
+ rs2
+ is_blt
+ dmem_wr_data
+ ld_data
+ dmem_rd_data
+ is_j_instr
+ result
+ is_bge
+ dmem_rd_en
+ is_load
+ is_u_instr
+ rf_wr_en
+ rf_rd_data1
+ is_bltu
+ sltu_rslt
+ dmem_addr
+ imm
+ rf_wr_index
+ rf_rd_data2
+ is_bgeu
+ sltiu_rslt
+ funct7_valid
+ is_andi
+ is_ori
+ is_jump
+ funct7
+ is_xori
+ is_jal
+ is_jalr
+ is_addi
+ is_slli
+ rd
+ is_srli
+ rd_valid
+ rf_wr_data
+ funct3_valid
+ is_and
+ is_or
+ funct3
+ is_xor
+ is_add
+ opcode
+ is_sub
+ dec_bits
+ is_sll
+ is_srl
+ is_sltu
+ is_sltiu
+ is_lui
+ is_auipc
+ is_srai
+ is_slt
+ is_slti
+ is_sra
+ is_sb
+ is_sh
+ is_sw
+
+
+
+
+
+
+ https://raw.githubusercontent.com/stevehoover/RISC-V_MYTH_Workshop/c1719d5b338896577b79ee76c2f443ca2a76e14f/tlv_lib/risc-v_shell_lib.tlv
+
+
+
+
+
+
+
+
+
+
+
+ // /====================\ // | Sum 1 to 9 Program | // \====================/ // // Program for MYTH Workshop to test RV32I // Add 1,2,3,...,9 (in that order). // // Regs: // r10 (a0): In: 0, Out: final sum // r12 (a2): 10 // r13 (a3): 1..10 // r14 (a4): Sum // r15 (a5): stored/loaded Sum // // External to function: m4_asm(ADD, r10, r0, r0) // Initialize r10 (a0) to 0. // Function: m4_asm(ADD, r14, r10, r0) // Initialize sum register a4 with 0x0 m4_asm(ADDI, r12, r10, 1010) // Store count of 10 in register a2. m4_asm(ADD, r13, r10, r0) // Initialize intermediate sum register a3 with 0 // Loop: m4_asm(ADD, r14, r13, r14) // Incremental addition m4_asm(ADDI, r13, r13, 1) // Increment intermediate register by 1 m4_asm(BLT, r13, r12, 1111111111000) // If a3 is less than a2, branch to label named <loop> m4_asm(ADD, r10, r14, r0) // Store final result to register a0 so that it can be read by main program // Store/Load m4_asm(SW, r0, r10, 100) // Store final result in data memory at address 'b100 (4) m4_asm(LW, r15, r0, 100) // Load final result into a5 // Optional: m4_asm(JAL, r7, 00000000000000000000) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
+
+
+ define_hier
+ ['M4_IMEM'], M4_NUM_INSTRS
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+
+ cpu
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+ 0
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+ =
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+
+
+ reset
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+ $
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+
+ start
+
+
+ $
+
+
+
+
+
+
+ &
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+
+
+ reset
+
+
+ !$
+
+
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+
+ reset
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+ 1
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+ $
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+ pc
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+ $
+
+
+
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+ [31:0]
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+ reset
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+ 1
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+ $
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+ 0
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+
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+ ?
+ :
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+
+
+ valid_taken_br
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+
+ 3
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+
+
+ $
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+ br_tgt_pc
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+ $
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+
+ ?
+ :
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+ valid_jump
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+ 3
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+ $
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+ jalr_tgt_pc
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+ ?
+ :
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+ valid_load
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+ $
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+
+ 4
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+ ;
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+ pc
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+ $
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+ 4
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+ imem_rd_en
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+ !$
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+ imem_rd_addr
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+ $
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+ [M4_IMEM_INDEX_CNT-1:0]
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+ [M4_IMEM_INDEX_CNT+1:2]
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+ 21
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+ [30:20]
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+ :
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+ [30:25]
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+ $
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+ [11:7]
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+ 20
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+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_110_1100011
+
+
+
+
+
+
+ =
+
+
+
+ is_bgeu
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_111_1100011
+
+
+
+
+
+
+ =
+
+
+
+ is_addi
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_000_0010011
+
+
+
+
+
+
+ =
+
+
+
+ is_add
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_000_0110011
+
+
+
+
+
+
+ =
+
+
+
+ is_lui
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_xxx_0110111
+
+
+
+
+
+
+ =
+
+
+
+ is_auipc
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_xxx_0010111
+
+
+
+
+
+
+ =
+
+
+
+ is_jal
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_xxx_1101111
+
+
+
+
+
+
+ =
+
+
+
+ is_jalr
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_000_1100111
+
+
+
+
+
+
+ =
+
+
+
+ is_load
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ opcode
+
+
+ $
+
+
+
+
+
+
+ 7'b0000011
+
+
+
+
+
+
+ =
+
+
+
+ is_sb
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_000_0100011
+
+
+
+
+
+
+ =
+
+
+
+ is_sh
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_001_0100011
+
+
+
+
+
+
+ =
+
+
+
+ is_sw
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_010_0100011
+
+
+
+
+
+
+ =
+
+
+
+ is_slti
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_010_0010011
+
+
+
+
+
+
+ =
+
+
+
+ is_sltiu
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_011_0010011
+
+
+
+
+
+
+ =
+
+
+
+ is_xori
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_100_0010011
+
+
+
+
+
+
+ =
+
+
+
+ is_ori
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_110_0010011
+
+
+
+
+
+
+ =
+
+
+
+ is_andi
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'bx_111_0010011
+
+
+
+
+
+
+ =
+
+
+
+ is_slli
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b0_001_0010011
+
+
+
+
+
+
+ =
+
+
+
+ is_srli
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b0_101_0010011
+
+
+
+
+
+
+ =
+
+
+
+ is_srai
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b1_101_0010011
+
+
+
+
+
+
+ =
+
+
+
+ is_sub
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b1_000_0110011
+
+
+
+
+
+
+ =
+
+
+
+ is_sll
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b0_001_0110011
+
+
+
+
+
+
+ =
+
+
+
+ is_slt
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b0_010_0110011
+
+
+
+
+
+
+ =
+
+
+
+ is_sltu
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b0_011_0110011
+
+
+
+
+
+
+ =
+
+
+
+ is_xor
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b0_100_0110011
+
+
+
+
+
+
+ =
+
+
+
+ is_srl
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b0_101_0110011
+
+
+
+
+
+
+ =
+
+
+
+ is_sra
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b1_101_0110011
+
+
+
+
+
+
+ =
+
+
+
+ is_or
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b0_110_0110011
+
+
+
+
+
+
+ =
+
+
+
+ is_and
+
+
+ $
+
+
+
+
+
+
+ ==?
+
+
+
+ dec_bits
+
+
+ $
+
+
+
+
+
+
+ 11'b0_111_0110011
+
+
+
+
+
+
+ `BOGUS_USE($is_lui $is_auipc $is_jal $is_jalr) `BOGUS_USE($is_load $is_sb $is_sh $is_sw) `BOGUS_USE($is_slti $is_sltiu $is_xori $is_ori $is_andi $is_slli $is_srli $is_srai) `BOGUS_USE($is_sub $is_sll $is_slt $is_sltu $is_xor $is_srl $is_sra $is_or $is_and) `BOGUS_USE($is_beq $is_bne $is_blt $is_bge $is_bltu $is_bgeu $is_addi $is_add)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2
+
+
+ =
+
+
+
+ rf_rd_en1
+
+
+ $
+
+
+
+
+
+
+
+ rs1_valid
+
+
+ $
+
+
+
+
+
+
+ =
+
+
+
+ rf_rd_en2
+
+
+ $
+
+
+
+
+
+
+
+ rs2_valid
+
+
+ $
+
+
+
+
+
+
+ =
+
+
+
+ rf_rd_index1
+
+
+ $
+
+
+
+
+ [4:0]
+
+
+
+
+
+
+
+ rs1
+
+
+ $
+
+
+
+
+
+
+ =
+
+
+
+ rf_rd_index2
+
+
+ $
+
+
+
+
+ [4:0]
+
+
+
+
+
+
+
+ rs2
+
+
+ $
+
+
+
+
+
+
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+ [31:0]
+
+
+
+
+
+
+ &&
+
+
+ ==
+
+
+
+ rf_wr_index
+
+
+
+
+
+ 1
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+
+ rf_rd_index1
+
+
+ $
+
+
+
+
+
+
+
+
+
+ rf_wr_en
+
+
+
+
+
+ 1
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+
+ result
+
+
+
+
+
+ 1
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+ ;
+
+
+
+
+ rf_rd_data1
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+ [31:0]
+
+
+
+
+
+
+ &&
+
+
+ ==
+
+
+
+ rf_wr_index
+
+
+
+
+
+ 1
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+
+ rf_rd_index2
+
+
+ $
+
+
+
+
+
+
+
+
+
+ rf_wr_en
+
+
+
+
+
+ 1
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+
+ result
+
+
+
+
+
+ 1
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+ ;
+
+
+
+
+ rf_rd_data2
+
+
+ $
+
+
+
+
+
+
+
+
+ =
+
+
+
+ br_tgt_pc
+
+
+ $
+
+
+
+
+ [31:0]
+
+
+
+
+
+
+ +
+
+
+
+ pc
+
+
+ $
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+
+
+
+
+ =
+
+
+
+ jalr_tgt_pc
+
+
+ $
+
+
+
+
+ [31:0]
+
+
+
+
+
+
+ +
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3
+
+
+
+
+
+ taken_br
+
+
+ $
+
+
+
+
+
+
+
+ is_beq
+
+
+ $
+
+
+
+
+
+
+ ==
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_bne
+
+
+ $
+
+
+
+
+
+
+ !=
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_blt
+
+
+ $
+
+
+
+
+
+
+ ^
+
+
+ <
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ !=
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_bge
+
+
+ $
+
+
+
+
+
+
+ ^
+
+
+ >=
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ !=
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_bltu
+
+
+ $
+
+
+
+
+
+
+ <
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_bgeu
+
+
+ $
+
+
+
+
+
+
+ >=
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ ;
+
+
+
+ 1'b0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ =
+
+
+
+ valid
+
+
+ $
+
+
+
+
+
+
+ !
+
+
+
+
+ ||
+
+
+
+ valid_taken_br
+
+
+
+
+
+ 1
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+ ||
+
+
+
+ valid_taken_br
+
+
+
+
+
+ 2
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+ ||
+
+
+
+ valid_load
+
+
+
+
+
+ 1
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+
+ valid_load
+
+
+
+
+
+ 2
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ =
+
+
+
+ valid_taken_br
+
+
+ $
+
+
+
+
+
+
+ &&
+
+
+
+ valid
+
+
+ $
+
+
+
+
+
+
+
+ taken_br
+
+
+ $
+
+
+
+
+
+
+
+
+ =
+
+
+
+ valid_load
+
+
+ $
+
+
+
+
+
+
+ &&
+
+
+
+ valid
+
+
+ $
+
+
+
+
+
+
+
+ is_load
+
+
+ $
+
+
+
+
+
+
+
+
+ =
+
+
+
+ sltu_rslt
+
+
+ $
+
+
+
+
+ [31:0]
+
+
+
+
+
+
+ <
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ =
+
+
+
+ sltiu_rslt
+
+
+ $
+
+
+
+
+ [31:0]
+
+
+
+
+
+
+ <
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+
+ result
+
+
+ $
+
+
+
+
+ [31:0]
+
+
+
+
+
+
+
+ is_andi
+
+
+ $
+
+
+
+
+
+
+ &&
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_ori
+
+
+ $
+
+
+
+
+
+
+ ||
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_xori
+
+
+ $
+
+
+
+
+
+
+ ^
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+ ||
+
+
+
+ is_addi
+
+
+ $
+
+
+
+
+
+
+ ||
+
+
+
+ is_load
+
+
+ $
+
+
+
+
+
+
+
+ is_s_instr
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+ +
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_slli
+
+
+ $
+
+
+
+
+
+
+ <<
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+ [5:0]
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_srli
+
+
+ $
+
+
+
+
+
+
+ >>
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+ [5:0]
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_and
+
+
+ $
+
+
+
+
+
+
+ &
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_or
+
+
+ $
+
+
+
+
+
+
+ |
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_xor
+
+
+ $
+
+
+
+
+
+
+ ^
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_add
+
+
+ $
+
+
+
+
+
+
+ +
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_sub
+
+
+ $
+
+
+
+
+
+
+ -
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_sll
+
+
+ $
+
+
+
+
+
+
+ <<
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+ [4:0]
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_srl
+
+
+ $
+
+
+
+
+
+
+ >>
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+ [4:0]
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_sltu
+
+
+ $
+
+
+
+
+
+
+
+ sltu_rslt
+
+
+ $
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_sltiu
+
+
+ $
+
+
+
+
+
+
+
+ sltiu_rslt
+
+
+ $
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_lui
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+ [31:12]
+
+
+
+
+
+
+ 12'b0
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_auipc
+
+
+ $
+
+
+
+
+
+
+ +
+
+
+
+ pc
+
+
+ $
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_jal
+
+
+ $
+
+
+
+
+
+
+ +
+
+
+
+ pc
+
+
+ $
+
+
+
+
+
+
+ 32'd4
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_jalr
+
+
+ $
+
+
+
+
+
+
+ +
+
+
+
+ pc
+
+
+ $
+
+
+
+
+
+
+ 32'd4
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_srai
+
+
+ $
+
+
+
+
+
+
+ >>
+
+
+
+
+
+
+
+
+ 32
+
+
+
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+
+
+
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+ [4:0]
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_slt
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+ ==
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+
+
+ sltu_rslt
+
+
+ $
+
+
+
+
+
+
+
+
+
+ 31'b0
+
+
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_slti
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+ ==
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+ imm
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+
+
+ sltiu_rslt
+
+
+ $
+
+
+
+
+
+
+
+
+
+ 31'b0
+
+
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+
+
+
+
+
+ ?
+ :
+
+
+
+ is_sra
+
+
+ $
+
+
+
+
+
+
+ >>
+
+
+
+
+
+
+
+
+ 32
+
+
+
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+ [31]
+
+
+
+
+
+
+
+
+
+
+
+
+
+ src1_value
+
+
+ $
+
+
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+ [4:0]
+
+
+
+
+
+
+
+
+ ;
+
+
+
+ 32'bx
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ =
+
+
+
+ is_jump
+
+
+ $
+
+
+
+
+
+
+ ||
+
+
+
+ is_jal
+
+
+ $
+
+
+
+
+
+
+
+ is_jalr
+
+
+ $
+
+
+
+
+
+
+
+
+ =
+
+
+
+ valid_jump
+
+
+ $
+
+
+
+
+
+
+ &&
+
+
+
+ is_jump
+
+
+ $
+
+
+
+
+
+
+
+ valid
+
+
+ $
+
+
+
+
+
+
+
+
+ =
+
+
+
+ rf_wr_en
+
+
+ $
+
+
+
+
+
+
+ ||
+
+
+ &&
+
+
+
+ rd_valid
+
+
+ $
+
+
+
+
+
+
+ &&
+
+
+
+ valid
+
+
+ $
+
+
+
+
+
+
+ !=
+
+
+
+ rd
+
+
+ $
+
+
+
+
+
+
+ 5'b0
+
+
+
+
+
+
+
+
+
+
+
+ valid_load
+
+
+
+
+
+ 2
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+
+
+
+ rf_wr_index
+
+
+ $
+
+
+
+
+ [4:0]
+
+
+
+
+
+
+
+ valid_load
+
+
+
+
+
+ 2
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+
+ rd
+
+
+
+
+
+ 2
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+ ;
+
+
+
+
+ rd
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+
+ rf_wr_data
+
+
+ $
+
+
+
+
+ [31:0]
+
+
+
+
+
+
+
+ valid_load
+
+
+
+
+
+ 2
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+
+ ld_data
+
+
+
+
+
+ 2
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+ ;
+
+
+
+
+ result
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4
+
+
+ =
+
+
+
+ dmem_wr_en
+
+
+ $
+
+
+
+
+
+
+ &&
+
+
+
+ is_s_instr
+
+
+ $
+
+
+
+
+
+
+
+ valid
+
+
+ $
+
+
+
+
+
+
+
+
+ =
+
+
+
+ dmem_wr_data
+
+
+ $
+
+
+
+
+ [31:0]
+
+
+
+
+
+
+
+ src2_value
+
+
+ $
+
+
+
+
+
+
+ =
+
+
+
+ dmem_rd_en
+
+
+ $
+
+
+
+
+
+
+
+ is_load
+
+
+ $
+
+
+
+
+
+
+ =
+
+
+
+ dmem_addr
+
+
+ $
+
+
+
+
+ [3:0]
+
+
+
+
+
+
+
+ result
+
+
+ $
+
+
+
+
+ [3:0]
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 5
+
+
+ =
+
+
+
+ ld_data
+
+
+ $
+
+
+
+
+ [31:0]
+
+
+
+
+
+
+
+ dmem_rd_data
+
+
+ $
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ =
+
+
+
+ passed
+
+
+ *
+
+
+
+
+
+
+ ==
+
+
+
+ value
+
+
+
+
+
+ |cpu/xreg[15]
+
+
+
+
+ 5
+
+
+
+
+ $
+
+
+
+
+
+
+
+
+ (1+2+3+4+5+6+7+8+9)
+
+
+
+
+
+
+ =
+
+
+
+ failed
+
+
+ *
+
+
+
+
+
+
+ 1'b0
+
+
+
+
+ cpu
+
+
+ imem(@1)
+
+
+ rf(@2, @3)
+
+
+ dmem(@4)
+
+
+
+
+
+
+
+
+ cpu_viz(@4)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Certificate/certificate.pdf b/Certificate/certificate.pdf
new file mode 100644
index 0000000..0f6a835
Binary files /dev/null and b/Certificate/certificate.pdf differ
diff --git a/Day2/README.md b/Day2/README.md
index 53a90bf..20a6d89 100644
--- a/Day2/README.md
+++ b/Day2/README.md
@@ -1 +1,33 @@
-Empty
+# Running the 1to9_custom.c and load.S on the riscv GNU toolchain
+
+* First, we ran the program using riscv64-unknown-elf-gcc command.
+* Then, debugged the Program using spike -d pk 1to9_custom.o to check for values of registers at specific addresses as asked
+* Finally we took a look into the assembly code to check the address locations of the load and theloop blocks.
+
+### 1) Program Run and Debug
+
+---
+
+### 2) Debug
+
+---
+
+### 3) Assembly code
+
+---
+
+
+# Running the 1to9_custom.c and load.S on the picorv32 riscv cpu core
+
+* Ran the program using the picorv32 core using ./rv32im.sh command in ~/labs
+* Peeked inside the rv32im.sh file using vim rv32im.sh to check the -mabi and -march values
+
+### 1) Program Run
+
+---
+
+
+### 2) Read rv32im.sh
+
+---
+
diff --git a/Day2/assembly.PNG b/Day2/assembly.PNG
new file mode 100644
index 0000000..8e94c74
Binary files /dev/null and b/Day2/assembly.PNG differ
diff --git a/Day2/debug.PNG b/Day2/debug.PNG
new file mode 100644
index 0000000..cc9307b
Binary files /dev/null and b/Day2/debug.PNG differ
diff --git a/Day2/prog_run.PNG b/Day2/prog_run.PNG
new file mode 100644
index 0000000..c042371
Binary files /dev/null and b/Day2/prog_run.PNG differ
diff --git a/Day2/prog_run_debug.PNG b/Day2/prog_run_debug.PNG
new file mode 100644
index 0000000..123152c
Binary files /dev/null and b/Day2/prog_run_debug.PNG differ
diff --git a/Day2/read_rv32im.PNG b/Day2/read_rv32im.PNG
new file mode 100644
index 0000000..f06f787
Binary files /dev/null and b/Day2/read_rv32im.PNG differ
diff --git a/Day3_5/calculator_solutions.tlv b/Day3_5/calculator_solutions.tlv
index 8bd6338..aaa9045 100644
--- a/Day3_5/calculator_solutions.tlv
+++ b/Day3_5/calculator_solutions.tlv
@@ -1,3 +1,66 @@
\m4_TLV_version 1d: tl-x.org
\SV
-//Calculator labs solutions here
+ // This code can be found in: https://github.com/stevehoover/RISC-V_MYTH_Workshop
+
+ m4_include_lib(['https://raw.githubusercontent.com/stevehoover/RISC-V_MYTH_Workshop/bd1f186fde018ff9e3fd80597b7397a1c862cf15/tlv_lib/calculator_shell_lib.tlv'])
+
+\SV
+ m4_makerchip_module // (Expanded in Nav-TLV pane.)
+
+\TLV
+ |calc
+ @0
+ $reset = *reset;
+ @1
+
+ $valid[31:0] = ($reset) ? 0
+ : (>>1$valid == 32'b0) ? 1
+ : 32'b0;
+ $valid_or_reset = $reset | $valid;
+ ?$valid_or_reset
+ @1
+ $val1[31:0] = >>2$out[31:0];
+ $val2[31:0] = $rand2[3:0];
+
+ $sum[31:0] = $val1[31:0] + $val2[31:0];
+ $diff[31:0] = $val1[31:0] - $val2[31:0];
+ $prod[31:0] = $val1[31:0] * $val2[31:0];
+ $quot[31:0] = $val1[31:0] / $val2[31:0];
+ @2
+ $mem[31:0] = ($op[2:0] == 3'b101)
+ ? >>2$mem :
+ $reset
+ ? 0 :
+ >>2$out[31:0];
+
+ $out[31:0] = ($op[2:0] == 3'b000)
+ ? $sum[31:0] :
+ ($op[2:0] == 3'b001)
+ ? $diff[31:0] :
+ ($op[2:0] == 3'b010)
+ ? $prod[31:0] :
+ ($op[2:0] == 3'b011)
+ ? $quot[31:0] :
+ ($op[2:0] == 3'b100)
+ ? >>2$mem[31:0]:
+ 32'b0;
+
+ // Macro instantiations for calculator visualization(disabled by default).
+ // Uncomment to enable visualisation, and also,
+ // NOTE: If visualization is enabled, $op must be defined to the proper width using the expression below.
+ // (Any signals other than $rand1, $rand2 that are not explicitly assigned will result in strange errors.)
+ // You can, however, safely use these specific random signals as described in the videos:
+ // o $rand1[3:0]
+ // o $rand2[3:0]
+ // o $op[x:0]
+
+ m4+cal_viz(@2) // Arg: Pipeline stage represented by viz, should be atleast equal to last stage of CALCULATOR logic.
+
+
+ // Assert these to end simulation (before Makerchip cycle limit).
+ *passed = *cyc_cnt > 40;
+ *failed = 1'b0;
+
+
+\SV
+ endmodule
diff --git a/Day3_5/risc-v_solutions.tlv b/Day3_5/risc-v_solutions.tlv
index 1b43c72..c5e51de 100644
--- a/Day3_5/risc-v_solutions.tlv
+++ b/Day3_5/risc-v_solutions.tlv
@@ -1,3 +1,240 @@
\m4_TLV_version 1d: tl-x.org
\SV
-//RISC-V labs solutions here
+ // This code can be found in: https://github.com/stevehoover/RISC-V_MYTH_Workshop
+
+ m4_include_lib(['https://raw.githubusercontent.com/stevehoover/RISC-V_MYTH_Workshop/c1719d5b338896577b79ee76c2f443ca2a76e14f/tlv_lib/risc-v_shell_lib.tlv'])
+
+\SV
+ m4_makerchip_module // (Expanded in Nav-TLV pane.)
+\TLV
+
+ // /====================\
+ // | Sum 1 to 9 Program |
+ // \====================/
+ //
+ // Program for MYTH Workshop to test RV32I
+ // Add 1,2,3,...,9 (in that order).
+ //
+ // Regs:
+ // r10 (a0): In: 0, Out: final sum
+ // r12 (a2): 10
+ // r13 (a3): 1..10
+ // r14 (a4): Sum
+ //
+ // External to function:
+ m4_asm(ADD, r10, r0, r0) // Initialize r10 (a0) to 0.
+ // Function:
+ m4_asm(ADD, r14, r10, r0) // Initialize sum register a4 with 0x0
+ m4_asm(ADDI, r12, r10, 1010) // Store count of 10 in register a2.
+ m4_asm(ADD, r13, r10, r0) // Initialize intermediate sum register a3 with 0
+ // Loop:
+ m4_asm(ADD, r14, r13, r14) // Incremental addition
+ m4_asm(ADDI, r13, r13, 1) // Increment intermediate register by 1
+ m4_asm(BLT, r13, r12, 1111111111000) // If a3 is less than a2, branch to label named
+ m4_asm(ADD, r10, r14, r0) // Store final result to register a0 so that it can be read by main program
+ m4_asm(SW, r0, r10, 100)
+ m4_asm(LW, r15, r0, 100)
+ // Optional:
+ // m4_asm(JAL, r7, 00000000000000000000) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
+ m4_define_hier(['M4_IMEM'], M4_NUM_INSTRS)
+
+ |cpu
+ @0
+ $reset = *reset;
+ $pc[31:0] = >>1$reset ? '0 :
+ >>3$valid_taken_br ? >>3$br_tgt_pc :
+ >>3$valid_load ? >>3$inc_pc :
+ >>3$valid_jump && >>3$is_jal ? >>3$br_tgt_pc :
+ >>3$valid_jump && >>3$is_jalr ? >>3$jalr_tgt_pc :
+ >>1$inc_pc ;
+ $imem_rd_en = !$reset;
+ $imem_rd_addr[M4_IMEM_INDEX_CNT-1:0] = $pc[M4_IMEM_INDEX_CNT+1:2];
+
+ $start = >>1$reset && !$reset;
+ @1
+ $inc_pc[31:0] = $pc[31:0] + 32'd4;
+ $instr[31:0] = $imem_rd_data[31:0];
+
+ $is_i_instr = $instr[6:2] ==? 5'b0000x ||
+ $instr[6:2] ==? 5'b001x0 ||
+ $instr[6:2] ==? 5'b11001 ;
+
+ $is_r_instr = $instr[6:2] ==? 5'b01011 ||
+ $instr[6:2] ==? 5'b011x0 ||
+ $instr[6:2] ==? 5'b10100 ;
+
+ $is_s_instr = $instr[6:2] ==? 5'b0100x;
+
+ $is_b_instr = $instr[6:2] ==? 5'b11000;
+
+ $is_j_instr = $instr[6:2] ==? 5'b11011;
+
+ $is_u_instr = $instr[6:2] ==? 5'b0x101;
+
+ $imm[31:0] = $is_i_instr ? { {21{$instr[31]}}, $instr[30:20] } :
+ $is_s_instr ? {{21{$instr[31]}},$instr[30:25],$instr[11:7] } :
+ $is_b_instr ? {{20{$instr[31]}},$instr[7], $instr[30:25],$instr[11:8],1'b0 } :
+ $is_u_instr ? {$instr[31:12], 12'b0 } :
+ $is_j_instr ? {{12{$instr[31]}},$instr[19:12], $instr[20],$instr[30:21],1'b0 } :
+ 32'b0;
+ $funct7_valid = $is_r_instr;
+ ?$funct7_valid
+ $funct7[6:0] = $instr[31:25];
+
+ $rs2_valid = $is_r_instr || $is_s_instr || $is_b_instr;
+ ?$rs2_valid
+ $rs2[4:0] = $instr[24:20];
+ $rs1_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
+ ?$rs1_valid
+ $rs1[4:0] = $instr[19:15];
+ $funct3_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
+ ?$funct3_valid
+ $funct3[2:0] = $instr[14:12];
+ $rd_valid = $is_r_instr || $is_i_instr || $is_u_instr || $is_j_instr;
+ ?$rd_valid
+ $rd[4:0] = $instr[11:7];
+ $opcode[6:0] = $instr[6:0];
+
+ $dec_bits[10:0] = {$funct7[5],$funct3,$opcode};
+ $is_beq = $dec_bits ==? 11'bx_000_1100011;
+ $is_bne = $dec_bits ==? 11'bx_001_1100011;
+ $is_blt = $dec_bits ==? 11'bx_100_1100011;
+ $is_bge = $dec_bits ==? 11'bx_101_1100011;
+ $is_bltu = $dec_bits ==? 11'bx_110_1100011;
+ $is_bgeu = $dec_bits ==? 11'bx_111_1100011;
+ $is_addi = $dec_bits ==? 11'bx_000_0010011;
+ $is_add = $dec_bits ==? 11'bx_000_0110011;
+ $is_lui = $dec_bits ==? 11'bx_xxx_0110111 ;
+ $is_auipc = $dec_bits ==? 11'bx_xxx_0010111 ;
+ $is_jal = $dec_bits ==? 11'bx_xxx_1101111 ;
+ $is_jalr = $dec_bits ==? 11'bx_000_1100111 ;
+ $is_load = $opcode == 7'b0000011;
+ $is_sb = $dec_bits ==? 11'bx_000_0100011 ;
+ $is_sh = $dec_bits ==? 11'bx_001_0100011 ;
+ $is_sw = $dec_bits ==? 11'bx_010_0100011 ;
+ $is_slti = $dec_bits ==? 11'bx_010_0010011 ;
+ $is_sltiu = $dec_bits ==? 11'bx_011_0010011 ;
+ $is_xori = $dec_bits ==? 11'bx_100_0010011 ;
+ $is_ori = $dec_bits ==? 11'bx_110_0010011 ;
+ $is_andi = $dec_bits ==? 11'bx_111_0010011 ;
+ $is_slli = $dec_bits ==? 11'b0_001_0010011 ;
+ $is_srli = $dec_bits ==? 11'b0_101_0010011 ;
+ $is_srai = $dec_bits ==? 11'b1_101_0010011 ;
+ $is_sub = $dec_bits ==? 11'b1_000_0110011 ;
+ $is_sll = $dec_bits ==? 11'b0_001_0110011 ;
+ $is_slt = $dec_bits ==? 11'b0_010_0110011 ;
+ $is_sltu = $dec_bits ==? 11'b0_011_0110011 ;
+ $is_xor = $dec_bits ==? 11'b0_100_0110011 ;
+ $is_srl = $dec_bits ==? 11'b0_101_0110011 ;
+ $is_sra = $dec_bits ==? 11'b1_101_0110011 ;
+ $is_or = $dec_bits ==? 11'b0_110_0110011 ;
+ $is_and = $dec_bits ==? 11'b0_111_0110011 ;
+
+ `BOGUS_USE($is_lui $is_auipc $is_jal $is_jalr)
+ `BOGUS_USE($is_load $is_sb $is_sh $is_sw)
+ `BOGUS_USE($is_slti $is_sltiu $is_xori $is_ori $is_andi $is_slli $is_srli $is_srai)
+ `BOGUS_USE($is_sub $is_sll $is_slt $is_sltu $is_xor $is_srl $is_sra $is_or $is_and)
+ `BOGUS_USE($is_beq $is_bne $is_blt $is_bge $is_bltu $is_bgeu $is_addi $is_add)
+
+ @2
+ $rf_rd_en1 = $rs1_valid;
+ $rf_rd_en2 = $rs2_valid;
+ $rf_rd_index1[4:0] = $rs1;
+ $rf_rd_index2[4:0] = $rs2;
+
+ $src1_value[31:0] =
+ (>>1$rf_wr_index == $rf_rd_index1) && >>1$rf_wr_en
+ ? >>1$result :
+ $rf_rd_data1 ;
+ $src2_value[31:0] =
+ (>>1$rf_wr_index == $rf_rd_index2) && >>1$rf_wr_en
+ ? >>1$result :
+ $rf_rd_data2 ;
+
+ $br_tgt_pc[31:0] = $pc + $imm;
+ $jalr_tgt_pc[31:0] = $src1_value + $imm;
+
+ @3
+ $taken_br = $is_beq ? ($src1_value == $src2_value) :
+ $is_bne ? ($src1_value != $src2_value) :
+ $is_blt ? ($src1_value < $src2_value) ^ ($src1_value[31] != $src2_value[31]) :
+ $is_bge ? ($src1_value >= $src2_value) ^ ($src1_value[31] != $src2_value[31]) :
+ $is_bltu ? ($src1_value < $src2_value) :
+ $is_bgeu ? ($src1_value >= $src2_value) :
+ 1'b0;
+
+ $valid = !(>>1$valid_taken_br || >>2$valid_taken_br ||
+ >>1$valid_load || >>2$valid_load);
+
+ $valid_taken_br = $valid && $taken_br;
+ $valid_load = $valid && $is_load;
+
+ $sltu_rslt[31:0] = $src1_value < $src2_value;
+ $sltiu_rslt[31:0] = $src1_value < $imm;
+
+ $result[31:0] = $is_andi ? $src1_value & $imm :
+ $is_ori ? $src1_value | $imm :
+ $is_xori ? $src1_value ^ $imm :
+ ($is_addi || $is_load || $is_s_instr) ? $src1_value + $imm :
+ $is_slli ? $src1_value << $imm[5:0] :
+ $is_srli ? $src1_value >> $imm[5:0] :
+ $is_and ? $src1_value & $src2_value :
+ $is_or ? $src1_value | $src2_value :
+ $is_xor ? $src1_value ^ $src2_value :
+ $is_add ? $src1_value + $src2_value :
+ $is_sub ? $src1_value - $src2_value :
+ $is_sll ? $src1_value << $src2_value[4:0] :
+ $is_srl ? $src1_value >> $src2_value[4:0] :
+ $is_sltu ? $sltu_rslt :
+ $is_sltiu ? $sltiu_rslt :
+ $is_lui ? {$imm[31:12], 12'b0} :
+ $is_auipc ? $pc + $imm :
+ $is_jal ? $pc + 32'd4 :
+ $is_jalr ? $pc + 32'd4 :
+ $is_srai ? {{32{$src1_value[31]}}, $src1_value} >> $imm[4:0] :
+ $is_slt ? (($src1_value[31] == $src2_value[31]) ? $sltu_rslt : {31'b0, $src1_value[31]}) :
+ $is_slti ? (($src1_value[31] == $imm[31]) ? $sltiu_rslt : {31'b0, $src1_value[31]}) :
+ $is_sra ? {{32{$src1_value[31]}}, $src1_value} >> $src2_value[4:0] :
+ 32'bx;
+
+ $is_jump = $is_jal || $is_jalr;
+ $valid_jump = $is_jump && $valid;
+
+ $rf_wr_en = ($rd_valid && $valid && $rd != 5'b0) || >>2$valid_load;
+ $rf_wr_index[4:0] = >>2$valid_load ? >>2$rd : $rd;
+ $rf_wr_data[31:0] = >>2$valid_load ? >>2$ld_data : $result;
+
+ @4
+ $dmem_wr_en = $is_s_instr && $valid;
+ $dmem_wr_data[31:0] = $src2_value;
+ $dmem_rd_en = $is_load;
+ $dmem_addr[3:0] = $result[5:2];
+
+ @5
+ $ld_data[31:0] = $dmem_rd_data;
+
+ // YOUR CODE HERE
+ // ...
+
+ // Note: Because of the magic we are using for visualisation, if visualisation is enabled below,
+ // be sure to avoid having unassigned signals (which you might be using for random inputs)
+ // other than those specifically expected in the labs. You'll get strange errors for these.
+
+
+ // Assert these to end simulation (before Makerchip cycle limit).
+ *passed = |cpu/xreg[15]>>5$value == (1+2+3+4+5+6+7+8+9);
+ *failed = 1'b0;
+
+ // Macro instantiations for:
+ // o instruction memory
+ // o register file
+ // o data memory
+ // o CPU visualization
+ |cpu
+ m4+imem(@1) // Args: (read stage)
+ m4+rf(@2, @3) // Args: (read stage, write stage) - if equal, no register bypass is required
+ m4+dmem(@4) // Args: (read/write stage)
+
+ m4+cpu_viz(@4) // For visualisation, argument should be at least equal to the last stage of CPU logic. @4 would work for all labs.
+\SV
+ endmodule
diff --git a/README.md b/README.md
index 6d41013..ad9929b 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,333 @@
-# RISC-V_MYTH_Workshop
+# RISC-V CPU CORE
-For students of "Microprocessor for You in Thirty Hours" Workshop, offered by for VLSI System Design (VSD) and Redwood EDA, find here accompanying live info and links.
+Follow this repo to build your RISC-V pipelined core, housing a RV64I instruction set.
+
+---
+**Codes:**
+- [Calculator with Memory](https://github.com/ninja3011/riscv-cpu-core/blob/0ef0985c46cd8b82766e21e9d06581bc470d742d/Day3_5/calculator_solutions.tlv)
+ Run in [makerchip](https://myth3.makerchip.com/sandbox?code_url=https:%2F%2Fraw.githubusercontent.com%2Fstevehoover%2FRISC-V_MYTH_Workshop%2Fmaster%2Fcalculator_shell.tlv)
+- [Pipelined RISC-V CPU CORE](https://github.com/ninja3011/riscv-cpu-core/blob/0ef0985c46cd8b82766e21e9d06581bc470d742d/Day3_5/risc-v_solutions.tlv)
+ Run in [makerchip](https://myth3.makerchip.com/sandbox?code_url=https:%2F%2Fraw.githubusercontent.com%2Fstevehoover%2FRISC-V_MYTH_Workshop%2Fmaster%2Frisc-v_shell.tlv)
+
+---
+# Table of Contents
+- [What is RISC-V ISA?](#what-is-risc-v-isa)
+- [GNU compiler toolchain](#risc-v-gnu-compiler-toolchain)
+- [Application Binary Interface](#application-binary-interface)
+- [TL-Verilog](#tl-verilog)
+- [Makerchip](#makerchip)
+ - [Combinational logic](#combinational-logic)
+ - [Sequential logic](#sequential-logic)
+ - [Pipelined logic](#pipelined-logic)
+ - [Validity](#validity)
+- [RISC-V CPU Architecture](#risc-v-cpu-architecture)
+ - [Fetch](#fetch)
+ - [Decode](#decode)
+ - [Execute](#execute)
+ - [Control Logic](#control-logic)
+ - [Base CPU](#base-cpu)
+- [Pipelined RISC-V CPU](#pipelined-risc-v-cpu)
+ - [Jump](#jump)
+ - [Completed Pipelined RISC-V CPU](#completed-pipelined-risc-v-cpu)
+- [Acknowledgements](#acknowledgements)
+
+# What is RISC-V ISA?
+
+- RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use.
+- Because the ISA is open, it is the equivalent of everyone having a micro architecture license. One can optimize designs for lower power, performance, security, etc.
+- RISC-V is much more than an open ISA, it is also a frozen ISA. The base instructions are frozen and optional extensions which have been approved are also frozen.
+
+# RISC-V GNU Compiler Toolchain
+
+- This is the RISC-V C and C++ cross-compiler. It supports two build modes:
+a generic ELF/Newlib toolchain and a more sophisticated Linux-ELF/glibc
+toolchain.
+- **Installation (UBUNTU) :**
+
+ * `$ sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev`
+ * `$ git clone https://github.com/riscv/riscv-gnu-toolchain`
+- **Configuration**
+
+ Pick an install path. If you choose, say, `/opt/riscv`, then add `/opt/riscv/bin` to your `PATH` now. Then, simply run the following command:
+ #### OPTIONS:
+ 1. **(Newlib)**
+
+ `./configure --prefix=/opt/riscv`
+
+ `make`
+
+ You should now be able to use riscv64-unknown-elf-gcc and its cousins.
+ 2. **(LINUX)**
+
+ *RV64GC (64-bit):*
+ `./configure --prefix=/opt/riscv`
+ `make linux`
+
+ *32-bit RV32GC :*
+ `./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d`
+ `make linux`
+ 3. **(MULTILIB)**
+
+ `./configure --prefix=/opt/riscv --enable-multilib`
+ `make` (FOR NEWLIB)
+ `make linux` (FOR LINUX)
+
+ The multilib compiler will have the prefix riscv64-unknown-elf- or riscv64-unknown-linux-gnu-, but will be able to target both 32-bit and 64-bit systems. It will support the most common `-march`/`-mabi` options, which can be seen by using the `--print-multi-lib` flag on either cross-compiler.
+
+#### COMMANDS
+
+ Under the risc-v toolchain,
+ * **Compile:**
+
+ `riscv64-unknown-elf-gcc -Ofast -mabi=lp64 -march=rv64i -o `
+
+ **Compile with options:**
+
+ `riscv64-unknown-elf-gcc -o `
+
+ [All Options](https://www.sifive.com/blog/all-aboard-part-1-compiler-args)
+
+ * **See Assembly**
+
+ `riscv64-unknown-elf-objdump -d