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davemgreendavemgreen
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[ARM] Add mayStore to more store instructions
As in llvm#121565 we need to mark all stores as mayStore, hasSideEffects is not enough to prevent moving loads past the instructions. And marking the instructions as mayStore is a sensible thing to do on its own.
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10 files changed

+59
-32
lines changed

10 files changed

+59
-32
lines changed

‎llvm/lib/Target/ARM/ARMInstrFormats.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -686,6 +686,8 @@ class AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrIt
686686
let Inst{9-8} = opcod2;
687687
let Inst{7-4} = 0b1001;
688688
let Inst{3-0} = Rt;
689+
690+
let mayStore = 1;
689691
}
690692
// Atomic load/store instructions
691693
class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,

‎llvm/lib/Target/ARM/ARMInstrInfo.td

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3388,6 +3388,8 @@ def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
33883388

33893389
// STRT, STRBT, and STRHT
33903390

3391+
let mayStore = 1, hasSideEffects = 0 in {
3392+
33913393
def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
33923394
(ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
33933395
IndexModePost, StFrm, IIC_iStore_bh_ru,
@@ -3428,7 +3430,6 @@ def STRBT_POST
34283430
: ARMAsmPseudo<"strbt${q} $Rt, $addr",
34293431
(ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
34303432

3431-
let mayStore = 1, hasSideEffects = 0 in {
34323433
def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
34333434
(ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
34343435
IndexModePost, StFrm, IIC_iStore_ru,
@@ -3464,7 +3465,6 @@ def STRT_POST_IMM
34643465
let Inst{11-0} = offset{11-0};
34653466
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
34663467
}
3467-
}
34683468

34693469
def STRT_POST
34703470
: ARMAsmPseudo<"strt${q} $Rt, $addr",
@@ -3493,7 +3493,6 @@ multiclass AI3strT<bits<4> op, string opc> {
34933493
}
34943494
}
34953495

3496-
34973496
defm STRHT : AI3strT<0b1011, "strht">;
34983497

34993498
def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
@@ -3503,6 +3502,8 @@ def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
35033502
def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
35043503
NoItinerary, "stlh", "\t$Rt, $addr", []>;
35053504

3505+
} // mayStore = 1, hasSideEffects = 0
3506+
35063507
//===----------------------------------------------------------------------===//
35073508
// Load / store multiple Instructions.
35083509
//
@@ -5633,15 +5634,19 @@ multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> {
56335634
}
56345635
}
56355636

5637+
let mayLoad = 1 in {
56365638
defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc timm:$cop, timm:$CRd, addrmode5:$addr)]>;
56375639
defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;
56385640
defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
56395641
defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
5642+
}
56405643

5644+
let mayStore = 1 in {
56415645
defm STC : LdStCop <0, 0, "stc", [(int_arm_stc timm:$cop, timm:$CRd, addrmode5:$addr)]>;
56425646
defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;
56435647
defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
56445648
defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
5649+
}
56455650

56465651
} // DecoderNamespace = "CoProc"
56475652

‎llvm/lib/Target/ARM/ARMInstrNEON.td

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8186,6 +8186,7 @@ def VLD1LNdWB_register_Asm_32 :
81868186
(ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
81878187
rGPR:$Rm, pred:$p)>;
81888188

8189+
let mayStore = 1 in {
81898190

81908191
// VST1 single-lane pseudo-instructions. These need special handling for
81918192
// the lane index that an InstAlias can't handle, so we use these instead.
@@ -8224,6 +8225,8 @@ def VST1LNdWB_register_Asm_32 :
82248225
(ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
82258226
rGPR:$Rm, pred:$p)>;
82268227

8228+
}
8229+
82278230
// VLD2 single-lane pseudo-instructions. These need special handling for
82288231
// the lane index that an InstAlias can't handle, so we use these instead.
82298232
def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
@@ -8282,6 +8285,7 @@ def VLD2LNqWB_register_Asm_32 :
82828285
(ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
82838286
rGPR:$Rm, pred:$p)>;
82848287

8288+
let mayStore = 1 in {
82858289

82868290
// VST2 single-lane pseudo-instructions. These need special handling for
82878291
// the lane index that an InstAlias can't handle, so we use these instead.
@@ -8342,6 +8346,8 @@ def VST2LNqWB_register_Asm_32 :
83428346
(ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
83438347
rGPR:$Rm, pred:$p)>;
83448348

8349+
}
8350+
83458351
// VLD3 all-lanes pseudo-instructions. These need special handling for
83468352
// the lane index that an InstAlias can't handle, so we use these instead.
83478353
def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
@@ -8531,6 +8537,8 @@ def VLD3qWB_register_Asm_32 :
85318537
(ins VecListThreeQ:$list, addrmode6align64:$addr,
85328538
rGPR:$Rm, pred:$p)>;
85338539

8540+
let mayStore = 1 in {
8541+
85348542
// VST3 single-lane pseudo-instructions. These need special handling for
85358543
// the lane index that an InstAlias can't handle, so we use these instead.
85368544
def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
@@ -8650,6 +8658,8 @@ def VST3qWB_register_Asm_32 :
86508658
(ins VecListThreeQ:$list, addrmode6align64:$addr,
86518659
rGPR:$Rm, pred:$p)>;
86528660

8661+
}
8662+
86538663
// VLD4 all-lanes pseudo-instructions. These need special handling for
86548664
// the lane index that an InstAlias can't handle, so we use these instead.
86558665
def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
@@ -8853,6 +8863,8 @@ def VLD4qWB_register_Asm_32 :
88538863
(ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
88548864
rGPR:$Rm, pred:$p)>;
88558865

8866+
let mayStore = 1 in {
8867+
88568868
// VST4 single-lane pseudo-instructions. These need special handling for
88578869
// the lane index that an InstAlias can't handle, so we use these instead.
88588870
def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
@@ -8983,6 +8995,7 @@ def VST4qWB_register_Asm_32 :
89838995
NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
89848996
(ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
89858997
rGPR:$Rm, pred:$p)>;
8998+
}
89868999

89879000
// VMOV/VMVN takes an optional datatype suffix
89889001
defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",

‎llvm/lib/Target/ARM/ARMInstrThumb2.td

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1795,6 +1795,8 @@ def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
17951795
Sched<[WriteST]>;
17961796
}
17971797

1798+
let mayStore = 1, hasSideEffects = 0 in {
1799+
17981800
// F5.1.229 STR (immediate) T4
17991801
// .w suffixes; Constraints can't be used on t2InstAlias to describe
18001802
// "$Rn = $Rn_wb,@earlyclobber $Rn_wb" on POST or
@@ -1850,6 +1852,8 @@ def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
18501852
def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
18511853
def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
18521854

1855+
} // mayStore = 1, hasSideEffects = 0
1856+
18531857
// ldrd / strd pre / post variants
18541858

18551859
let mayLoad = 1, hasSideEffects = 0 in
@@ -4482,16 +4486,19 @@ multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag>
44824486
}
44834487

44844488
let DecoderNamespace = "Thumb2CoProc" in {
4489+
let mayLoad = 1 in {
44854490
defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc timm:$cop, timm:$CRd, addrmode5:$addr)]>;
44864491
defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;
44874492
defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
44884493
defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4489-
4494+
}
4495+
let mayStore = 1 in {
44904496
defm t2STC : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc timm:$cop, timm:$CRd, addrmode5:$addr)]>;
44914497
defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;
44924498
defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
44934499
defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
44944500
}
4501+
}
44954502

44964503

44974504
//===----------------------------------------------------------------------===//

‎llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -306,10 +306,10 @@
306306
# CHECK-NEXT: 2 2 1.00 * strb r6, [r2], -r4
307307
# CHECK-NEXT: 2 3 1.00 * strb r7, [r12, -r3, lsl #5]
308308
# CHECK-NEXT: 2 2 1.00 * strb sp, [r7], r2, asr #12
309-
# CHECK-NEXT: 2 1 1.00 U strbt r6, [r2], #12
310-
# CHECK-NEXT: 2 1 1.00 U strbt r5, [r6], #-13
311-
# CHECK-NEXT: 2 2 1.00 U strbt r4, [r9], r5
312-
# CHECK-NEXT: 2 2 1.00 U strbt r3, [r8], -r2, lsl #3
309+
# CHECK-NEXT: 2 1 1.00 * strbt r6, [r2], #12
310+
# CHECK-NEXT: 2 1 1.00 * strbt r5, [r6], #-13
311+
# CHECK-NEXT: 2 2 1.00 * strbt r4, [r9], r5
312+
# CHECK-NEXT: 2 2 1.00 * strbt r3, [r8], -r2, lsl #3
313313
# CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r4]
314314
# CHECK-NEXT: 1 1 1.00 * strd r2, r3, [r6, #1]
315315
# CHECK-NEXT: 1 1 1.00 * strd r2, r3, [r6, r2]
@@ -332,10 +332,10 @@
332332
# CHECK-NEXT: 2 1 1.00 * strh r1, [r2, -r1]!
333333
# CHECK-NEXT: 2 1 1.00 * strh r9, [r7], r2
334334
# CHECK-NEXT: 2 1 1.00 * strh r4, [r3], -r2
335-
# CHECK-NEXT: 2 1 1.00 U strht r2, [r5], #76
336-
# CHECK-NEXT: 2 1 1.00 U strht r8, [r1], #-25
337-
# CHECK-NEXT: 2 1 1.00 U strht r5, [r3], r4
338-
# CHECK-NEXT: 2 1 1.00 U strht r6, [r8], -r0
335+
# CHECK-NEXT: 2 1 1.00 * strht r2, [r5], #76
336+
# CHECK-NEXT: 2 1 1.00 * strht r8, [r1], #-25
337+
# CHECK-NEXT: 2 1 1.00 * strht r5, [r3], r4
338+
# CHECK-NEXT: 2 1 1.00 * strht r6, [r8], -r0
339339

340340
# CHECK: Resources:
341341
# CHECK-NEXT: [0] - A57UnitB

‎llvm/test/tools/llvm-mca/ARM/cortex-a57-thumb.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1594,14 +1594,14 @@
15941594
# CHECK-NEXT: 1 1 1.00 * strh.w r8, [r8, r2, lsl #2]
15951595
# CHECK-NEXT: 1 1 1.00 * strh.w r7, [sp, r2, lsl #1]
15961596
# CHECK-NEXT: 1 1 1.00 * strh.w r7, [sp, r2]
1597-
# CHECK-NEXT: 2 1 1.00 U strht r1, [r2]
1598-
# CHECK-NEXT: 2 1 1.00 U strht r1, [r8]
1599-
# CHECK-NEXT: 2 1 1.00 U strht r1, [r8, #3]
1600-
# CHECK-NEXT: 2 1 1.00 U strht r1, [r8, #255]
1601-
# CHECK-NEXT: 1 1 1.00 U strt r1, [r2]
1602-
# CHECK-NEXT: 1 1 1.00 U strt r1, [r8]
1603-
# CHECK-NEXT: 1 1 1.00 U strt r1, [r8, #3]
1604-
# CHECK-NEXT: 1 1 1.00 U strt r1, [r8, #255]
1597+
# CHECK-NEXT: 2 1 1.00 * strht r1, [r2]
1598+
# CHECK-NEXT: 2 1 1.00 * strht r1, [r8]
1599+
# CHECK-NEXT: 2 1 1.00 * strht r1, [r8, #3]
1600+
# CHECK-NEXT: 2 1 1.00 * strht r1, [r8, #255]
1601+
# CHECK-NEXT: 1 1 1.00 * strt r1, [r2]
1602+
# CHECK-NEXT: 1 1 1.00 * strt r1, [r8]
1603+
# CHECK-NEXT: 1 1 1.00 * strt r1, [r8, #3]
1604+
# CHECK-NEXT: 1 1 1.00 * strt r1, [r8, #255]
16051605
# CHECK-NEXT: 0 0 0.00 U itet eq
16061606
# CHECK-NEXT: 1 1 0.50 subeq r1, r2, #4
16071607
# CHECK-NEXT: 1 1 0.50 subwne r5, r3, #1023

‎llvm/test/tools/llvm-mca/ARM/m4-int.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -776,7 +776,7 @@ yield
776776
# CHECK-NEXT: 1 1 1.00 * strb r0, [r1, r2]
777777
# CHECK-NEXT: 1 1 1.00 * strb.w r0, [r1, r2]
778778
# CHECK-NEXT: 1 1 1.00 * strb.w r0, [r1, r2, lsl #1]
779-
# CHECK-NEXT: 1 1 1.00 U strbt r0, [r1, #1]
779+
# CHECK-NEXT: 1 1 1.00 * strbt r0, [r1, #1]
780780
# CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r2, #4]
781781
# CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r2], #4
782782
# CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r2, #4]!
@@ -793,8 +793,8 @@ yield
793793
# CHECK-NEXT: 1 1 1.00 * strh r0, [r1, r2]
794794
# CHECK-NEXT: 1 1 1.00 * strh.w r0, [r1, r2]
795795
# CHECK-NEXT: 1 1 1.00 * strh.w r0, [r1, r2, lsl #1]
796-
# CHECK-NEXT: 1 1 1.00 U strht r0, [r1, #1]
797-
# CHECK-NEXT: 1 1 1.00 U strt r0, [r1, #1]
796+
# CHECK-NEXT: 1 1 1.00 * strht r0, [r1, #1]
797+
# CHECK-NEXT: 1 1 1.00 * strt r0, [r1, #1]
798798
# CHECK-NEXT: 1 1 1.00 U sub sp, #4
799799
# CHECK-NEXT: 1 1 1.00 sub.w r0, sp, #1
800800
# CHECK-NEXT: 1 1 1.00 subs.w r0, sp, #1

‎llvm/test/tools/llvm-mca/ARM/m55-int.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -836,7 +836,7 @@ yield
836836
# CHECK-NEXT: 1 1 1.00 * strb r0, [r1, r2]
837837
# CHECK-NEXT: 1 1 1.00 * strb.w r0, [r1, r2]
838838
# CHECK-NEXT: 1 1 1.00 * strb.w r0, [r1, r2, lsl #1]
839-
# CHECK-NEXT: 1 1 1.00 U strbt r0, [r1, #1]
839+
# CHECK-NEXT: 1 1 1.00 * strbt r0, [r1, #1]
840840
# CHECK-NEXT: 1 2 1.00 * strd r0, r1, [r2, #4]
841841
# CHECK-NEXT: 1 2 1.00 * strd r0, r1, [r2], #4
842842
# CHECK-NEXT: 1 2 1.00 * strd r0, r1, [r2, #4]!
@@ -853,8 +853,8 @@ yield
853853
# CHECK-NEXT: 1 1 1.00 * strh r0, [r1, r2]
854854
# CHECK-NEXT: 1 1 1.00 * strh.w r0, [r1, r2]
855855
# CHECK-NEXT: 1 1 1.00 * strh.w r0, [r1, r2, lsl #1]
856-
# CHECK-NEXT: 1 1 1.00 U strht r0, [r1, #1]
857-
# CHECK-NEXT: 1 1 1.00 U strt r0, [r1, #1]
856+
# CHECK-NEXT: 1 1 1.00 * strht r0, [r1, #1]
857+
# CHECK-NEXT: 1 1 1.00 * strt r0, [r1, #1]
858858
# CHECK-NEXT: 1 1 1.00 U sub sp, #4
859859
# CHECK-NEXT: 1 1 0.50 sub.w r0, sp, #1
860860
# CHECK-NEXT: 1 1 0.50 subs.w r0, sp, #1

‎llvm/test/tools/llvm-mca/ARM/m7-int.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -752,7 +752,7 @@ yield
752752
# CHECK-NEXT: 1 3 1.00 * strb r0, [r1, r2]
753753
# CHECK-NEXT: 1 3 1.00 * strb.w r0, [r1, r2]
754754
# CHECK-NEXT: 1 3 1.00 * strb.w r0, [r1, r2, lsl #1]
755-
# CHECK-NEXT: 1 3 1.00 U strbt r0, [r1, #1]
755+
# CHECK-NEXT: 1 3 1.00 * strbt r0, [r1, #1]
756756
# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2, #4]
757757
# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2], #4
758758
# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2, #4]!
@@ -769,8 +769,8 @@ yield
769769
# CHECK-NEXT: 1 3 1.00 * strh r0, [r1, r2]
770770
# CHECK-NEXT: 1 3 1.00 * strh.w r0, [r1, r2]
771771
# CHECK-NEXT: 1 3 1.00 * strh.w r0, [r1, r2, lsl #1]
772-
# CHECK-NEXT: 1 3 1.00 U strht r0, [r1, #1]
773-
# CHECK-NEXT: 1 3 1.00 U strt r0, [r1, #1]
772+
# CHECK-NEXT: 1 3 1.00 * strht r0, [r1, #1]
773+
# CHECK-NEXT: 1 3 1.00 * strt r0, [r1, #1]
774774
# CHECK-NEXT: 1 1 0.50 subs r0, r1, #1
775775
# CHECK-NEXT: 1 1 0.50 subs r0, #1
776776
# CHECK-NEXT: 1 1 0.50 sub.w r0, r1, #1

‎llvm/test/tools/llvm-mca/ARM/m85-int.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -865,7 +865,7 @@ yield.w
865865
# CHECK-NEXT: 1 3 0.50 * strb r0, [r1, r2]
866866
# CHECK-NEXT: 1 3 0.50 * strb.w r0, [r1, r2]
867867
# CHECK-NEXT: 1 3 0.50 * strb.w r0, [r1, r2, lsl #1]
868-
# CHECK-NEXT: 1 3 0.50 U strbt r0, [r1, #1]
868+
# CHECK-NEXT: 1 3 0.50 * strbt r0, [r1, #1]
869869
# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2, #4]
870870
# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2], #4
871871
# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2, #4]!
@@ -882,8 +882,8 @@ yield.w
882882
# CHECK-NEXT: 1 3 0.50 * strh r0, [r1, r2]
883883
# CHECK-NEXT: 1 3 0.50 * strh.w r0, [r1, r2]
884884
# CHECK-NEXT: 1 3 0.50 * strh.w r0, [r1, r2, lsl #1]
885-
# CHECK-NEXT: 1 3 0.50 U strht r0, [r1, #1]
886-
# CHECK-NEXT: 1 3 0.50 U strt r0, [r1, #1]
885+
# CHECK-NEXT: 1 3 0.50 * strht r0, [r1, #1]
886+
# CHECK-NEXT: 1 3 0.50 * strt r0, [r1, #1]
887887
# CHECK-NEXT: 1 2 0.50 U sub sp, #4
888888
# CHECK-NEXT: 1 1 0.50 sub.w r0, sp, #1
889889
# CHECK-NEXT: 1 1 0.50 subs.w r0, sp, #1

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