@@ -244,7 +244,6 @@ def __setitem__(self, reg, value):
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class WM8960 :
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-
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_bit_clock_divider_table = {
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2 : 0 ,
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3 : 1 ,
@@ -399,7 +398,6 @@ def __init__(
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self .config_data_format (sysclk , sample_rate , bits )
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def deinit (self ):
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self .set_module (MODULE_ADC , False )
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self .set_module (MODULE_DAC , False )
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self .set_module (MODULE_VREF , False )
@@ -467,33 +465,28 @@ def set_speaker_clock(self, sysclk):
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)
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def set_module (self , module , is_enabled ):
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is_enabled = 1 if is_enabled else 0
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regs = self .regs
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if module == MODULE_ADC :
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regs [_POWER1 ] = (
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_POWER1_ADCL_MASK | _POWER1_ADCR_MASK ,
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(_POWER1_ADCL_MASK | _POWER1_ADCR_MASK ) * is_enabled ,
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)
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elif module == MODULE_DAC :
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regs [_POWER2 ] = (
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_POWER2_DACL_MASK | _POWER2_DACR_MASK ,
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(_POWER2_DACL_MASK | _POWER2_DACR_MASK ) * is_enabled ,
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)
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elif module == MODULE_VREF :
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regs [_POWER1 ] = (
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_POWER1_VREF_MASK ,
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(is_enabled << _POWER1_VREF_SHIFT ),
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)
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elif module == MODULE_LINE_IN :
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regs [_POWER1 ] = (
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_POWER1_AINL_MASK | _POWER1_AINR_MASK ,
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(_POWER1_AINL_MASK | _POWER1_AINR_MASK ) * is_enabled ,
@@ -504,36 +497,31 @@ def set_module(self, module, is_enabled):
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)
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elif module == MODULE_LINE_OUT :
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regs [_POWER2 ] = (
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_POWER2_LOUT1_MASK | _POWER2_ROUT1_MASK ,
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(_POWER2_LOUT1_MASK | _POWER2_ROUT1_MASK ) * is_enabled ,
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)
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elif module == MODULE_MIC_BIAS :
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regs [_POWER1 ] = (
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_POWER1_MICB_MASK ,
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(is_enabled << _POWER1_MICB_SHIFT ),
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)
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elif module == MODULE_SPEAKER :
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regs [_POWER2 ] = (
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_POWER2_SPKL_MASK | _POWER2_SPKR_MASK ,
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(_POWER2_SPKL_MASK | _POWER2_SPKR_MASK ) * is_enabled ,
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)
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regs [_CLASSD1 ] = 0xF7
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elif module == MODULE_OMIX :
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regs [_POWER3 ] = (
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_POWER3_LOMIX_MASK | _POWER3_ROMIX_MASK ,
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(_POWER3_LOMIX_MASK | _POWER3_ROMIX_MASK ) * is_enabled ,
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)
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elif module == MODULE_MONO_OUT :
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regs [_MONOMIX1 ] = regs [_MONOMIX2 ] = is_enabled << 7
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regs [_MONO ] = is_enabled << 6
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