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nikicakiramenai
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[InstCombine] Fix APInt ctor assertion
The (extended) bit width might not fit into the (non-extended) type, resulting in an incorrect truncation of the compared value. Fix this by using m_SpecificInt(), which is both simpler and handles this correctly. Fixes the assertion failure reported in: llvm/llvm-project#114539 (comment)
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+18
-7
lines changed

2 files changed

+18
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llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1338,14 +1338,10 @@ Instruction *InstCombinerImpl::
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// low bits to skip = shift bitwidth - high bits to extract
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// The shift amount itself may be extended, and we need to look past zero-ext
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// when matching NBits, that will matter for matching later.
1341-
Constant *C;
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Value *NBits;
1343-
if (!match(
1344-
LowBitsToSkip,
1345-
m_ZExtOrSelf(m_Sub(m_Constant(C), m_ZExtOrSelf(m_Value(NBits))))) ||
1346-
!match(C, m_SpecificInt_ICMP(ICmpInst::Predicate::ICMP_EQ,
1347-
APInt(C->getType()->getScalarSizeInBits(),
1348-
X->getType()->getScalarSizeInBits()))))
1342+
if (!match(LowBitsToSkip,
1343+
m_ZExtOrSelf(m_Sub(m_SpecificInt(XTy->getScalarSizeInBits()),
1344+
m_ZExtOrSelf(m_Value(NBits))))))
13491345
return nullptr;
13501346

13511347
// Sign-extending value can be zero-extended if we `sub`tract it,

llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1137,3 +1137,18 @@ define i32 @n290_or_with_wrong_magic(i32 %data, i32 %nbits) {
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%signextended = or i32 %high_bits_extracted, %magic
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ret i32 %signextended
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}
1140+
1141+
define i32 @bitwidth_does_not_fit(i3 %arg) {
1142+
; CHECK-LABEL: @bitwidth_does_not_fit(
1143+
; CHECK-NEXT: [[NEG:%.*]] = sub i3 0, [[ARG:%.*]]
1144+
; CHECK-NEXT: [[NEG_EXT:%.*]] = zext i3 [[NEG]] to i32
1145+
; CHECK-NEXT: [[SHR:%.*]] = lshr i32 1, [[NEG_EXT]]
1146+
; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[SHR]], 1
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; CHECK-NEXT: ret i32 [[INC]]
1148+
;
1149+
%neg = sub i3 0, %arg
1150+
%neg.ext = zext i3 %neg to i32
1151+
%shr = lshr i32 1, %neg.ext
1152+
%inc = add i32 %shr, 1
1153+
ret i32 %inc
1154+
}

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