From 4320dda055b036b7fd0e925d5bb2541ac705ef6f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 5 Jun 2024 13:05:39 -0700 Subject: [PATCH] [RISCV] Use ForceTailAgnostic for masked vmsbf/vmsif/vmsof.m. These instructions use the mask policy, but always update the destination under tail agnostic policy. --- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 1 + llvm/test/CodeGen/RISCV/rvv/vmsbf.ll | 16 ++++++++-------- llvm/test/CodeGen/RISCV/rvv/vmsif.ll | 16 ++++++++-------- llvm/test/CodeGen/RISCV/rvv/vmsof.ll | 16 ++++++++-------- 4 files changed, 25 insertions(+), 24 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 5fe5a7a5bd5cc..222909d24e539 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -2059,6 +2059,7 @@ multiclass VPseudoVSFS_M { def "_M_" # mti.BX : VPseudoUnaryNoMask, SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx, forceMergeOpRead=true>; + let ForceTailAgnostic = true in def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask, SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx, forceMergeOpRead=true>; diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbf.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbf.ll index 14a1f084c3985..d1f344d52763d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsbf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsbf.ll @@ -33,7 +33,7 @@ define @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmsbf.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret @@ -75,7 +75,7 @@ define @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmsbf.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret @@ -117,7 +117,7 @@ define @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmsbf.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret @@ -159,9 +159,9 @@ define @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmsbf.m v10, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv8i1( @@ -201,7 +201,7 @@ define @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1( @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1( @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1( @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret @@ -75,7 +75,7 @@ define @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret @@ -117,7 +117,7 @@ define @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret @@ -159,9 +159,9 @@ define @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmsif.m v10, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv8i1( @@ -201,7 +201,7 @@ define @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1( @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1( @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1( @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret @@ -75,7 +75,7 @@ define @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret @@ -117,7 +117,7 @@ define @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret @@ -159,9 +159,9 @@ define @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1( ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmsof.m v10, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv8i1( @@ -201,7 +201,7 @@ define @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1( @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1( @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(