diff --git a/clang/test/Driver/aarch64-v95a.c b/clang/test/Driver/aarch64-v95a.c index 1037da65c8cb5..62878f2127626 100644 --- a/clang/test/Driver/aarch64-v95a.c +++ b/clang/test/Driver/aarch64-v95a.c @@ -6,7 +6,7 @@ // RUN: %clang -target aarch64 -mlittle-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A %s // RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A %s // RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A %s -// GENERICV95A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a" +// GENERICV95A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a"{{.*}} "-target-feature" "+cpa"{{.*}} "-target-feature" "+faminmax"{{.*}} "-target-feature" "+lut" // RUN: %clang -target aarch64_be -march=armv9.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s // RUN: %clang -target aarch64_be -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s @@ -14,14 +14,10 @@ // RUN: %clang -target aarch64 -mbig-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s // RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s // RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s -// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a" +// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a"{{.*}} "-target-feature" "+cpa"{{.*}} "-target-feature" "+faminmax"{{.*}} "-target-feature" "+lut" // ===== Features supported on aarch64 ===== -// RUN: %clang -target aarch64 -march=armv9.5a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s -// RUN: %clang -target aarch64 -march=armv9.5-a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s -// V95A-CPA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a"{{.*}} "-target-feature" "+cpa" - // RUN: %clang -target aarch64 -march=armv9.5a+pauth-lr -### -c %s 2>&1 | FileCheck -check-prefix=V95A-PAUTHLR %s // RUN: %clang -target aarch64 -march=armv9.5-a+pauth-lr -### -c %s 2>&1 | FileCheck -check-prefix=V95A-PAUTHLR %s // V95A-PAUTHLR: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a"{{.*}} "-target-feature" "+pauth-lr" diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index ba0b760ce3d73..ffb899a301459 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -223,13 +223,6 @@ def FeatureSVE : Extension<"sve", "SVE", "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16], "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>; -def FeatureFPMR : Extension<"fpmr", "FPMR", - "Enable FPMR Register (FEAT_FPMR)">; - -let FMVDependencies = "+fpmr" in -def FeatureFP8 : Extension<"fp8", "FP8", - "Enable FP8 instructions (FEAT_FP8)">; - // This flag is currently still labeled as Experimental, but when fully // implemented this should tell the compiler to use the zeroing pseudos to // benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive @@ -667,41 +660,44 @@ def FeatureSME2p1 : Extension<"sme2p1", "SME2p1", def FeatureFAMINMAX: Extension<"faminmax", "FAMINMAX", "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">; -let FMVDependencies = "+fpmr" in +def FeatureLUT: Extension<"lut", "LUT", + "Enable Lookup Table instructions (FEAT_LUT)">; + +def FeatureFP8 : Extension<"fp8", "FP8", + "Enable FP8 instructions (FEAT_FP8)", [FeatureFAMINMAX, FeatureLUT, FeatureBF16]>; + def FeatureFP8FMA : Extension<"fp8fma", "FP8FMA", - "Enable fp8 multiply-add instructions (FEAT_FP8FMA)">; + "Enable fp8 multiply-add instructions (FEAT_FP8FMA)", [FeatureFP8]>; let FMVDependencies = "+sme2" in def FeatureSSVE_FP8FMA : Extension<"ssve-fp8fma", "SSVE_FP8FMA", - "Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2]>; + "Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2, FeatureFP8]>; +def FeatureFP8DOT4: Extension<"fp8dot4", "FP8DOT4", + "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)", [FeatureFP8FMA]>; + def FeatureFP8DOT2: Extension<"fp8dot2", "FP8DOT2", - "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)">; + "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)", [FeatureFP8DOT4]>; let FMVDependencies = "+sme2" in -def FeatureSSVE_FP8DOT2 : Extension<"ssve-fp8dot2", "SSVE_FP8DOT2", - "Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSME2]>; - -def FeatureFP8DOT4: Extension<"fp8dot4", "FP8DOT4", - "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)">; +def FeatureSSVE_FP8DOT4 : Extension<"ssve-fp8dot4", "SSVE_FP8DOT4", + "Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSSVE_FP8FMA]>; let FMVDependencies = "+sme2" in -def FeatureSSVE_FP8DOT4 : Extension<"ssve-fp8dot4", "SSVE_FP8DOT4", - "Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSME2]>; -def FeatureLUT: Extension<"lut", "LUT", - "Enable Lookup Table instructions (FEAT_LUT)">; +def FeatureSSVE_FP8DOT2 : Extension<"ssve-fp8dot2", "SSVE_FP8DOT2", + "Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSSVE_FP8DOT4]>; def FeatureSME_LUTv2 : Extension<"sme-lutv2", "SME_LUTv2", "Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">; -let FMVDependencies = "+fp8,+sme2" in -def FeatureSMEF8F16 : Extension<"sme-f8f16", "SMEF8F16", - "Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSME2, FeatureFP8]>; - let FMVDependencies = "+sme2,+fp8" in def FeatureSMEF8F32 : Extension<"sme-f8f32", "SMEF8F32", "Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>; +let FMVDependencies = "+fp8,+sme2" in +def FeatureSMEF8F16 : Extension<"sme-f8f16", "SMEF8F16", + "Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSMEF8F32]>; + def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true", "Apple A7 (the CPU formerly known as Cyclone)">; @@ -869,7 +865,7 @@ def HasV9_4aOps : Architecture64<9, 4, "a", "v9.4a", FeatureRASv2])>; def HasV9_5aOps : Architecture64<9, 5, "a", "v9.5a", [HasV9_4aOps, FeatureCPA], - !listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA])>; + !listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA, FeatureLUT, FeatureFAMINMAX])>; def HasV8_0rOps : Architecture64<8, 0, "r", "v8r", [ //v8.1 FeatureCRC, FeaturePAN, FeatureLSE, FeatureCONTEXTIDREL2, diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index a39e3b7be76dc..4830033b23527 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -171,8 +171,6 @@ def HasSME2 : Predicate<"Subtarget->hasSME2()">, AssemblerPredicateWithAll<(all_of FeatureSME2), "sme2">; def HasSME2p1 : Predicate<"Subtarget->hasSME2p1()">, AssemblerPredicateWithAll<(all_of FeatureSME2p1), "sme2p1">; -def HasFPMR : Predicate<"Subtarget->hasFPMR()">, - AssemblerPredicateWithAll<(all_of FeatureFPMR), "fpmr">; def HasFP8 : Predicate<"Subtarget->hasFP8()">, AssemblerPredicateWithAll<(all_of FeatureFP8), "fp8">; def HasFAMINMAX : Predicate<"Subtarget->hasFAMINMAX()">, diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 0564741c49700..0b5bc97674c76 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -1943,11 +1943,9 @@ def : RWSysReg<"PM", 0b11, 0b000, 0b0100, 0b0011, 0b001>; // 2023 ISA Extension // AArch64 Floating-point Mode Register controls behaviors of the FP8 // instructions (FEAT_FPMR) -let Requires = [{ {AArch64::FeatureFPMR} }] in { // Op0 Op1 CRn CRm Op2 def : ROSysReg<"ID_AA64FPFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b111>; def : RWSysReg<"FPMR", 0b11, 0b011, 0b0100, 0b0100, 0b010>; -} // v9.5a Software Stepping Enhancements (FEAT_STEP2) // Op0 Op1 CRn CRm Op2 diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index c9bba9bf63142..13a68b7dcf984 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3718,7 +3718,6 @@ static const struct Extension { {"sb", {AArch64::FeatureSB}}, {"ssbs", {AArch64::FeatureSSBS}}, {"tme", {AArch64::FeatureTME}}, - {"fpmr", {AArch64::FeatureFPMR}}, {"fp8", {AArch64::FeatureFP8}}, {"faminmax", {AArch64::FeatureFAMINMAX}}, {"fp8fma", {AArch64::FeatureFP8FMA}}, @@ -3731,7 +3730,7 @@ static const struct Extension { {"sme-lutv2", {AArch64::FeatureSME_LUTv2}}, {"sme-f8f16", {AArch64::FeatureSMEF8F16}}, {"sme-f8f32", {AArch64::FeatureSMEF8F32}}, - {"sme-fa64", {AArch64::FeatureSMEFA64}}, + {"sme-fa64", {AArch64::FeatureSMEFA64}}, {"cpa", {AArch64::FeatureCPA}}, {"tlbiw", {AArch64::FeatureTLBIW}}, }; diff --git a/llvm/test/MC/AArch64/FP8/system-regs.s b/llvm/test/MC/AArch64/FP8/system-regs.s index 4a396d4dff82b..8959a7727b196 100644 --- a/llvm/test/MC/AArch64/FP8/system-regs.s +++ b/llvm/test/MC/AArch64/FP8/system-regs.s @@ -1,11 +1,9 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fpmr < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ -// RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fpmr < %s \ -// RUN: | llvm-objdump -d --mattr=+fpmr - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fpmr < %s \ -// RUN: | llvm-objdump --mattr=-fpmr -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN // --------------------------------------------------------------------------// // read @@ -13,14 +11,13 @@ mrs x3, FPMR // CHECK-INST: mrs x3, FPMR // CHECK-ENCODING: [0x43,0x44,0x3b,0xd5] -// CHECK-ERROR: expected readable system register -// CHECK-UNKNOWN: d53b4443 mrs x3, S3_3_C4_C4_2 +// CHECK-UNKNOWN: d53b4443 mrs x3, FPMR + mrs x3, ID_AA64FPFR0_EL1 // CHECK-INST: mrs x3, ID_AA64FPFR0_EL1 // CHECK-ENCODING: [0xe3,0x04,0x38,0xd5] -// CHECK-ERROR: expected readable system register -// CHECK-UNKNOWN: d53804e3 mrs x3, S3_0_C0_C4_7 +// CHECK-UNKNOWN: d53804e3 mrs x3, ID_AA64FPFR0_EL1 // --------------------------------------------------------------------------// // write @@ -28,5 +25,4 @@ mrs x3, ID_AA64FPFR0_EL1 msr FPMR, x3 // CHECK-INST: msr FPMR, x3 // CHECK-ENCODING: [0x43,0x44,0x1b,0xd5] -// CHECK-ERROR: expected writable system register or pstate -// CHECK-UNKNOWN: d51b4443 msr S3_3_C4_C4_2, x3 +// CHECK-UNKNOWN: d51b4443 msr FPMR, x3 \ No newline at end of file diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 0455e061f0bf7..797d7dfbca200 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1996,7 +1996,6 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { AArch64::AEK_D128, AArch64::AEK_LSE128, AArch64::AEK_SPECRES2, AArch64::AEK_RASV2, AArch64::AEK_ITE, AArch64::AEK_GCS, - AArch64::AEK_FPMR, AArch64::AEK_FP8, AArch64::AEK_FAMINMAX, AArch64::AEK_FP8FMA, AArch64::AEK_SSVE_FP8FMA, AArch64::AEK_FP8DOT2, AArch64::AEK_SSVE_FP8DOT2, AArch64::AEK_FP8DOT4, @@ -2005,7 +2004,8 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { AArch64::AEK_SMEF8F32, AArch64::AEK_SMEFA64, AArch64::AEK_CPA, AArch64::AEK_PAUTHLR, AArch64::AEK_TLBIW, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA, + AArch64::AEK_FCMA, AArch64::AEK_FP8, + }; std::vector Features; @@ -2078,7 +2078,6 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { EXPECT_TRUE(llvm::is_contained(Features, "+specres2")); EXPECT_TRUE(llvm::is_contained(Features, "+ite")); EXPECT_TRUE(llvm::is_contained(Features, "+gcs")); - EXPECT_TRUE(llvm::is_contained(Features, "+fpmr")); EXPECT_TRUE(llvm::is_contained(Features, "+fp8")); EXPECT_TRUE(llvm::is_contained(Features, "+faminmax")); EXPECT_TRUE(llvm::is_contained(Features, "+fp8fma")); @@ -2224,7 +2223,6 @@ TEST(TargetParserTest, AArch64ArchExtFeature) { {"predres2", "nopredres2", "+specres2", "-specres2"}, {"rasv2", "norasv2", "+rasv2", "-rasv2"}, {"gcs", "nogcs", "+gcs", "-gcs"}, - {"fpmr", "nofpmr", "+fpmr", "-fpmr"}, {"fp8", "nofp8", "+fp8", "-fp8"}, {"faminmax", "nofaminmax", "+faminmax", "-faminmax"}, {"fp8fma", "nofp8fma", "+fp8fma", "-fp8fma"},