From 4046e8eed292973725730cad77acc9daa4866635 Mon Sep 17 00:00:00 2001 From: Xuan Zhang Date: Fri, 26 Apr 2024 13:04:38 -0700 Subject: [PATCH 1/4] outlining order by benefit-to-cost ratio --- llvm/lib/CodeGen/MachineOutliner.cpp | 6 +- .../machine-outliner-sort-per-priority.ll | 96 +++++++++++++++++++ .../CodeGen/ARM/machine-outliner-calls.mir | 80 ++++++---------- .../CodeGen/ARM/machine-outliner-default.mir | 33 +++---- .../ARM/machine-outliner-stack-fixup-arm.mir | 56 +++++------ .../machine-outliner-stack-fixup-thumb.mir | 74 ++++++-------- 6 files changed, 194 insertions(+), 151 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp index 626e577a30bf3..9e2e6316dc6d1 100644 --- a/llvm/lib/CodeGen/MachineOutliner.cpp +++ b/llvm/lib/CodeGen/MachineOutliner.cpp @@ -828,10 +828,12 @@ bool MachineOutliner::outline(Module &M, << "\n"); bool OutlinedSomething = false; - // Sort by benefit. The most beneficial functions should be outlined first. + // Sort by priority where priority := getNotOutlinedCost / getOutliningCost. + // The function with highest priority should be outlined first. stable_sort(FunctionList, [](const OutlinedFunction &LHS, const OutlinedFunction &RHS) { - return LHS.getBenefit() > RHS.getBenefit(); + return LHS.getNotOutlinedCost() * RHS.getOutliningCost() > + RHS.getNotOutlinedCost() * LHS.getOutliningCost(); }); // Walk over each function, outlining them as we go along. Functions are diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll b/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll new file mode 100644 index 0000000000000..00efc3c6e71c8 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll @@ -0,0 +1,96 @@ +; This tests the order in which functions are outlined in MachineOutliner +; There are TWO key OutlinedFunction in FunctionList +; +; ===================== First One ===================== +; ``` +; mov w0, #1 +; mov w1, #2 +; mov w2, #3 +; mov w3, #4 +; mov w4, #5 +; ``` +; It has: +; - `SequenceSize=20` and `OccurrenceCount=6` +; - each Candidate has `CallOverhead=12` and `FrameOverhead=4` +; - `NotOutlinedCost=20*6=120` and `OutliningCost=12*6+20+4=96` +; - `Benefit=120-96=24` and `Priority=120/96=1.25` +; +; ===================== Second One ===================== +; ``` +; mov w6, #6 +; mov w7, #7 +; b +; ``` +; It has: +; - `SequenceSize=12` and `OccurrenceCount=4` +; - each Candidate has `CallOverhead=4` and `FrameOverhead=0` +; - `NotOutlinedCost=12*4=48` and `OutliningCost=4*4+12+0=28` +; - `Benefit=120-96=20` and `Priority=48/28=1.71` +; +; Note that the first one has higher benefit, but lower priority. +; Hence, when outlining per priority, the second one will be outlined first. + +; RUN: llc %s -enable-machine-outliner=always -filetype=obj -o %t +; RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=CHECK-SORT-BY-PRIORITY + +; RUN: llc %s -enable-machine-outliner=always -outliner-benefit-threshold=22 -filetype=obj -o %t +; RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=CHECK-THRESHOLD + + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-macosx14.0.0" + +declare i32 @_Z3fooiiii(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) + +define i32 @_Z2f1v() minsize { + %1 = tail call i32 @_Z3fooiiii(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 11, i32 noundef 6, i32 noundef 7) + ret i32 %1 +} + +define i32 @_Z2f2v() minsize { + %1 = tail call i32 @_Z3fooiiii(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 12, i32 noundef 6, i32 noundef 7) + ret i32 %1 +} + +define i32 @_Z2f3v() minsize { + %1 = tail call i32 @_Z3fooiiii(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 13, i32 noundef 6, i32 noundef 7) + ret i32 %1 +} + +define i32 @_Z2f4v() minsize { + %1 = tail call i32 @_Z3fooiiii(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 14, i32 noundef 6, i32 noundef 7) + ret i32 %1 +} + +define i32 @_Z2f5v() minsize { + %1 = tail call i32 @_Z3fooiiii(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 15, i32 noundef 8, i32 noundef 9) + ret i32 %1 +} + +define i32 @_Z2f6v() minsize { + %1 = tail call i32 @_Z3fooiiii(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 16, i32 noundef 9, i32 noundef 8) + ret i32 %1 +} + +; CHECK-SORT-BY-PRIORITY: <_OUTLINED_FUNCTION_0>: +; CHECK-SORT-BY-PRIORITY-NEXT: mov w6, #0x6 +; CHECK-SORT-BY-PRIORITY-NEXT: mov w7, #0x7 +; CHECK-SORT-BY-PRIORITY-NEXT: b + +; CHECK-SORT-BY-PRIORITY: <_OUTLINED_FUNCTION_1>: +; CHECK-SORT-BY-PRIORITY-NEXT: mov w0, #0x1 +; CHECK-SORT-BY-PRIORITY-NEXT: mov w1, #0x2 +; CHECK-SORT-BY-PRIORITY-NEXT: mov w2, #0x3 +; CHECK-SORT-BY-PRIORITY-NEXT: mov w3, #0x4 +; CHECK-SORT-BY-PRIORITY-NEXT: mov w4, #0x5 +; CHECK-SORT-BY-PRIORITY-NEXT: ret + +; CHECK-THRESHOLD: <_OUTLINED_FUNCTION_0>: +; CHECK-THRESHOLD-NEXT: mov w0, #0x1 +; CHECK-THRESHOLD-NEXT: mov w1, #0x2 +; CHECK-THRESHOLD-NEXT: mov w2, #0x3 +; CHECK-THRESHOLD-NEXT: mov w3, #0x4 +; CHECK-THRESHOLD-NEXT: mov w4, #0x5 +; CHECK-THRESHOLD-NEXT: ret + +; CHECK-THRESHOLD-NOT: <_OUTLINED_FUNCTION_1>: diff --git a/llvm/test/CodeGen/ARM/machine-outliner-calls.mir b/llvm/test/CodeGen/ARM/machine-outliner-calls.mir index a92c9dd28be5a..7634ecd6e863a 100644 --- a/llvm/test/CodeGen/ARM/machine-outliner-calls.mir +++ b/llvm/test/CodeGen/ARM/machine-outliner-calls.mir @@ -26,15 +26,15 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: BL @OUTLINED_FUNCTION_0 + ; CHECK: BL @OUTLINED_FUNCTION_2 ; CHECK: bb.1: - ; CHECK: BL @OUTLINED_FUNCTION_0 + ; CHECK: BL @OUTLINED_FUNCTION_2 ; CHECK: bb.2: - ; CHECK: BL @OUTLINED_FUNCTION_0 + ; CHECK: BL @OUTLINED_FUNCTION_2 ; CHECK: bb.3: - ; CHECK: BL @OUTLINED_FUNCTION_0 + ; CHECK: BL @OUTLINED_FUNCTION_2 ; CHECK: bb.4: - ; CHECK: BL @OUTLINED_FUNCTION_0 + ; CHECK: BL @OUTLINED_FUNCTION_2 ; CHECK: bb.5: ; CHECK: $sp = frame-destroy LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $lr ; CHECK: BX_RET 14 /* CC::al */, $noreg @@ -139,13 +139,13 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: BL @OUTLINED_FUNCTION_1 + ; CHECK: BL @OUTLINED_FUNCTION_0 ; CHECK: bb.1: - ; CHECK: BL @OUTLINED_FUNCTION_1 + ; CHECK: BL @OUTLINED_FUNCTION_0 ; CHECK: bb.2: - ; CHECK: BL @OUTLINED_FUNCTION_1 + ; CHECK: BL @OUTLINED_FUNCTION_0 ; CHECK: bb.3: - ; CHECK: BL @OUTLINED_FUNCTION_1 + ; CHECK: BL @OUTLINED_FUNCTION_0 ; CHECK: bb.4: ; CHECK: $sp = frame-destroy LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $lr ; CHECK: BX_RET 14 /* CC::al */, $noreg @@ -245,19 +245,19 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp - ; CHECK: BL @OUTLINED_FUNCTION_2 + ; CHECK: BL @OUTLINED_FUNCTION_1 ; CHECK: bb.1: ; CHECK: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp - ; CHECK: BL @OUTLINED_FUNCTION_2 + ; CHECK: BL @OUTLINED_FUNCTION_1 ; CHECK: bb.2: ; CHECK: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp - ; CHECK: BL @OUTLINED_FUNCTION_2 + ; CHECK: BL @OUTLINED_FUNCTION_1 ; CHECK: bb.3: ; CHECK: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp - ; CHECK: BL @OUTLINED_FUNCTION_2 + ; CHECK: BL @OUTLINED_FUNCTION_1 ; CHECK: bb.4: ; CHECK: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp - ; CHECK: BL @OUTLINED_FUNCTION_2 + ; CHECK: BL @OUTLINED_FUNCTION_1 ; CHECK: bb.5: ; CHECK: $sp = frame-destroy LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $lr ; CHECK: BX_RET 14 /* CC::al */, $noreg @@ -307,38 +307,17 @@ body: | bb.0: BX_RET 14, $noreg - ; CHECK-LABEL: name: OUTLINED_FUNCTION_0 ; CHECK: bb.0: - ; CHECK: liveins: $r11, $r10, $r9, $r8, $r7, $r6, $r5, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr - ; CHECK: early-clobber $sp = frame-setup STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8 - ; CHECK: BL @bar, implicit-def dead $lr, implicit $sp - ; CHECK: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r3 = MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r4 = MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr, $sp = frame-destroy LDR_POST_IMM $sp, $noreg, 8, 14 /* CC::al */, $noreg - ; CHECK: MOVPCLR 14 /* CC::al */, $noreg - - ; CHECK-LABEL: name: OUTLINED_FUNCTION_1 - ; CHECK: bb.0: - ; CHECK: liveins: $r11, $r10, $r9, $r8, $r7, $r6, $r5, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr - ; CHECK: early-clobber $sp = frame-setup STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8 - ; CHECK: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK: liveins: $r11, $r10, $r9, $r8, $r7, $r6, $r5, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8 ; CHECK: $r0 = MOVi 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r2 = MOVi 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r3 = MOVi 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r4 = MOVi 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr, $sp = frame-destroy LDR_POST_IMM $sp, $noreg, 8, 14 /* CC::al */, $noreg ; CHECK: TAILJMPd @bar, implicit $sp - ; CHECK-LABEL: name: OUTLINED_FUNCTION_2 + ; CHECK-LABEL: name: OUTLINED_FUNCTION_1 ; CHECK: bb.0: ; CHECK: liveins: $r11, $r10, $r9, $r8, $r7, $r6, $r5, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8 ; CHECK: $r0 = MOVi 3, 14 /* CC::al */, $noreg, $noreg @@ -348,31 +327,28 @@ body: | ; CHECK: $r4 = MOVi 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: MOVPCLR 14 /* CC::al */, $noreg + ; CHECK-LABEL: name: OUTLINED_FUNCTION_2 + ; CHECK: bb.0: + ; CHECK: liveins: $r11, $r10, $r9, $r8, $r7, $r6, $r5, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8 + ; CHECK: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: $r3 = MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: $r4 = MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: MOVPCLR 14 /* CC::al */, $noreg + ; CHECK-LABEL: name: OUTLINED_FUNCTION_3 ; CHECK: bb.0: - ; CHECK: liveins: $r11, $r10, $r9, $r8, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr - ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8 - ; CHECK: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK: liveins: $r11, $r10, $r9, $r8, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8 ; CHECK: $r0 = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r1 = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r2 = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg ; CHECK: tTAILJMPdND @bar, 14 /* CC::al */, $noreg, implicit $sp ; CHECK-LABEL: name: OUTLINED_FUNCTION_4 ; CHECK: bb.0: - ; CHECK: liveins: $r11, $r10, $r9, $r8, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr - ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8 - ; CHECK: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK: liveins: $r11, $r10, $r9, $r8, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8 ; CHECK: $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg - - - diff --git a/llvm/test/CodeGen/ARM/machine-outliner-default.mir b/llvm/test/CodeGen/ARM/machine-outliner-default.mir index 6d0218dbfe636..de2b8f5596976 100644 --- a/llvm/test/CodeGen/ARM/machine-outliner-default.mir +++ b/llvm/test/CodeGen/ARM/machine-outliner-default.mir @@ -19,17 +19,17 @@ body: | ; CHECK: bb.0: ; CHECK: liveins: $lr ; CHECK: early-clobber $sp = frame-setup STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: BL @OUTLINED_FUNCTION_0 + ; CHECK: BL @OUTLINED_FUNCTION_1 ; CHECK: $lr, $sp = frame-destroy LDR_POST_IMM $sp, $noreg, 8, 14 /* CC::al */, $noreg ; CHECK: bb.1: ; CHECK: liveins: $lr, $r6, $r7, $r8, $r9, $r10, $r11 ; CHECK: early-clobber $sp = frame-setup STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: BL @OUTLINED_FUNCTION_0 + ; CHECK: BL @OUTLINED_FUNCTION_1 ; CHECK: $lr, $sp = frame-destroy LDR_POST_IMM $sp, $noreg, 8, 14 /* CC::al */, $noreg ; CHECK: bb.2: ; CHECK: liveins: $lr, $r6, $r7, $r8, $r9, $r10, $r11 ; CHECK: early-clobber $sp = frame-setup STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: BL @OUTLINED_FUNCTION_0 + ; CHECK: BL @OUTLINED_FUNCTION_1 ; CHECK: $lr, $sp = frame-destroy LDR_POST_IMM $sp, $noreg, 8, 14 /* CC::al */, $noreg ; CHECK: bb.3: ; CHECK: liveins: $lr, $r6, $r7, $r8, $r9, $r10, $r11 @@ -73,17 +73,17 @@ body: | ; CHECK: bb.0: ; CHECK: liveins: $lr ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_1 + ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0 ; CHECK: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg ; CHECK: bb.1: ; CHECK: liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_1 + ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0 ; CHECK: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg ; CHECK: bb.2: ; CHECK: liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_1 + ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0 ; CHECK: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg ; CHECK: bb.3: ; CHECK: liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 @@ -114,6 +114,15 @@ body: | ; CHECK-LABEL: name: OUTLINED_FUNCTION_0 ; CHECK: bb.0: + ; CHECK: liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 + ; CHECK: $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: $r3 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: tBX_RET 14 /* CC::al */, $noreg + + ; CHECK-LABEL: name: OUTLINED_FUNCTION_1 + ; CHECK: bb.0: ; CHECK: liveins: $lr, $r6, $r7, $r8, $r9, $r10, $r11 ; CHECK: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg @@ -122,15 +131,3 @@ body: | ; CHECK: $r4 = MOVi 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r5 = MOVi 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: MOVPCLR 14 /* CC::al */, $noreg - - ; CHECK-LABEL: name: OUTLINED_FUNCTION_1 - ; CHECK: bb.0: - ; CHECK: liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 - ; CHECK: $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r3 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: tBX_RET 14 /* CC::al */, $noreg - - - diff --git a/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir b/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir index ae5caa5b7c06d..e71edc8ceb3f6 100644 --- a/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir +++ b/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir @@ -18,6 +18,7 @@ body: | liveins: $r0 ; CHECK-LABEL: name: CheckAddrMode_i12 ; CHECK: $r1 = MOVr killed $r0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp ; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I12:[0-9]+]] ; CHECK-NEXT: $r6 = LDRi12 $sp, 4088, 14 /* CC::al */, $noreg $r1 = MOVr killed $r0, 14, $noreg, $noreg @@ -47,6 +48,7 @@ body: | liveins: $r1 ; CHECK-LABEL: name: CheckAddrMode3 ; CHECK: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp ; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I3:[0-9]+]] ; CHECK-NEXT: $r6 = LDRSH $sp, $noreg, 248, 14 /* CC::al */, $noreg $r0 = MOVr killed $r1, 14, $noreg, $noreg @@ -76,6 +78,7 @@ body: | liveins: $r2 ; CHECK-LABEL: name: CheckAddrMode5 ; CHECK: $r0 = MOVr killed $r2, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp ; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I5:[0-9]+]] ; CHECK-NEXT: $d5 = VLDRD $sp, 254, 14 /* CC::al */, $noreg $r0 = MOVr killed $r2, 14, $noreg, $noreg @@ -110,6 +113,7 @@ body: | liveins: $r3 ; CHECK-LABEL: name: CheckAddrMode5FP16 ; CHECK: $r0 = MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp ; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I5FP16:[0-9]+]] ; CHECK-NEXT: $s6 = VLDRH $sp, 252, 14, $noreg $r0 = MOVr killed $r3, 14, $noreg, $noreg @@ -146,41 +150,29 @@ body: | BX_RET 14, $noreg ;CHECK: name: OUTLINED_FUNCTION_[[I5]] - ;CHECK: early-clobber $sp = frame-setup STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -8 - ;CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp - ;CHECK-NEXT: $d0 = VLDRD $sp, 2, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $d1 = VLDRD $sp, 10, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $d4 = VLDRD $sp, 255, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $lr, $sp = frame-destroy LDR_POST_IMM $sp, $noreg, 8, 14 /* CC::al */, $noreg + ;CHECK: liveins: $r10, $r9, $r8, $r7, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8 + ;CHECK: $d0 = VLDRD $sp, 0, 14 /* CC::al */, $noreg + ;CHECK-NEXT: $d1 = VLDRD $sp, 8, 14 /* CC::al */, $noreg + ;CHECK-NEXT: $d4 = VLDRD $sp, 253, 14 /* CC::al */, $noreg + ;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg ;CHECK: name: OUTLINED_FUNCTION_[[I5FP16]] - ;CHECK: early-clobber $sp = frame-setup STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -8 - ;CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp - ;CHECK-NEXT: $s1 = VLDRH $sp, 4, 14, $noreg - ;CHECK-NEXT: $s2 = VLDRH $sp, 12, 14, $noreg - ;CHECK-NEXT: $s5 = VLDRH $sp, 244, 14, $noreg - ;CHECK-NEXT: $lr, $sp = frame-destroy LDR_POST_IMM $sp, $noreg, 8, 14 /* CC::al */, $noreg + ;CHECK: liveins: $r10, $r9, $r8, $r7, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8 + ;CHECK: $s1 = VLDRH $sp, 0, 14, $noreg + ;CHECK-NEXT: $s2 = VLDRH $sp, 8, 14, $noreg + ;CHECK-NEXT: $s5 = VLDRH $sp, 240, 14, $noreg + ;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg ;CHECK: name: OUTLINED_FUNCTION_[[I12]] - ;CHECK: early-clobber $sp = frame-setup STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -8 - ;CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp - ;CHECK-NEXT: $r1 = LDRi12 $sp, 8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $r2 = LDRi12 $sp, 16, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $r5 = LDRi12 $sp, 4094, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $lr, $sp = frame-destroy LDR_POST_IMM $sp, $noreg, 8, 14 /* CC::al */, $noreg + ;CHECK: liveins: $r10, $r9, $r8, $r7, $d8, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9 + ;CHECK: $r1 = LDRi12 $sp, 0, 14 /* CC::al */, $noreg + ;CHECK-NEXT: $r2 = LDRi12 $sp, 8, 14 /* CC::al */, $noreg + ;CHECK-NEXT: $r5 = LDRi12 $sp, 4086, 14 /* CC::al */, $noreg + ;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg ;CHECK: name: OUTLINED_FUNCTION_[[I3]] - ;CHECK: early-clobber $sp = frame-setup STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -8 - ;CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp - ;CHECK-NEXT: $r1 = LDRSH $sp, $noreg, 8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $r2 = LDRSH $sp, $noreg, 16, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $r5 = LDRSH $sp, $noreg, 255, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $lr, $sp = frame-destroy LDR_POST_IMM $sp, $noreg, 8, 14 /* CC::al */, $noreg + ;CHECK: liveins: $r10, $r9, $r8, $r7, $d8, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9 + ;CHECK: $r1 = LDRSH $sp, $noreg, 0, 14 /* CC::al */, $noreg + ;CHECK-NEXT: $r2 = LDRSH $sp, $noreg, 8, 14 /* CC::al */, $noreg + ;CHECK-NEXT: $r5 = LDRSH $sp, $noreg, 247, 14 /* CC::al */, $noreg + ;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg diff --git a/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir b/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir index 5618444842448..f2cdaebdfa8ba 100644 --- a/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir +++ b/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir @@ -19,7 +19,7 @@ body: | bb.0: liveins: $r1 ;CHECK-LABEL: name: CheckAddrModeT2_i12 - ;CHECK: $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg + ;CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[SHARED:[0-9+]]] ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[I12:[0-9]+]] ;CHECK-NEXT: $r0 = t2LDRi12 $sp, 4088, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r1, 14, $noreg @@ -49,7 +49,7 @@ body: | bb.0: liveins: $r1 ;CHECK-LABEL: name: CheckAddrModeT2_i8 - ;CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg + ;CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[SHARED:[0-9+]]] ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[I8:[0-9]+]] ;CHECK-NEXT: t2STRHT $r0, $sp, 248, 14 /* CC::al */, $noreg $r0 = tMOVr $r1, 14, $noreg @@ -79,7 +79,7 @@ body: | bb.0: liveins: $r1 ;CHECK-LABEL: name: CheckAddrModeT2_i8s4 - ;CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg + ;CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[SHARED:[0-9+]]] ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[I8S4:[0-9]+]] ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 1020, 14 /* CC::al */, $noreg $r0 = tMOVr $r1, 14, $noreg @@ -109,7 +109,7 @@ body: | bb.0: liveins: $r1 ;CHECK-LABEL: name: CheckAddrModeT2_ldrex - ;CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg + ;CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[SHARED:[0-9+]]] ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[LDREX:[0-9]+]] ;CHECK-NEXT: $r1 = t2LDREX $sp, 254, 14 /* CC::al */, $noreg $r0 = tMOVr $r1, 14, $noreg @@ -144,8 +144,10 @@ body: | bb.0: liveins: $r0, $r1 ;CHECK-LABEL: name: CheckAddrModeT1_s - ;CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg - ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[T1_S:[0-9]+]] + ;CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[SHARED:[0-9+]]] + ;CHECK-NEXT: tSTRspi $r0, $sp, 0, 14 /* CC::al */, $noreg + ;CHECK-NEXT: tSTRspi $r0, $sp, 4, 14 /* CC::al */, $noreg + ;CHECK-NEXT: tSTRspi $r0, $sp, 253, 14 /* CC::al */, $noreg ;CHECK-NEXT: tSTRspi $r0, $sp, 254, 14 /* CC::al */, $noreg $r0 = tMOVr $r1, 14, $noreg tBL 14, $noreg, @foo, implicit-def dead $lr, implicit $sp @@ -181,51 +183,29 @@ body: | BX_RET 14, $noreg ;CHECK: name: OUTLINED_FUNCTION_[[LDREX]] - ;CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -8 - ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @foo, implicit-def dead $lr, implicit $sp - ;CHECK-NEXT: $r1 = t2LDREX $sp, 2, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $r1 = t2LDREX $sp, 10, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $r1 = t2LDREX $sp, 255, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg + ;CHECK: $r1 = t2LDREX $sp, 0, 14 /* CC::al */, $noreg + ;CHECK-NEXT: $r1 = t2LDREX $sp, 8, 14 /* CC::al */, $noreg + ;CHECK-NEXT: $r1 = t2LDREX $sp, 253, 14 /* CC::al */, $noreg + ;CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg ;CHECK: name: OUTLINED_FUNCTION_[[I8]] - ;CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -8 - ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @foo, implicit-def dead $lr, implicit $sp - ;CHECK-NEXT: t2STRHT $r0, $sp, 8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: t2STRHT $r0, $sp, 12, 14 /* CC::al */, $noreg - ;CHECK-NEXT: t2STRHT $r0, $sp, 255, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg + ;CHECK: t2STRHT $r0, $sp, 0, 14 /* CC::al */, $noreg + ;CHECK-NEXT: t2STRHT $r0, $sp, 4, 14 /* CC::al */, $noreg + ;CHECK-NEXT: t2STRHT $r0, $sp, 247, 14 /* CC::al */, $noreg + ;CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg ;CHECK: name: OUTLINED_FUNCTION_[[I8S4]] - ;CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -8 - ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @foo, implicit-def dead $lr, implicit $sp + ;CHECK: t2STRDi8 $r0, $r1, $sp, 0, 14 /* CC::al */, $noreg ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 16, 14 /* CC::al */, $noreg - ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 1020, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg + ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 1012, 14 /* CC::al */, $noreg + ;CHECK-NEXT: tBX_RET 14 /* CC::al */, $nore ;CHECK: name: OUTLINED_FUNCTION_[[I12]] - ;CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -8 - ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @foo, implicit-def dead $lr, implicit $sp - ;CHECK-NEXT: $r0 = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $r0 = t2LDRi12 $sp, 12, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $r0 = t2LDRi12 $sp, 4094, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg - - ;CHECK: name: OUTLINED_FUNCTION_[[T1_S]] - ;CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ;CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -8 - ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @foo, implicit-def dead $lr, implicit $sp - ;CHECK-NEXT: tSTRspi $r0, $sp, 2, 14 /* CC::al */, $noreg - ;CHECK-NEXT: tSTRspi $r0, $sp, 6, 14 /* CC::al */, $noreg - ;CHECK-NEXT: tSTRspi $r0, $sp, 255, 14 /* CC::al */, $noreg - ;CHECK-NEXT: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg + ;CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg + ;CHECK-NEXT: $r0 = t2LDRi12 $sp, 4, 14 /* CC::al */, $noreg + ;CHECK-NEXT: $r0 = t2LDRi12 $sp, 4086, 14 /* CC::al */, $noreg + ;CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg + + ;CHECK: name: OUTLINED_FUNCTION_[[SHARED]] + ;CHECK: $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg + ;CHECK-NEXT: tTAILJMPdND @foo, 14 /* CC::al */, $noreg, implicit $sp From 285cc63c710dffc0ebf17eaaa61d8e214ae57283 Mon Sep 17 00:00:00 2001 From: Xuan Zhang Date: Tue, 4 Jun 2024 06:04:56 -0700 Subject: [PATCH 2/4] fix comment in lit test --- llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll b/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll index 00efc3c6e71c8..09b02531d2a75 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll +++ b/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll @@ -25,7 +25,7 @@ ; - `SequenceSize=12` and `OccurrenceCount=4` ; - each Candidate has `CallOverhead=4` and `FrameOverhead=0` ; - `NotOutlinedCost=12*4=48` and `OutliningCost=4*4+12+0=28` -; - `Benefit=120-96=20` and `Priority=48/28=1.71` +; - `Benefit=48-28=20` and `Priority=48/28=1.71` ; ; Note that the first one has higher benefit, but lower priority. ; Hence, when outlining per priority, the second one will be outlined first. From 487a413e686959677bd42264fc384f7edc7d0e09 Mon Sep 17 00:00:00 2001 From: Xuan Zhang Date: Tue, 4 Jun 2024 13:59:05 -0700 Subject: [PATCH 3/4] add MIR test --- .../machine-outliner-sort-per-priority.mir | 206 ++++++++++++++++++ 1 file changed, 206 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.mir diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.mir b/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.mir new file mode 100644 index 0000000000000..0d4afeed72ab5 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.mir @@ -0,0 +1,206 @@ +# The content of this test is modfied upon the output obtained from running +# `bin/llc -O2 -stop-before=machine-outliner /llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll -o -` +# RUN: llc -mtriple=aarch64 -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s + +--- | + declare i32 @foo() + + define void @f1() #0 { ret void } + define void @f2() #0 { ret void } + define void @f3() #0 { ret void } + define void @f4() #0 { ret void } + define void @f5() #0 { ret void } + define void @f6() #0 { ret void } + + attributes #0 = { minsize } +... +--- +# CHECK-LABEL: name: f1 +# CHECK-LABEL: bb.0: +# CHECK-NEXT: liveins: $lr +# CHECK-NEXT: {{ $}} +# CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 +# CHECK-NEXT: $w5 = MOVZWi 11, 0 +# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0, 0, implicit $sp, implicit-def $w7, implicit-def $w6, implicit $sp, implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5 +name: f1 +tracksRegLiveness: true +frameInfo: + isCalleeSavedInfoValid: true +machineFunctionInfo: + hasRedZone: false +body: | + bb.0: + $w0 = MOVZWi 1, 0 + $w1 = MOVZWi 2, 0 + $w2 = MOVZWi 3, 0 + $w3 = MOVZWi 4, 0 + $w4 = MOVZWi 5, 0 + $w5 = MOVZWi 11, 0 + $w6 = MOVZWi 6, 0 + $w7 = MOVZWi 7, 0 + TCRETURNdi @foo, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $w2, implicit killed $w3, implicit killed $w4, implicit killed $w5, implicit killed $w6, implicit killed $w7 + +... +--- +# CHECK-LABEL: name: f2 +# CHECK-LABEL: bb.0: +# CHECK-NEXT: liveins: $lr +# CHECK-NEXT: {{ $}} +# CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 +# CHECK-NEXT: $w5 = MOVZWi 12, 0 +# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0, 0, implicit $sp, implicit-def $w7, implicit-def $w6, implicit $sp, implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5 +name: f2 +tracksRegLiveness: true +frameInfo: + isCalleeSavedInfoValid: true +machineFunctionInfo: + hasRedZone: false +body: | + bb.0: + $w0 = MOVZWi 1, 0 + $w1 = MOVZWi 2, 0 + $w2 = MOVZWi 3, 0 + $w3 = MOVZWi 4, 0 + $w4 = MOVZWi 5, 0 + $w5 = MOVZWi 12, 0 + $w6 = MOVZWi 6, 0 + $w7 = MOVZWi 7, 0 + TCRETURNdi @foo, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $w2, implicit killed $w3, implicit killed $w4, implicit killed $w5, implicit killed $w6, implicit killed $w7 + +... +--- +# CHECK-LABEL: name: f3 +# CHECK-LABEL: bb.0: +# CHECK-NEXT: liveins: $lr +# CHECK-NEXT: {{ $}} +# CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 +# CHECK-NEXT: $w5 = MOVZWi 13, 0 +# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0, 0, implicit $sp, implicit-def $w7, implicit-def $w6, implicit $sp, implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5 +name: f3 +tracksRegLiveness: true +frameInfo: + isCalleeSavedInfoValid: true +machineFunctionInfo: + hasRedZone: false +body: | + bb.0: + $w0 = MOVZWi 1, 0 + $w1 = MOVZWi 2, 0 + $w2 = MOVZWi 3, 0 + $w3 = MOVZWi 4, 0 + $w4 = MOVZWi 5, 0 + $w5 = MOVZWi 13, 0 + $w6 = MOVZWi 6, 0 + $w7 = MOVZWi 7, 0 + TCRETURNdi @foo, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $w2, implicit killed $w3, implicit killed $w4, implicit killed $w5, implicit killed $w6, implicit killed $w7 + +... +--- +# CHECK-LABEL: name: f4 +# CHECK-LABEL: bb.0: +# CHECK-NEXT: liveins: $lr +# CHECK-NEXT: {{ $}} +# CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 +# CHECK-NEXT: $w5 = MOVZWi 14, 0 +# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0, 0, implicit $sp, implicit-def $w7, implicit-def $w6, implicit $sp, implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5 +name: f4 +tracksRegLiveness: true +frameInfo: + isCalleeSavedInfoValid: true +machineFunctionInfo: + hasRedZone: false +body: | + bb.0: + $w0 = MOVZWi 1, 0 + $w1 = MOVZWi 2, 0 + $w2 = MOVZWi 3, 0 + $w3 = MOVZWi 4, 0 + $w4 = MOVZWi 5, 0 + $w5 = MOVZWi 14, 0 + $w6 = MOVZWi 6, 0 + $w7 = MOVZWi 7, 0 + TCRETURNdi @foo, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $w2, implicit killed $w3, implicit killed $w4, implicit killed $w5, implicit killed $w6, implicit killed $w7 + +... +--- +# CHECK-LABEL: name: f5 +# CHECK-LABEL: bb.0: +# CHECK-NEXT: liveins: $lr +# CHECK-NEXT: {{ $}} +# CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 +# CHECK-NO: @OUTLINED_FUNCTION_0 +name: f5 +tracksRegLiveness: true +frameInfo: + isCalleeSavedInfoValid: true +machineFunctionInfo: + hasRedZone: false +body: | + bb.0: + $w0 = MOVZWi 1, 0 + $w1 = MOVZWi 2, 0 + $w2 = MOVZWi 3, 0 + $w3 = MOVZWi 4, 0 + $w4 = MOVZWi 5, 0 + $w5 = MOVZWi 15, 0 + $w6 = MOVZWi 8, 0 + $w7 = MOVZWi 9, 0 + TCRETURNdi @foo, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $w2, implicit killed $w3, implicit killed $w4, implicit killed $w5, implicit killed $w6, implicit killed $w7 + +... +--- +# CHECK-LABEL: name: f6 +# CHECK-LABEL: bb.0: +# CHECK-NEXT: liveins: $lr +# CHECK-NEXT: {{ $}} +# CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 +# CHECK-NO: @OUTLINED_FUNCTION_0 +name: f6 +tracksRegLiveness: true +frameInfo: + isCalleeSavedInfoValid: true +machineFunctionInfo: + hasRedZone: false +body: | + bb.0: + $w0 = MOVZWi 1, 0 + $w1 = MOVZWi 2, 0 + $w2 = MOVZWi 3, 0 + $w3 = MOVZWi 4, 0 + $w4 = MOVZWi 5, 0 + $w5 = MOVZWi 16, 0 + $w6 = MOVZWi 9, 0 + $w7 = MOVZWi 8, 0 + TCRETURNdi @foo, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $w2, implicit killed $w3, implicit killed $w4, implicit killed $w5, implicit killed $w6, implicit killed $w7 + +... + +# CHECK-LABEL: name: OUTLINED_FUNCTION_0 +# CHECK-LABEL: bb.0: +# CHECK-NEXT: liveins: $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $lr, $d8, $d9, $d10, $d11, $d12, $d13, $d14, $d15, $w0, $w1, $w2, $w3, $w4, $w5 +# CHECK-NEXT: {{ $}} +# CHECK-NEXT: $w6 = MOVZWi 6, 0 +# CHECK-NEXT: $w7 = MOVZWi 7, 0 + +# CHECK-LABEL: name: OUTLINED_FUNCTION_1 +# CHECK-LABEL: bb.0: +# CHECK-NEXT: liveins: $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $lr, $d8, $d9, $d10, $d11, $d12, $d13, $d14, $d15 +# CHECK-NEXT: {{ $}} +# CHECK-NEXT: $w0 = MOVZWi 1, 0 +# CHECK-NEXT: $w1 = MOVZWi 2, 0 +# CHECK-NEXT: $w2 = MOVZWi 3, 0 +# CHECK-NEXT: $w3 = MOVZWi 4, 0 +# CHECK-NEXT: $w4 = MOVZWi 5, 0 +# CHECK-NEXT: RET $lr From 5e5299eeb1c964f58f6900f0220031fb077622fd Mon Sep 17 00:00:00 2001 From: Xuan Zhang Date: Wed, 5 Jun 2024 10:41:06 -0700 Subject: [PATCH 4/4] fix mir test --- .../machine-outliner-sort-per-priority.mir | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.mir b/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.mir index 0d4afeed72ab5..444590657a200 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.mir +++ b/llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.mir @@ -20,10 +20,10 @@ # CHECK-NEXT: liveins: $lr # CHECK-NEXT: {{ $}} # CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 -# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1 # CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 # CHECK-NEXT: $w5 = MOVZWi 11, 0 -# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0, 0, implicit $sp, implicit-def $w7, implicit-def $w6, implicit $sp, implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5 +# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0 name: f1 tracksRegLiveness: true frameInfo: @@ -49,10 +49,10 @@ body: | # CHECK-NEXT: liveins: $lr # CHECK-NEXT: {{ $}} # CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 -# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1 # CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 # CHECK-NEXT: $w5 = MOVZWi 12, 0 -# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0, 0, implicit $sp, implicit-def $w7, implicit-def $w6, implicit $sp, implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5 +# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0 name: f2 tracksRegLiveness: true frameInfo: @@ -78,10 +78,10 @@ body: | # CHECK-NEXT: liveins: $lr # CHECK-NEXT: {{ $}} # CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 -# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1 # CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 # CHECK-NEXT: $w5 = MOVZWi 13, 0 -# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0, 0, implicit $sp, implicit-def $w7, implicit-def $w6, implicit $sp, implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5 +# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0 name: f3 tracksRegLiveness: true frameInfo: @@ -107,10 +107,10 @@ body: | # CHECK-NEXT: liveins: $lr # CHECK-NEXT: {{ $}} # CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 -# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1 # CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 # CHECK-NEXT: $w5 = MOVZWi 14, 0 -# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0, 0, implicit $sp, implicit-def $w7, implicit-def $w6, implicit $sp, implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5 +# CHECK-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0 name: f4 tracksRegLiveness: true frameInfo: @@ -136,9 +136,9 @@ body: | # CHECK-NEXT: liveins: $lr # CHECK-NEXT: {{ $}} # CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 -# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1 # CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 -# CHECK-NO: @OUTLINED_FUNCTION_0 +# CHECK-NOT: @OUTLINED_FUNCTION_0 name: f5 tracksRegLiveness: true frameInfo: @@ -164,9 +164,9 @@ body: | # CHECK-NEXT: liveins: $lr # CHECK-NEXT: {{ $}} # CHECK-NEXT: $x5 = ORRXrs $xzr, $lr, 0 -# CHECK-NEXT: BL @OUTLINED_FUNCTION_1, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $w0, implicit-def $w1, implicit-def $w2, implicit-def $w3, implicit-def $w4, implicit $sp, implicit $xzr, implicit $x5 +# CHECK-NEXT: BL @OUTLINED_FUNCTION_1 # CHECK-NEXT: $lr = ORRXrs $xzr, $x5, 0 -# CHECK-NO: @OUTLINED_FUNCTION_0 +# CHECK-NOT: @OUTLINED_FUNCTION_0 name: f6 tracksRegLiveness: true frameInfo: