diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 8f50126f1b362..55673f3feb130 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -145,6 +145,7 @@ // CHECK-NOT: __riscv_zacas {{.*$}} // CHECK-NOT: __riscv_zalrsc {{.*$}} // CHECK-NOT: __riscv_zcmop {{.*$}} +// CHECK-NOT: __riscv_zalasr {{.*$}} // CHECK-NOT: __riscv_zfbfmin {{.*$}} // CHECK-NOT: __riscv_zicfilp {{.*$}} // CHECK-NOT: __riscv_zicfiss {{.*$}} @@ -1120,6 +1121,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s // CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zalasr1p0 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zalasr1p0 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s +// CHECK-ZALASR-EXT: __riscv_zalasr 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32izfa -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 2cfbb10abc8a1..1ac6f760fbad8 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -228,6 +228,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zacas`` LLVM implements the `1.0-rc1 draft specification `_. +``experimental-zalasr`` + LLVM implements the `most recent specification `_. + ``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma`` LLVM implements assembler support for the `1.0.0-rc2 specification `_. diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 32b4ff5de86f1..4c4eecde5da44 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -195,6 +195,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zaamo", {0, 2}}, {"zacas", {1, 0}}, {"zalrsc", {0, 2}}, + {"zalasr", {1, 0}}, {"zcmop", {0, 2}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index c822b9c9c6240..db1b6c95909f6 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -797,6 +797,13 @@ def FeatureStdExtSvpbmt : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true", "'Svpbmt' (Page-Based Memory Types)">; +def FeatureStdExtZalasr + : SubtargetFeature<"experimental-zalasr", "HasStdExtZalasr", "true", + "'Zalasr' (Load-Acquire and Store-Release Instructions)">; +def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">, + AssemblerPredicate<(all_of FeatureStdExtZalasr), + "'Zalasr' (Load-Acquire and Store-Release Instructions)">; + //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 9d49c22fdf215..df7d95d19b97b 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -20506,6 +20506,14 @@ unsigned RISCVTargetLowering::getCustomCtpopCost(EVT VT, return isCtpopFast(VT) ? 0 : 1; } +bool RISCVTargetLowering::shouldInsertFencesForAtomic( + const Instruction *I) const { + if (Subtarget.hasStdExtZalasr()) { + return false; + } + return isa(I) || isa(I); +} + bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const { // GISel support is in progress or complete for G_ADD, G_SUB, G_AND, G_OR, and diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 8d2fdbb9d40b4..9316cfe811ba2 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -689,9 +689,8 @@ class RISCVTargetLowering : public TargetLowering { bool preferZeroCompareBranch() const override { return true; } - bool shouldInsertFencesForAtomic(const Instruction *I) const override { - return isa(I) || isa(I); - } + bool shouldInsertFencesForAtomic(const Instruction *I) const override; + Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override; Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 114329c2c7c5f..8996ba3bc9f82 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2144,6 +2144,7 @@ include "RISCVInstrInfoM.td" // Atomic include "RISCVInstrInfoA.td" include "RISCVInstrInfoZa.td" +include "RISCVInstrInfoZalasr.td" // Scalar FP include "RISCVInstrInfoF.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td index 36842ceb49bfb..25bd4ed236b08 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -105,22 +105,63 @@ defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">, // Pseudo-instructions and codegen patterns //===----------------------------------------------------------------------===// +// An atomic load operation that does not need either acquire or release +// semantics. +class relaxed_load + : PatFrag<(ops node:$ptr), (base node:$ptr)> { + let IsAtomic = 1; + let IsAtomicOrderingMonotonic = 1; +} + +// A atomic load operation that actually needs acquire semantics. +class acquiring_load + : PatFrag<(ops node:$ptr), (base node:$ptr)> { + let IsAtomic = 1; + let IsAtomicOrderingAcquire = 1; +} + +// An atomic load operation that needs sequential consistency. +class seq_cst_load + : PatFrag<(ops node:$ptr), (base node:$ptr)> { + let IsAtomic = 1; + let IsAtomicOrderingSequentiallyConsistent = 1; +} + +// An atomic store operation that doesn't actually need to be atomic on RISCV. +class relaxed_store + : PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> { + let IsAtomic = 1; + let IsAtomicOrderingMonotonic = 1; +} + +// A store operation that actually needs release semantics. +class releasing_store + : PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> { + let IsAtomic = 1; + let IsAtomicOrderingRelease = 1; +} + +// A store operation that actually needs sequential consistency. +class seq_cst_store + : PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> { + let IsAtomic = 1; + let IsAtomicOrderingSequentiallyConsistent = 1; +} + // Atomic load/store are available under both +a and +force-atomics. -// Fences will be inserted for atomic load/stores according to the logic in -// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}. let Predicates = [HasAtomicLdSt] in { - def : LdPat; - def : LdPat; - def : LdPat; + def : LdPat, LB>; + def : LdPat, LH>; + def : LdPat, LW>; - def : StPat; - def : StPat; - def : StPat; + def : StPat, SB, GPR, XLenVT>; + def : StPat, SH, GPR, XLenVT>; + def : StPat, SW, GPR, XLenVT>; } let Predicates = [HasAtomicLdSt, IsRV64] in { - def : LdPat; - def : StPat; + def : LdPat, LD, i64>; + def : StPat, SD, GPR, i64>; } /// AMOs diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td new file mode 100644 index 0000000000000..b0acdf3d4a4b1 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td @@ -0,0 +1,98 @@ +//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions -------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the Zalasr (Load-Acquire +// and Store-Release) extension +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +class LAQ_r funct3, string opcodestr> + : RVInstRAtomic<0b00110, aq, rl, funct3, OPC_AMO, + (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1), + opcodestr, "$rd, $rs1"> { + let rs2 = 0; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +class SRL_r funct3, string opcodestr> + : RVInstRAtomic<0b00111, aq, rl, funct3, OPC_AMO, + (outs ), (ins GPRMemZeroOffset:$rs1, GPR:$rs2), + opcodestr, "$rs2, $rs1"> { + let rd = 0; +} +multiclass LAQ_r_aq_rl funct3, string opcodestr> { + def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">; + def _AQ_RL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">; +} + +multiclass SRL_r_aq_rl funct3, string opcodestr> { + def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">; + def _AQ_RL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">; +} + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + + +let Predicates = [HasStdExtZalasr] in { +defm LB_AQ : LAQ_r_aq_rl<0b000, "lb">; +defm LH_AQ : LAQ_r_aq_rl<0b001, "lh">; +defm LW_AQ : LAQ_r_aq_rl<0b010, "lw">; +defm SB_RL : SRL_r_aq_rl<0b000, "sb">; +defm SH_RL : SRL_r_aq_rl<0b001, "sh">; +defm SW_RL : SRL_r_aq_rl<0b010, "sw">; +} // Predicates = [HasStdExtZalasr] + +let Predicates = [HasStdExtZalasr, IsRV64] in { +defm LD_AQ : LAQ_r_aq_rl<0b011, "ld">; +defm SD_RL : SRL_r_aq_rl<0b011, "sd">; +} // Predicates = [HasStdExtZalasr, IsRV64] + +//===----------------------------------------------------------------------===// +// Pseudo-instructions and codegen patterns +//===----------------------------------------------------------------------===// + +class PatLAQ + : Pat<(vt (OpNode (vt GPRMemZeroOffset:$rs1))), (Inst GPRMemZeroOffset:$rs1)>; + +class PatSRL + : Pat<(OpNode (vt GPR:$rs2), (vt GPRMemZeroOffset:$rs1)), (Inst GPR:$rs2, GPRMemZeroOffset:$rs1)>; + +let Predicates = [HasStdExtZalasr] in { + def : PatLAQ, LB_AQ_AQ>; + def : PatLAQ, LB_AQ_AQ>; // these use lb.aq instead of lb.aqrl to match the psABI + + def : PatLAQ, LH_AQ_AQ>; + def : PatLAQ, LH_AQ_AQ>; + + def : PatLAQ, LW_AQ_AQ>; + def : PatLAQ, LW_AQ_AQ>; + + def : PatSRL, SB_RL_RL>; + def : PatSRL, SB_RL_RL>; // these use sb.rl instead of sb.aqrl to match the psABI + + def : PatSRL, SH_RL_RL>; + def : PatSRL, SH_RL_RL>; + + def : PatSRL, SW_RL_RL>; + def : PatSRL, SW_RL_RL>; +} // Predicates HasStdExtZalasr + +let Predicates = [HasStdExtZalasr, IsRV64] in { + def : PatLAQ, LD_AQ_AQ>; + def : PatLAQ, LD_AQ_AQ>; + + def : PatSRL, SD_RL_RL>; + def : PatSRL, SD_RL_RL>; +} // Predicates HasStdExtZalasr, IsRV64 diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index ed1ab5a74f5c4..e1b47d964c73a 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -97,6 +97,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s @@ -201,6 +202,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV64ZALRSC %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s ; CHECK: .attribute 4, 16 @@ -300,6 +302,7 @@ ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0" ; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc0p2" ; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4" +; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr1p0" ; RV64M: .attribute 5, "rv64i2p1_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" @@ -403,6 +406,7 @@ ; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0" ; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc0p2" ; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4" +; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr1p0" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 5f9a7cabcc768..4d3c224f9e37d 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -309,6 +309,9 @@ .attribute arch, "rv32izacas1p0" # CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0" +.attribute arch, "rv32izalasr1p0" +# CHECK: attribute 5, "rv32i2p1_zalasr1p0" + .attribute arch, "rv32i_xcvalu" # CHECK: attribute 5, "rv32i2p1_xcvalu1p0" diff --git a/llvm/test/MC/RISCV/rv32zalasr-invalid.s b/llvm/test/MC/RISCV/rv32zalasr-invalid.s new file mode 100644 index 0000000000000..3731c85cbc077 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zalasr-invalid.s @@ -0,0 +1,40 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s + +# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}} +ld.aq a1, (t0) + +# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}} +ld.aqrl a1, (t0) + +# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}} +sd.rl a1, (t0) + +# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}} +sd.aqrl a1, (t0) + +# CHECK: error: unrecognized instruction mnemonic +lw. a1, (t0) + +# CHECK: error: unrecognized instruction mnemonic +lw.rl t3, 0(t5) + +# CHECK: error: unrecognized instruction mnemonic +lh.rlaq t4, (t6) + +# CHECK: error: unrecognized instruction mnemonic +sb. a1, (t0) + +# CHECK: error: unrecognized instruction mnemonic +sh.aq t3, 0(t5) + +# CHECK: error: unrecognized instruction mnemonic +sh.rlaq t4, (t6) + +# CHECK: error: optional integer offset must be 0 +lw.aq zero, 1(a0) + +# CHECK: error: optional integer offset must be 0 +sw.rl t1, 2(s0) + +# CHECK: error: optional integer offset must be 0 +sb.aqrl sp, 3(s2) diff --git a/llvm/test/MC/RISCV/rv32zalasr-valid.s b/llvm/test/MC/RISCV/rv32zalasr-valid.s new file mode 100644 index 0000000000000..fb85fbc00dfea --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zalasr-valid.s @@ -0,0 +1,70 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zalasr < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 \ +# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s + +# CHECK-ASM-AND-OBJ: lb.aq t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x34] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lb.aq t1, 0(a0) + +# CHECK-ASM-AND-OBJ: lh.aq t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x34] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lh.aq t1, 0(a0) + +# CHECK-ASM-AND-OBJ: lw.aq t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x34] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lw.aq t1, (a0) + +# CHECK-ASM-AND-OBJ: lb.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x36] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lb.aqrl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: lh.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x36] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lh.aqrl t1, (a0) + +# CHECK-ASM-AND-OBJ: lw.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x36] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lw.aqrl t1, (a0) + + +# CHECK-ASM-AND-OBJ: sb.rl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sb.rl t1, (a0) + +# CHECK-ASM-AND-OBJ: sh.rl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sh.rl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: sw.rl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sw.rl t1, (a0) + +# CHECK-ASM-AND-OBJ: sb.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sb.aqrl t1, (a0) + +# CHECK-ASM-AND-OBJ: sh.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sh.aqrl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: sw.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sw.aqrl t1, 0(a0) diff --git a/llvm/test/MC/RISCV/rv64zalasr-invalid.s b/llvm/test/MC/RISCV/rv64zalasr-invalid.s new file mode 100644 index 0000000000000..032c0c00882cb --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zalasr-invalid.s @@ -0,0 +1,28 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s + +# CHECK: error: unrecognized instruction mnemonic +lw. a1, (t0) + +# CHECK: error: unrecognized instruction mnemonic +lw.rl t3, 0(t5) + +# CHECK: error: unrecognized instruction mnemonic +lh.rlaq t4, (t6) + +# CHECK: error: unrecognized instruction mnemonic +sb. a1, (t0) + +# CHECK: error: unrecognized instruction mnemonic +sh.aq t3, 0(t5) + +# CHECK: error: unrecognized instruction mnemonic +sh.rlaq t4, (t6) + +# CHECK: error: optional integer offset must be 0 +lw.aq zero, 1(a0) + +# CHECK: error: optional integer offset must be 0 +sw.rl t1, 2(s0) + +# CHECK: error: optional integer offset must be 0 +sb.aqrl sp, 3(s2) diff --git a/llvm/test/MC/RISCV/rv64zalasr-valid.s b/llvm/test/MC/RISCV/rv64zalasr-valid.s new file mode 100644 index 0000000000000..9e623ccaaaf88 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zalasr-valid.s @@ -0,0 +1,91 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalasr < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv64 \ +# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s + + +# CHECK-ASM-AND-OBJ: lb.aq t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x34] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lb.aq t1, 0(a0) + +# CHECK-ASM-AND-OBJ: lh.aq t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x34] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lh.aq t1, 0(a0) + +# CHECK-ASM-AND-OBJ: lw.aq t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x34] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lw.aq t1, (a0) + +# CHECK-ASM-AND-OBJ: ld.aq t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x33,0x05,0x34] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +ld.aq t1, (a0) + +# CHECK-ASM-AND-OBJ: lb.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x36] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lb.aqrl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: lh.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x36] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lh.aqrl t1, (a0) + +# CHECK-ASM-AND-OBJ: lw.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x36] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lw.aqrl t1, (a0) + +# CHECK-ASM-AND-OBJ: ld.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x33,0x05,0x36] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +ld.aqrl t1, 0(a0) + + +# CHECK-ASM-AND-OBJ: sb.rl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sb.rl t1, (a0) + +# CHECK-ASM-AND-OBJ: sh.rl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sh.rl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: sw.rl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sw.rl t1, (a0) + +# CHECK-ASM-AND-OBJ: sd.rl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x30,0x65,0x3a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sd.rl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: sb.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sb.aqrl t1, (a0) + +# CHECK-ASM-AND-OBJ: sh.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sh.aqrl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: sw.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sw.aqrl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: sd.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x30,0x65,0x3e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sd.aqrl t1, (a0) diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index a595526dd24a9..fba5413df24a2 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -800,6 +800,7 @@ Experimental extensions zalrsc 0.2 zfbfmin 1.0 zcmop 0.2 + zalasr 1.0 ztso 0.1 zvfbfmin 1.0 zvfbfwma 1.0