diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h index ed9fc8f7ec3d7..6157f446d5f96 100644 --- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h +++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h @@ -688,12 +688,15 @@ class MachineBasicBlock } /// Update the terminator instructions in block to account for changes to - /// block layout which may have been made. PreviousLayoutSuccessor should be - /// set to the block which may have been used as fallthrough before the block - /// layout was modified. If the block previously fell through to that block, - /// it may now need a branch. If it previously branched to another block, it - /// may now be able to fallthrough to the current layout successor. - void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor); + /// block layout which may have been made. \p PreviousLayoutSuccessor should + /// be set to the block which may have been used as fallthrough before the + /// block layout was modified. If the block previously fell through to that + /// block, it may now need a branch. If it previously branched to another + /// block, it may now be able to fallthrough to the current layout successor. + /// SlotIndexes provided by \p Indexes will be updated to reflect any + /// instructions inserted or removed. + void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor, + SlotIndexes *Indexes = nullptr); // Machine-CFG mutators diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h index 1c2ca86783464..5e902b8385b41 100644 --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -53,6 +53,7 @@ class ScheduleDAGMI; class ScheduleHazardRecognizer; class SDNode; class SelectionDAG; +class SlotIndexes; class SMSchedule; class SwingSchedulerDAG; class RegScavenger; @@ -679,9 +680,12 @@ class TargetInstrInfo : public MCInstrInfo { /// Remove the branching code at the end of the specific MBB. /// This is only invoked in cases where analyzeBranch returns success. It /// returns the number of instructions that were removed. + /// If \p Indexes is non-null, then instructions will also be removed from + /// SlotIndexes. /// If \p BytesRemoved is non-null, report the change in code size from the /// removed instructions. virtual unsigned removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const { llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!"); } @@ -689,8 +693,11 @@ class TargetInstrInfo : public MCInstrInfo { /// Insert branch code into the end of the specified MachineBasicBlock. The /// operands to this method are the same as those returned by analyzeBranch. /// This is only invoked in cases where analyzeBranch returns success. It - /// returns the number of instructions inserted. If \p BytesAdded is non-null, - /// report the change in code size from the added instructions. + /// returns the number of instructions inserted. + /// If \p Indexes is non-null, then added instructions will be inserted into + /// SlotIndexes. + /// If \p BytesAdded is non-null, report the change in code size from the + /// added instructions. /// /// It is also invoked by tail merging to add unconditional branches in /// cases where analyzeBranch doesn't apply because there was no original @@ -703,6 +710,7 @@ class TargetInstrInfo : public MCInstrInfo { MachineBasicBlock *FBB, ArrayRef Cond, const DebugLoc &DL, + SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const { llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!"); } @@ -710,9 +718,10 @@ class TargetInstrInfo : public MCInstrInfo { unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, + SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const { return insertBranch(MBB, DestBB, nullptr, ArrayRef(), DL, - BytesAdded); + Indexes, BytesAdded); } /// Object returned by analyzeLoopForPipelining. Allows software pipelining diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp index f50eb5e1730a3..e87d35633eea1 100644 --- a/llvm/lib/CodeGen/BranchRelaxation.cpp +++ b/llvm/lib/CodeGen/BranchRelaxation.cpp @@ -364,7 +364,8 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) { MachineBasicBlock *DestBB) { unsigned &BBSize = BlockInfo[MBB->getNumber()].Size; int NewBrSize = 0; - TII->insertUnconditionalBranch(*MBB, DestBB, DL, &NewBrSize); + TII->insertUnconditionalBranch(*MBB, DestBB, DL, /*Indexes=*/nullptr, + &NewBrSize); BBSize += NewBrSize; }; auto insertBranch = [&](MachineBasicBlock *MBB, MachineBasicBlock *TBB, @@ -372,13 +373,14 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) { SmallVectorImpl& Cond) { unsigned &BBSize = BlockInfo[MBB->getNumber()].Size; int NewBrSize = 0; - TII->insertBranch(*MBB, TBB, FBB, Cond, DL, &NewBrSize); + TII->insertBranch(*MBB, TBB, FBB, Cond, DL, /*Indexes=*/nullptr, + &NewBrSize); BBSize += NewBrSize; }; auto removeBranch = [&](MachineBasicBlock *MBB) { unsigned &BBSize = BlockInfo[MBB->getNumber()].Size; int RemovedSize = 0; - TII->removeBranch(*MBB, &RemovedSize); + TII->removeBranch(*MBB, /*Indexes=*/nullptr, &RemovedSize); BBSize -= RemovedSize; }; diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index 280ced65db7d8..45b1a008ad7d2 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -681,7 +681,7 @@ static int findJumpTableIndex(const MachineBasicBlock &MBB) { } void MachineBasicBlock::updateTerminator( - MachineBasicBlock *PreviousLayoutSuccessor) { + MachineBasicBlock *PreviousLayoutSuccessor, SlotIndexes *Indexes) { LLVM_DEBUG(dbgs() << "Updating terminators on " << printMBBReference(*this) << "\n"); @@ -693,7 +693,7 @@ void MachineBasicBlock::updateTerminator( MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; DebugLoc DL = findBranchDebugLoc(); - bool B = TII->analyzeBranch(*this, TBB, FBB, Cond); + bool B = TII->analyzeBranch(*this, TBB, FBB, Cond, /*AllowModify=*/false); (void) B; assert(!B && "UpdateTerminators requires analyzable predecessors!"); if (Cond.empty()) { @@ -701,7 +701,7 @@ void MachineBasicBlock::updateTerminator( // The block has an unconditional branch. If its successor is now its // layout successor, delete the branch. if (isLayoutSuccessor(TBB)) - TII->removeBranch(*this); + TII->removeBranch(*this, Indexes); } else { // The block has an unconditional fallthrough, or the end of the block is // unreachable. @@ -717,7 +717,8 @@ void MachineBasicBlock::updateTerminator( // If the unconditional successor block is not the current layout // successor, insert a branch to jump to it. if (!isLayoutSuccessor(PreviousLayoutSuccessor)) - TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL); + TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL, + Indexes); } return; } @@ -729,11 +730,11 @@ void MachineBasicBlock::updateTerminator( if (isLayoutSuccessor(TBB)) { if (TII->reverseBranchCondition(Cond)) return; - TII->removeBranch(*this); - TII->insertBranch(*this, FBB, nullptr, Cond, DL); + TII->removeBranch(*this, Indexes); + TII->insertBranch(*this, FBB, nullptr, Cond, DL, Indexes); } else if (isLayoutSuccessor(FBB)) { - TII->removeBranch(*this); - TII->insertBranch(*this, TBB, nullptr, Cond, DL); + TII->removeBranch(*this, Indexes); + TII->insertBranch(*this, TBB, nullptr, Cond, DL, Indexes); } return; } @@ -747,10 +748,10 @@ void MachineBasicBlock::updateTerminator( // We had a fallthrough to the same basic block as the conditional jump // targets. Remove the conditional jump, leaving an unconditional // fallthrough or an unconditional jump. - TII->removeBranch(*this); + TII->removeBranch(*this, Indexes); if (!isLayoutSuccessor(TBB)) { Cond.clear(); - TII->insertBranch(*this, TBB, nullptr, Cond, DL); + TII->insertBranch(*this, TBB, nullptr, Cond, DL, Indexes); } return; } @@ -760,14 +761,16 @@ void MachineBasicBlock::updateTerminator( if (TII->reverseBranchCondition(Cond)) { // We can't reverse the condition, add an unconditional branch. Cond.clear(); - TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL); + TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL, + Indexes); return; } - TII->removeBranch(*this); - TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL); + TII->removeBranch(*this, Indexes); + TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL, + Indexes); } else if (!isLayoutSuccessor(PreviousLayoutSuccessor)) { - TII->removeBranch(*this); - TII->insertBranch(*this, TBB, PreviousLayoutSuccessor, Cond, DL); + TII->removeBranch(*this, Indexes); + TII->insertBranch(*this, TBB, PreviousLayoutSuccessor, Cond, DL, Indexes); } } @@ -1166,51 +1169,20 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge( ReplaceUsesOfBlockWith(Succ, NMBB); - // If updateTerminator() removes instructions, we need to remove them from - // SlotIndexes. - SmallVector Terminators; - if (Indexes) { - for (MachineInstr &MI : - llvm::make_range(getFirstInstrTerminator(), instr_end())) - Terminators.push_back(&MI); - } - // Since we replaced all uses of Succ with NMBB, that should also be treated // as the fallthrough successor if (Succ == PrevFallthrough) PrevFallthrough = NMBB; if (!ChangedIndirectJump) - updateTerminator(PrevFallthrough); - - if (Indexes) { - SmallVector NewTerminators; - for (MachineInstr &MI : - llvm::make_range(getFirstInstrTerminator(), instr_end())) - NewTerminators.push_back(&MI); - - for (MachineInstr *Terminator : Terminators) { - if (!is_contained(NewTerminators, Terminator)) - Indexes->removeMachineInstrFromMaps(*Terminator); - } - } + updateTerminator(PrevFallthrough, Indexes); // Insert unconditional "jump Succ" instruction in NMBB if necessary. NMBB->addSuccessor(Succ); if (!NMBB->isLayoutSuccessor(Succ)) { SmallVector Cond; const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo(); - TII->insertBranch(*NMBB, Succ, nullptr, Cond, DL); - - if (Indexes) { - for (MachineInstr &MI : NMBB->instrs()) { - // Some instructions may have been moved to NMBB by updateTerminator(), - // so we first remove any instruction that already has an index. - if (Indexes->hasIndex(MI)) - Indexes->removeMachineInstrFromMaps(MI); - Indexes->insertMachineInstrInMaps(MI); - } - } + TII->insertBranch(*NMBB, Succ, nullptr, Cond, DL, Indexes); } // Fix PHI nodes in Succ so they refer to NMBB instead of this. diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index a41ac0e44a770..fcd470d7b6d90 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -10,8 +10,8 @@ // //===----------------------------------------------------------------------===// -#include "AArch64ExpandImm.h" #include "AArch64InstrInfo.h" +#include "AArch64ExpandImm.h" #include "AArch64FrameLowering.h" #include "AArch64MachineFunctionInfo.h" #include "AArch64Subtarget.h" @@ -31,6 +31,7 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/StackMaps.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" @@ -534,6 +535,7 @@ bool AArch64InstrInfo::reverseBranchCondition( } unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); if (I == MBB.end()) @@ -544,6 +546,8 @@ unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB, return 0; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); @@ -561,6 +565,8 @@ unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB, } // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); if (BytesRemoved) *BytesRemoved = 8; @@ -568,12 +574,18 @@ unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB, return 2; } -void AArch64InstrInfo::instantiateCondBranch( - MachineBasicBlock &MBB, const DebugLoc &DL, MachineBasicBlock *TBB, - ArrayRef Cond) const { +void AArch64InstrInfo::instantiateCondBranch(MachineBasicBlock &MBB, + const DebugLoc &DL, + MachineBasicBlock *TBB, + ArrayRef Cond, + SlotIndexes *Indexes) const { if (Cond[0].getImm() != -1) { // Regular Bcc - BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(AArch64::Bcc)) + .addImm(Cond[0].getImm()) + .addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); } else { // Folded compare-and-branch // Note that we use addOperand instead of addReg to keep the flags. @@ -582,20 +594,25 @@ void AArch64InstrInfo::instantiateCondBranch( if (Cond.size() > 3) MIB.addImm(Cond[3].getImm()); MIB.addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MIB); } } unsigned AArch64InstrInfo::insertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { + ArrayRef Cond, const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "insertBranch must not be told to insert a fallthrough"); if (!FBB) { - if (Cond.empty()) // Unconditional branch? - BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB); - else - instantiateCondBranch(MBB, DL, TBB, Cond); + if (Cond.empty()) { // Unconditional branch? + MachineInstr *MI = BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); + } else + instantiateCondBranch(MBB, DL, TBB, Cond, Indexes); if (BytesAdded) *BytesAdded = 4; @@ -604,8 +621,11 @@ unsigned AArch64InstrInfo::insertBranch( } // Two-way conditional branch. - instantiateCondBranch(MBB, DL, TBB, Cond); - BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB); + instantiateCondBranch(MBB, DL, TBB, Cond, Indexes); + MachineInstr *MI = BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB); + + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); if (BytesAdded) *BytesAdded = 8; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index 24ff676218cbe..ba42a1eb10793 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -225,11 +225,11 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo { bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; bool reverseBranchCondition(SmallVectorImpl &Cond) const override; @@ -378,7 +378,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo { void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL, MachineBasicBlock *TBB, - ArrayRef Cond) const; + ArrayRef Cond, + SlotIndexes *Indexes) const; bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg, const MachineRegisterInfo &MRI) const; bool removeCmpToZeroOrOne(MachineInstr &CmpInstr, unsigned SrcReg, diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp index 7f874b245b8f4..7d34187860537 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -19,6 +19,7 @@ #include "R600Subtarget.h" #include "llvm/ADT/SmallSet.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" using namespace llvm; @@ -730,14 +731,16 @@ unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes, int *BytesAdded) const { assert(TBB && "insertBranch must not be told to insert a fallthrough"); assert(!BytesAdded && "code size not handled"); if (!FBB) { if (Cond.empty()) { - BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } else { MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end()); @@ -745,9 +748,11 @@ unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB, addFlag(*PredSet, 0, MO_FLAG_PUSH); PredSet->getOperand(2).setImm(Cond[1].getImm()); - BuildMI(&MBB, DL, get(R600::JUMP_COND)) - .addMBB(TBB) - .addReg(R600::PREDICATE_BIT, RegState::Kill); + MachineInstr *MI = BuildMI(&MBB, DL, get(R600::JUMP_COND)) + .addMBB(TBB) + .addReg(R600::PREDICATE_BIT, RegState::Kill); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB); if (CfAlu == MBB.end()) return 1; @@ -760,10 +765,14 @@ unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB, assert(PredSet && "No previous predicate !"); addFlag(*PredSet, 0, MO_FLAG_PUSH); PredSet->getOperand(2).setImm(Cond[1].getImm()); - BuildMI(&MBB, DL, get(R600::JUMP_COND)) - .addMBB(TBB) - .addReg(R600::PREDICATE_BIT, RegState::Kill); - BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(FBB); + MachineInstr *CondBr = BuildMI(&MBB, DL, get(R600::JUMP_COND)) + .addMBB(TBB) + .addReg(R600::PREDICATE_BIT, RegState::Kill); + MachineInstr *UncondBr = BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(FBB); + if (Indexes) { + Indexes->insertMachineInstrInMaps(*CondBr); + Indexes->insertMachineInstrInMaps(*UncondBr); + } MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB); if (CfAlu == MBB.end()) return 2; @@ -774,6 +783,7 @@ unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB, } unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -792,6 +802,8 @@ unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB, case R600::JUMP_COND: { MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I); clearFlag(*predSet, 0, MO_FLAG_PUSH); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB); if (CfAlu == MBB.end()) @@ -801,6 +813,8 @@ unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB, break; } case R600::JUMP: + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); break; } @@ -817,6 +831,8 @@ unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB, case R600::JUMP_COND: { MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I); clearFlag(*predSet, 0, MO_FLAG_PUSH); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB); if (CfAlu == MBB.end()) @@ -826,6 +842,8 @@ unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB, break; } case R600::JUMP: + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); break; } diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h index f720e4656348c..bc9f19d32d068 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h @@ -170,10 +170,10 @@ class R600InstrInfo final : public R600GenInstrInfo { unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; bool isPredicated(const MachineInstr &MI) const override; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 38b5e0114903c..3ff192bc79ec8 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2843,7 +2843,7 @@ bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, return analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify); } -unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB, +unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes, int *BytesRemoved) const { unsigned Count = 0; unsigned RemovedSize = 0; @@ -2851,6 +2851,8 @@ unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB, // Skip over artificial terminators when removing instructions. if (MI.isBranch() || MI.isReturn()) { RemovedSize += getInstSizeInBytes(MI); + if (Indexes) + Indexes->removeMachineInstrFromMaps(MI); MI.eraseFromParent(); ++Count; } @@ -2873,21 +2875,26 @@ unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes, int *BytesAdded) const { if (!FBB && Cond.empty()) { - BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)) - .addMBB(TBB); + MachineInstr *UncondBr = + BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)).addMBB(TBB); if (BytesAdded) *BytesAdded = ST.hasOffset3fBug() ? 8 : 4; + if (Indexes) + Indexes->insertMachineInstrInMaps(*UncondBr); return 1; } - if(Cond.size() == 1 && Cond[0].isReg()) { - BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO)) - .add(Cond[0]) - .addMBB(TBB); - return 1; + if (Cond.size() == 1 && Cond[0].isReg()) { + MachineInstr *UncondBr = + BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO)) + .add(Cond[0]) + .addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*UncondBr); + return 1; } assert(TBB && Cond[0].isImm()); @@ -2899,6 +2906,8 @@ unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineInstr *CondBr = BuildMI(&MBB, DL, get(Opcode)) .addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*CondBr); // Copy the flags onto the implicit condition register operand. preserveCondRegFlags(CondBr->getOperand(1), Cond[1]); @@ -2911,12 +2920,9 @@ unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB, assert(TBB && FBB); - MachineInstr *CondBr = - BuildMI(&MBB, DL, get(Opcode)) - .addMBB(TBB); + MachineInstr *CondBr = BuildMI(&MBB, DL, get(Opcode)).addMBB(TBB); fixImplicitOperands(*CondBr); - BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)) - .addMBB(FBB); + MachineInstr *UncondBr = BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)).addMBB(FBB); MachineOperand &CondReg = CondBr->getOperand(1); CondReg.setIsUndef(Cond[1].isUndef()); @@ -2924,6 +2930,10 @@ unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB, if (BytesAdded) *BytesAdded = ST.hasOffset3fBug() ? 16 : 8; + if (Indexes) { + Indexes->insertMachineInstrInMaps(*CondBr); + Indexes->insertMachineInstrInMaps(*UncondBr); + } return 2; } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index e85917a4c0f32..4915a5777e879 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -331,12 +331,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo { SmallVectorImpl &Cond, bool AllowModify = false) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; bool reverseBranchCondition( diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp index fe78a98837cf9..202a14efa49ba 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp +++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp @@ -18,6 +18,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Debug.h" @@ -252,6 +253,7 @@ bool ARCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "Code size not handled"); MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); @@ -263,6 +265,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB, return 0; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); @@ -274,6 +278,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB, return 1; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); return 2; } @@ -370,7 +376,8 @@ unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, int *BytesAdded) const { + const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { assert(!BytesAdded && "Code size not handled."); // Shouldn't be a fall through. @@ -379,7 +386,9 @@ unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB, "ARC branch conditions have two components!"); if (Cond.empty()) { - BuildMI(&MBB, DL, get(ARC::BR)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(ARC::BR)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } int BccOpc = Cond[1].isImm() ? ARC::BRcc_ru6_p : ARC::BRcc_rr_p; @@ -388,6 +397,8 @@ unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB, for (unsigned i = 0; i < 3; i++) { MIB.add(Cond[i]); } + if (Indexes) + Indexes->insertMachineInstrInMaps(*MIB); // One-way conditional branch. if (!FBB) { @@ -395,7 +406,9 @@ unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB, } // Two-way conditional branch. - BuildMI(&MBB, DL, get(ARC::BR)).addMBB(FBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(ARC::BR)).addMBB(FBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 2; } diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.h b/llvm/lib/Target/ARC/ARCInstrInfo.h index c55c9535ec296..f176894367ba0 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.h +++ b/llvm/lib/Target/ARC/ARCInstrInfo.h @@ -57,10 +57,10 @@ class ARCInstrInfo : public ARCGenInstrInfo { unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &, + const DebugLoc &, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 1ffdde0360cf6..82a0dc43689b1 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -469,6 +469,7 @@ bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -481,6 +482,8 @@ unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB, return 0; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); @@ -491,16 +494,16 @@ unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB, return 1; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); return 2; } -unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB, - MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - ArrayRef Cond, - const DebugLoc &DL, - int *BytesAdded) const { +unsigned ARMBaseInstrInfo::insertBranch( + MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, + ArrayRef Cond, const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { assert(!BytesAdded && "code size not handled"); ARMFunctionInfo *AFI = MBB.getParent()->getInfo(); int BOpc = !AFI->isThumbFunction() @@ -517,33 +520,44 @@ unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB, // For conditional branches, we use addOperand to preserve CPSR flags. if (!FBB) { + MachineInstr *MI; if (Cond.empty()) { // Unconditional branch? if (isThumb) - BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL)); + MI = BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL)); else - BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); + MI = BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); } else if (Cond.size() == 2) { - BuildMI(&MBB, DL, get(BccOpc)) - .addMBB(TBB) - .addImm(Cond[0].getImm()) - .add(Cond[1]); + MI = BuildMI(&MBB, DL, get(BccOpc)) + .addMBB(TBB) + .addImm(Cond[0].getImm()) + .add(Cond[1]); } else - BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB); + MI = BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } // Two-way conditional branch. + MachineInstr *CondBr, *UncondBr; if (Cond.size() == 2) - BuildMI(&MBB, DL, get(BccOpc)) - .addMBB(TBB) - .addImm(Cond[0].getImm()) - .add(Cond[1]); + CondBr = BuildMI(&MBB, DL, get(BccOpc)) + .addMBB(TBB) + .addImm(Cond[0].getImm()) + .add(Cond[1]); else if (Cond.size() == 3) - BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB); + CondBr = BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB); + if (isThumb) - BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL)); + UncondBr = BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL)); else - BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); + UncondBr = BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); + + if (Indexes) { + Indexes->insertMachineInstrInMaps(*CondBr); + Indexes->insertMachineInstrInMaps(*UncondBr); + } + return 2; } diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index 5efcc1a0d9fc0..fa15af35f745f 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -143,11 +143,11 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo { MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify = false) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; bool diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp index b9d27c78ce8e4..3f8802324c181 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp +++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp @@ -17,6 +17,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Function.h" #include "llvm/MC/MCContext.h" @@ -399,7 +400,8 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, int *BytesAdded) const { + const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { if (BytesAdded) *BytesAdded = 0; @@ -413,6 +415,8 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB, auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB); if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI); + if (Indexes) + Indexes->insertMachineInstrInMaps(MI); return 1; } @@ -423,6 +427,8 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB, if (BytesAdded) *BytesAdded += getInstSizeInBytes(CondMI); + if (Indexes) + Indexes->insertMachineInstrInMaps(CondMI); ++Count; if (FBB) { @@ -430,6 +436,8 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB, auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB); if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI); + if (Indexes) + Indexes->insertMachineInstrInMaps(MI); ++Count; } @@ -437,6 +445,7 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB, } unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { if (BytesRemoved) *BytesRemoved = 0; @@ -459,6 +468,8 @@ unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB, // Remove the branch. if (BytesRemoved) *BytesRemoved += getInstSizeInBytes(*I); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); ++Count; diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.h b/llvm/lib/Target/AVR/AVRInstrInfo.h index 290177f5eec66..50d41b9ac346f 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.h +++ b/llvm/lib/Target/AVR/AVRInstrInfo.h @@ -99,9 +99,9 @@ class AVRInstrInfo : public AVRGenInstrInfo { bool AllowModify = false) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; bool reverseBranchCondition(SmallVectorImpl &Cond) const override; diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp index 2209f1f1462b4..31619e40b6214 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp +++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp @@ -15,6 +15,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/IR/DebugLoc.h" #include "llvm/Support/ErrorHandling.h" #include @@ -221,7 +222,7 @@ unsigned BPFInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes, int *BytesAdded) const { assert(!BytesAdded && "code size not handled"); @@ -231,7 +232,9 @@ unsigned BPFInstrInfo::insertBranch(MachineBasicBlock &MBB, if (Cond.empty()) { // Unconditional branch assert(!FBB && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, DL, get(BPF::JMP)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(BPF::JMP)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } @@ -239,6 +242,7 @@ unsigned BPFInstrInfo::insertBranch(MachineBasicBlock &MBB, } unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -252,6 +256,8 @@ unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB, if (I->getOpcode() != BPF::JMP) break; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); ++Count; diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.h b/llvm/lib/Target/BPF/BPFInstrInfo.h index 354aca1bd2f93..34be9799bff95 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.h +++ b/llvm/lib/Target/BPF/BPFInstrInfo.h @@ -52,12 +52,13 @@ class BPFInstrInfo : public BPFGenInstrInfo { SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; + private: void expandMEMCPY(MachineBasicBlock::iterator) const; diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp index e5581bcdc3975..679efeb4c73d1 100644 --- a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp +++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp @@ -15,6 +15,7 @@ #include "CSKYMachineFunctionInfo.h" #include "CSKYTargetMachine.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/MC/MCContext.h" #define DEBUG_TYPE "csky-instr-info" @@ -111,6 +112,7 @@ bool CSKYInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { if (BytesRemoved) *BytesRemoved = 0; @@ -125,6 +127,8 @@ unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB, // Remove the branch. if (BytesRemoved) *BytesRemoved += getInstSizeInBytes(*I); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); @@ -138,6 +142,8 @@ unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB, // Remove the branch. if (BytesRemoved) *BytesRemoved += getInstSizeInBytes(*I); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); return 2; } @@ -151,9 +157,12 @@ CSKYInstrInfo::getBranchDestBlock(const MachineInstr &MI) const { return MI.getOperand(NumOp - 1).getMBB(); } -unsigned CSKYInstrInfo::insertBranch( - MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { +unsigned CSKYInstrInfo::insertBranch(MachineBasicBlock &MBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + ArrayRef Cond, + const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { if (BytesAdded) *BytesAdded = 0; @@ -167,6 +176,8 @@ unsigned CSKYInstrInfo::insertBranch( MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(TBB); if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI); + if (Indexes) + Indexes->insertMachineInstrInMaps(MI); return 1; } @@ -175,6 +186,8 @@ unsigned CSKYInstrInfo::insertBranch( MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).addMBB(TBB); if (BytesAdded) *BytesAdded += getInstSizeInBytes(CondMI); + if (Indexes) + Indexes->insertMachineInstrInMaps(CondMI); // One-way conditional branch. if (!FBB) @@ -184,6 +197,8 @@ unsigned CSKYInstrInfo::insertBranch( MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(FBB); if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI); + if (Indexes) + Indexes->insertMachineInstrInMaps(MI); return 2; } diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.h b/llvm/lib/Target/CSKY/CSKYInstrInfo.h index dbb69a7a87980..45fce296e326f 100644 --- a/llvm/lib/Target/CSKY/CSKYInstrInfo.h +++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.h @@ -59,7 +59,7 @@ class CSKYInstrInfo : public CSKYGenInstrInfo { unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, @@ -67,7 +67,7 @@ class CSKYInstrInfo : public CSKYGenInstrInfo { SmallVectorImpl &Cond, bool AllowModify = false) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; bool diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 6f0210763bc5f..2c7526d821d6f 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -36,6 +36,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/ScheduleDAG.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetRegisterInfo.h" @@ -603,6 +604,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -618,19 +620,19 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB, return Count; if (Count && (I->getOpcode() == Hexagon::J2_jump)) llvm_unreachable("Malformed basic block: unconditional branch not last"); - MBB.erase(&MBB.back()); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); + I->eraseFromParent(); I = MBB.end(); ++Count; } return Count; } -unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, - MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - ArrayRef Cond, - const DebugLoc &DL, - int *BytesAdded) const { +unsigned HexagonInstrInfo::insertBranch( + MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, + ArrayRef Cond, const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { unsigned BOpc = Hexagon::J2_jump; unsigned BccOpc = Hexagon::J2_jumpt; assert(validateBranchCond(Cond) && "Invalid branching condition"); @@ -656,10 +658,12 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) && MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) { reverseBranchCondition(Cond); - removeBranch(MBB); - return insertBranch(MBB, TBB, nullptr, Cond, DL); + removeBranch(MBB, Indexes); + return insertBranch(MBB, TBB, nullptr, Cond, DL, Indexes); } - BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); } else if (isEndLoopN(Cond[0].getImm())) { int EndLoopOp = Cond[0].getImm(); assert(Cond[1].isMBB()); @@ -671,7 +675,9 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP"); Loop->getOperand(0).setMBB(TBB); // Add the ENDLOOP after the finding the LOOP0. - BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); } else if (isNewValueJump(Cond[0].getImm())) { assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump"); // New value jump @@ -680,20 +686,30 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, unsigned Flags1 = getUndefRegState(Cond[1].isUndef()); LLVM_DEBUG(dbgs() << "\nInserting NVJump for " << printMBBReference(MBB);); + MachineInstr *MI = nullptr; if (Cond[2].isReg()) { unsigned Flags2 = getUndefRegState(Cond[2].isUndef()); - BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). - addReg(Cond[2].getReg(), Flags2).addMBB(TBB); + MI = BuildMI(&MBB, DL, get(BccOpc)) + .addReg(Cond[1].getReg(), Flags1) + .addReg(Cond[2].getReg(), Flags2) + .addMBB(TBB); } else if(Cond[2].isImm()) { - BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). - addImm(Cond[2].getImm()).addMBB(TBB); + MI = BuildMI(&MBB, DL, get(BccOpc)) + .addReg(Cond[1].getReg(), Flags1) + .addImm(Cond[2].getImm()) + .addMBB(TBB); } else llvm_unreachable("Invalid condition for branching"); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); } else { assert((Cond.size() == 2) && "Malformed cond vector"); const MachineOperand &RO = Cond[1]; unsigned Flags = getUndefRegState(RO.isUndef()); - BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB); + MachineInstr *MI = + BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); } return 1; } @@ -713,13 +729,20 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP"); Loop->getOperand(0).setMBB(TBB); // Add the ENDLOOP after the finding the LOOP0. - BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); } else { const MachineOperand &RO = Cond[1]; unsigned Flags = getUndefRegState(RO.isUndef()); - BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB); + MachineInstr *MI = + BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); } - BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 2; } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 0bc0877f6e706..ea04a966368d3 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -111,7 +111,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo { /// Remove the branching code at the end of the specific MBB. /// This is only invoked in cases where analyzeBranch returns success. It /// returns the number of instructions that were removed. - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; /// Insert branch code into the end of the specified MachineBasicBlock. @@ -126,7 +126,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo { /// merging needs to be disabled. unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; /// Analyze loop L, which must be a single-basic-block loop, and if the diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp index aa7e8846406dd..89a1f22ac85c8 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -19,6 +19,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" @@ -657,7 +658,7 @@ unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef Condition, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes, int *BytesAdded) const { // Shouldn't be a fall through. assert(TrueBlock && "insertBranch must not be told to insert a fallthrough"); @@ -666,7 +667,9 @@ unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB, // If condition is empty then an unconditional branch is being inserted. if (Condition.empty()) { assert(!FalseBlock && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(TrueBlock); + MachineInstr *MI = BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(TrueBlock); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } @@ -674,18 +677,25 @@ unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB, assert((Condition.size() == 1) && "Lanai branch conditions should have one component."); unsigned ConditionalCode = Condition[0].getImm(); - BuildMI(&MBB, DL, get(Lanai::BRCC)).addMBB(TrueBlock).addImm(ConditionalCode); + MachineInstr *CondBr = BuildMI(&MBB, DL, get(Lanai::BRCC)) + .addMBB(TrueBlock) + .addImm(ConditionalCode); + if (Indexes) + Indexes->insertMachineInstrInMaps(*CondBr); // If no false block, then false behavior is fall through and no branch needs // to be inserted. if (!FalseBlock) return 1; - BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(FalseBlock); + MachineInstr *UncondBr = BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(FalseBlock); + if (Indexes) + Indexes->insertMachineInstrInMaps(*UncondBr); return 2; } unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -702,6 +712,8 @@ unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB, } // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*Instruction); Instruction->eraseFromParent(); Instruction = MBB.end(); ++Count; diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h index 62f6240c6e468..5d66056a0f556 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h @@ -89,7 +89,7 @@ class LanaiInstrInfo : public LanaiGenInstrInfo { SmallVectorImpl &Condition, bool AllowModify) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; // For a comparison instruction, return the source registers in SrcReg and @@ -138,8 +138,8 @@ class LanaiInstrInfo : public LanaiGenInstrInfo { unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, - ArrayRef Condition, - const DebugLoc &DL, + ArrayRef Condition, const DebugLoc &DL, + SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; }; diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp index 9fad3377a8fd8..fc4e2d8b1e84f 100644 --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp @@ -17,6 +17,7 @@ #include "MCTargetDesc/LoongArchMCTargetDesc.h" #include "MCTargetDesc/LoongArchMatInt.h" #include "llvm/CodeGen/RegisterScavenging.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/MC/MCInstBuilder.h" using namespace llvm; @@ -319,6 +320,7 @@ bool LoongArchInstrInfo::isBranchOffsetInRange(unsigned BranchOp, } unsigned LoongArchInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { if (BytesRemoved) *BytesRemoved = 0; @@ -332,6 +334,8 @@ unsigned LoongArchInstrInfo::removeBranch(MachineBasicBlock &MBB, // Remove the branch. if (BytesRemoved) *BytesRemoved += getInstSizeInBytes(*I); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); @@ -345,6 +349,8 @@ unsigned LoongArchInstrInfo::removeBranch(MachineBasicBlock &MBB, // Remove the branch. if (BytesRemoved) *BytesRemoved += getInstSizeInBytes(*I); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); return 2; } @@ -353,7 +359,8 @@ unsigned LoongArchInstrInfo::removeBranch(MachineBasicBlock &MBB, // the number of instructions inserted. unsigned LoongArchInstrInfo::insertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { + ArrayRef Cond, const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { if (BytesAdded) *BytesAdded = 0; @@ -367,6 +374,8 @@ unsigned LoongArchInstrInfo::insertBranch( MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(TBB); if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI); + if (Indexes) + Indexes->insertMachineInstrInMaps(MI); return 1; } @@ -377,6 +386,8 @@ unsigned LoongArchInstrInfo::insertBranch( MIB.addMBB(TBB); if (BytesAdded) *BytesAdded += getInstSizeInBytes(*MIB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MIB); // One-way conditional branch. if (!FBB) @@ -386,6 +397,8 @@ unsigned LoongArchInstrInfo::insertBranch( MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(FBB); if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI); + if (Indexes) + Indexes->insertMachineInstrInMaps(MI); return 2; } diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h index cf83abf27a1e3..08b9c88bbdb81 100644 --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h @@ -62,12 +62,12 @@ class LoongArchInstrInfo : public LoongArchGenInstrInfo { bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &dl, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; void insertIndirectBranch(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp index 8d36e94d8e696..82e60ea6adcf1 100644 --- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp +++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp @@ -24,6 +24,7 @@ #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Regex.h" @@ -255,6 +256,7 @@ bool M68kInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } unsigned M68kInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -269,6 +271,8 @@ unsigned M68kInstrInfo::removeBranch(MachineBasicBlock &MBB, getCondFromBranchOpc(I->getOpcode()) == M68k::COND_INVALID) break; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); ++Count; @@ -277,9 +281,12 @@ unsigned M68kInstrInfo::removeBranch(MachineBasicBlock &MBB, return Count; } -unsigned M68kInstrInfo::insertBranch( - MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { +unsigned M68kInstrInfo::insertBranch(MachineBasicBlock &MBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + ArrayRef Cond, + const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && @@ -289,7 +296,9 @@ unsigned M68kInstrInfo::insertBranch( if (Cond.empty()) { // Unconditional branch? assert(!FBB && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } @@ -300,11 +309,15 @@ unsigned M68kInstrInfo::insertBranch( unsigned Count = 0; M68k::CondCode CC = (M68k::CondCode)Cond[0].getImm(); unsigned Opc = GetCondBranchFromCond(CC); - BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); + MachineInstr *CondMI = BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*CondMI); ++Count; if (!FallThru) { // Two-way Conditional branch. Insert the second branch. - BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(FBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(FBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); ++Count; } return Count; diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.h b/llvm/lib/Target/M68k/M68kInstrInfo.h index 577967f2fdfc9..2a6e720c71d22 100644 --- a/llvm/lib/Target/M68k/M68kInstrInfo.h +++ b/llvm/lib/Target/M68k/M68kInstrInfo.h @@ -261,12 +261,12 @@ class M68kInstrInfo : public M68kGenInstrInfo { SmallVectorImpl &Cond, bool AllowModify) const; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp index 7405716516643..835dc9a8ccaae 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -17,6 +17,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/IR/Function.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" @@ -104,6 +105,7 @@ void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB, } unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -121,6 +123,8 @@ unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB, I->getOpcode() != MSP430::Bm) break; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); ++Count; @@ -254,7 +258,7 @@ unsigned MSP430InstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes, int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "insertBranch must not be told to insert a fallthrough"); @@ -265,18 +269,25 @@ unsigned MSP430InstrInfo::insertBranch(MachineBasicBlock &MBB, if (Cond.empty()) { // Unconditional branch? assert(!FBB && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } // Conditional branch. unsigned Count = 0; - BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm()); + MachineInstr *CondBr = + BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm()); + if (Indexes) + Indexes->insertMachineInstrInMaps(*CondBr); ++Count; if (FBB) { // Two-way Conditional branch. Insert the second branch. - BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB); + MachineInstr *UncondBr = BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*UncondBr); ++Count; } return Count; diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.h b/llvm/lib/Target/MSP430/MSP430InstrInfo.h index b8d015a21cd15..42ec12d9376ef 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.h +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.h @@ -61,11 +61,11 @@ class MSP430InstrInfo : public MSP430GenInstrInfo { SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; int64_t getFramePoppedByCallee(const MachineInstr &I) const { diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index 392cc15d7943a..ab74ffb61b0db 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineOperand.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/DebugInfoMetadata.h" @@ -118,7 +119,8 @@ bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB, void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, const DebugLoc &DL, - ArrayRef Cond) const { + ArrayRef Cond, + SlotIndexes *Indexes) const { unsigned Opc = Cond[0].getImm(); const MCInstrDesc &MCID = get(Opc); MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); @@ -129,13 +131,15 @@ void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MIB.add(Cond[i]); } MIB.addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MIB); } unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes, int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "insertBranch must not be told to insert a fallthrough"); @@ -151,21 +155,26 @@ unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB, // Two-way Conditional branch. if (FBB) { - BuildCondBr(MBB, TBB, DL, Cond); - BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB); + BuildCondBr(MBB, TBB, DL, Cond, Indexes); + MachineInstr *MI = BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 2; } // One way branch. // Unconditional branch. - if (Cond.empty()) - BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB); - else // Conditional branch. - BuildCondBr(MBB, TBB, DL, Cond); + if (Cond.empty()) { + MachineInstr *MI = BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); + } else // Conditional branch. + BuildCondBr(MBB, TBB, DL, Cond, Indexes); return 1; } unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -183,6 +192,8 @@ unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB, if (!getAnalyzableBrOpc(I->getOpcode())) break; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.rbegin(); ++removed; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h index dc4b9d99b39d2..bf9c7f5c78279 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsInstrInfo.h @@ -65,12 +65,12 @@ class MipsInstrInfo : public MipsGenInstrInfo { SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; bool @@ -206,7 +206,8 @@ class MipsInstrInfo : public MipsGenInstrInfo { SmallVectorImpl &Cond) const; void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - const DebugLoc &DL, ArrayRef Cond) const; + const DebugLoc &DL, ArrayRef Cond, + SlotIndexes *Indexes = nullptr) const; }; /// Create MipsInstrInfo objects. diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp index b0d792b5ee3fe..298599229eec3 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp @@ -17,6 +17,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/IR/Function.h" using namespace llvm; @@ -147,6 +148,7 @@ bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); MachineBasicBlock::iterator I = MBB.end(); @@ -157,6 +159,8 @@ unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB, return 0; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); @@ -168,6 +172,8 @@ unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB, return 1; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); return 2; } @@ -176,7 +182,7 @@ unsigned NVPTXInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes, int *BytesAdded) const { assert(!BytesAdded && "code size not handled"); @@ -187,15 +193,23 @@ unsigned NVPTXInstrInfo::insertBranch(MachineBasicBlock &MBB, // One-way branch. if (!FBB) { + MachineInstr *MI; if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB); + MI = BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB); else // Conditional branch - BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); + MI = BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } // Two-way Conditional Branch. - BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); - BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB); + MachineInstr *CondBr = + BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); + MachineInstr *UncondBr = BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB); + if (Indexes) { + Indexes->insertMachineInstrInMaps(*CondBr); + Indexes->insertMachineInstrInMaps(*UncondBr); + } return 2; } diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h index cd068a0939300..0e8f9bd0f4775 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h @@ -60,11 +60,11 @@ class NVPTXInstrInfo : public NVPTXGenInstrInfo { MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; }; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 6ca68ecdcc773..1ff163f73b3de 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1441,6 +1441,7 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -1455,6 +1456,8 @@ unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB, return 0; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); @@ -1468,6 +1471,8 @@ unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB, return 1; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); return 2; } @@ -1476,7 +1481,7 @@ unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes, int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "insertBranch must not be told to insert a fallthrough"); @@ -1488,39 +1493,49 @@ unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB, // One-way branch. if (!FBB) { + MachineInstr *MI; if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); + MI = BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) - BuildMI(&MBB, DL, get(Cond[0].getImm() ? - (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : - (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); + MI = BuildMI(&MBB, DL, + get(Cond[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) + : (isPPC64 ? PPC::BDZ8 : PPC::BDZ))) + .addMBB(TBB); else if (Cond[0].getImm() == PPC::PRED_BIT_SET) - BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); + MI = BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) - BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); + MI = BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); else // Conditional branch - BuildMI(&MBB, DL, get(PPC::BCC)) - .addImm(Cond[0].getImm()) - .add(Cond[1]) - .addMBB(TBB); + MI = BuildMI(&MBB, DL, get(PPC::BCC)) + .addImm(Cond[0].getImm()) + .add(Cond[1]) + .addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } // Two-way Conditional Branch. + MachineInstr *CondBr; if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) - BuildMI(&MBB, DL, get(Cond[0].getImm() ? - (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : - (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); + CondBr = BuildMI(&MBB, DL, + get(Cond[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) + : (isPPC64 ? PPC::BDZ8 : PPC::BDZ))) + .addMBB(TBB); else if (Cond[0].getImm() == PPC::PRED_BIT_SET) - BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); + CondBr = BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) - BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); + CondBr = BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); else - BuildMI(&MBB, DL, get(PPC::BCC)) - .addImm(Cond[0].getImm()) - .add(Cond[1]) - .addMBB(TBB); - BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); + CondBr = BuildMI(&MBB, DL, get(PPC::BCC)) + .addImm(Cond[0].getImm()) + .add(Cond[1]) + .addMBB(TBB); + MachineInstr *UncondBr = BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); + if (Indexes) { + Indexes->insertMachineInstrInMaps(*CondBr); + Indexes->insertMachineInstrInMaps(*UncondBr); + } return 2; } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index 93d2a58aa3902..d102b82d8a641 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -395,11 +395,12 @@ class PPCInstrInfo : public PPCGenInstrInfo { MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; // Select analysis. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 14f1bff4aee4c..30c29360b9c9c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -924,6 +924,7 @@ bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { if (BytesRemoved) *BytesRemoved = 0; @@ -938,6 +939,8 @@ unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB, // Remove the branch. if (BytesRemoved) *BytesRemoved += getInstSizeInBytes(*I); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); @@ -951,15 +954,20 @@ unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB, // Remove the branch. if (BytesRemoved) *BytesRemoved += getInstSizeInBytes(*I); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); return 2; } // Inserts a branch into the end of the specific MachineBasicBlock, returning // the number of instructions inserted. -unsigned RISCVInstrInfo::insertBranch( - MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { +unsigned RISCVInstrInfo::insertBranch(MachineBasicBlock &MBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + ArrayRef Cond, + const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { if (BytesAdded) *BytesAdded = 0; @@ -973,6 +981,8 @@ unsigned RISCVInstrInfo::insertBranch( MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB); if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI); + if (Indexes) + Indexes->insertMachineInstrInMaps(MI); return 1; } @@ -982,6 +992,8 @@ unsigned RISCVInstrInfo::insertBranch( *BuildMI(&MBB, DL, getBrCond(CC)).add(Cond[1]).add(Cond[2]).addMBB(TBB); if (BytesAdded) *BytesAdded += getInstSizeInBytes(CondMI); + if (Indexes) + Indexes->insertMachineInstrInMaps(CondMI); // One-way conditional branch. if (!FBB) @@ -991,6 +1003,8 @@ unsigned RISCVInstrInfo::insertBranch( MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB); if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI); + if (Indexes) + Indexes->insertMachineInstrInMaps(MI); return 2; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index 99c907a98121a..0964eddd40a83 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -102,7 +102,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo { unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &dl, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; void insertIndirectBranch(MachineBasicBlock &MBB, @@ -110,7 +110,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo { MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; bool diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp index 42317453a2370..313d26d9f6526 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp @@ -201,6 +201,7 @@ bool SPIRVInstrInfo::analyzeBranch(MachineBasicBlock &MBB, // If \p BytesRemoved is non-null, report the change in code size from the // removed instructions. unsigned SPIRVInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { report_fatal_error("Branch removal not supported, as MBB info not propagated" " to OpPhi instructions. Try using -O0 instead."); @@ -219,9 +220,12 @@ unsigned SPIRVInstrInfo::removeBranch(MachineBasicBlock &MBB, // // The CFG information in MBB.Predecessors and MBB.Successors must be valid // before calling this function. -unsigned SPIRVInstrInfo::insertBranch( - MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { +unsigned SPIRVInstrInfo::insertBranch(MachineBasicBlock &MBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + ArrayRef Cond, + const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { report_fatal_error("Branch insertion not supported, as MBB info not " "propagated to OpPhi instructions. Try using " "-O0 instead."); diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h index c01e30e109bd5..02050023975b2 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h +++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h @@ -41,12 +41,12 @@ class SPIRVInstrInfo : public SPIRVGenInstrInfo { SmallVectorImpl &Cond, bool AllowModify = false) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 90662cd87dcf1..dad5fee070d0d 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" @@ -328,7 +329,7 @@ unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes, int *BytesAdded) const { assert(TBB && "insertBranch must not be told to insert a fallthrough"); assert((Cond.size() <= 3) && @@ -336,21 +337,26 @@ unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB, if (Cond.empty()) { assert(!FBB && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); if (BytesAdded) *BytesAdded = 8; + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } // Conditional branch + MachineInstr *CondMI; unsigned Opc = Cond[0].getImm(); unsigned CC = Cond[1].getImm(); if (isRegCondBranchOpcode(Opc)) { Register Reg = Cond[2].getReg(); - BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC).addReg(Reg); + CondMI = BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC).addReg(Reg); } else { - BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC); + CondMI = BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC); } + if (Indexes) + Indexes->insertMachineInstrInMaps(*CondMI); if (!FBB) { if (BytesAdded) @@ -358,13 +364,17 @@ unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB, return 1; } - BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); if (BytesAdded) *BytesAdded = 16; + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); + return 2; } unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; @@ -380,6 +390,8 @@ unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB, break; // Not a branch Removed += getInstSizeInBytes(*I); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); ++Count; diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h index 7056d6babe17b..9fc41d551413d 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.h +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h @@ -71,12 +71,12 @@ class SparcInstrInfo : public SparcGenInstrInfo { SmallVectorImpl &Cond, bool AllowModify = false) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; bool diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index ac8c395f9064f..b8958909a4720 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -447,6 +447,7 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -464,6 +465,8 @@ unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB, break; // Remove the branch. I->eraseFromParent(); + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I = MBB.end(); ++Count; } @@ -478,12 +481,10 @@ reverseBranchCondition(SmallVectorImpl &Cond) const { return false; } -unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB, - MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - ArrayRef Cond, - const DebugLoc &DL, - int *BytesAdded) const { +unsigned SystemZInstrInfo::insertBranch( + MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, + ArrayRef Cond, const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { // In this function we output 32-bit branches, which should always // have enough range. They can be shortened and relaxed by later code // in the pipeline, if desired. @@ -497,7 +498,9 @@ unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB, if (Cond.empty()) { // Unconditional branch? assert(!FBB && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } @@ -505,14 +508,20 @@ unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB, unsigned Count = 0; unsigned CCValid = Cond[0].getImm(); unsigned CCMask = Cond[1].getImm(); - BuildMI(&MBB, DL, get(SystemZ::BRC)) - .addImm(CCValid).addImm(CCMask).addMBB(TBB); + MachineInstr *TrueMI = BuildMI(&MBB, DL, get(SystemZ::BRC)) + .addImm(CCValid) + .addImm(CCMask) + .addMBB(TBB); ++Count; + if (Indexes) + Indexes->insertMachineInstrInMaps(*TrueMI); if (FBB) { // Two-way Conditional branch. Insert the second branch. - BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB); + MachineInstr *FalseMI = BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB); ++Count; + if (Indexes) + Indexes->insertMachineInstrInMaps(*FalseMI); } return Count; } diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h index bb883ea464d37..e4c016ff186ce 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h @@ -238,11 +238,11 @@ class SystemZInstrInfo : public SystemZGenInstrInfo { MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp index ebb9e21389c37..35712125e0535 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.cpp +++ b/llvm/lib/Target/VE/VEInstrInfo.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" @@ -227,7 +228,8 @@ unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, int *BytesAdded) const { + const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { assert(TBB && "insertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 3 || Cond.size() == 0) && "VE branch conditions should have three component!"); @@ -235,8 +237,9 @@ unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB, if (Cond.empty()) { // Uncondition branch assert(!FBB && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, DL, get(VE::BRCFLa_t)) - .addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(VE::BRCFLa_t)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } @@ -266,29 +269,34 @@ unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB, opc[1] = VE::BRCFDrr; } } + MachineInstr *CondMI; if (Cond[1].isImm()) { - BuildMI(&MBB, DL, get(opc[0])) - .add(Cond[0]) // condition code - .add(Cond[1]) // lhs - .add(Cond[2]) // rhs - .addMBB(TBB); + CondMI = BuildMI(&MBB, DL, get(opc[0])) + .add(Cond[0]) // condition code + .add(Cond[1]) // lhs + .add(Cond[2]) // rhs + .addMBB(TBB); } else { - BuildMI(&MBB, DL, get(opc[1])) - .add(Cond[0]) - .add(Cond[1]) - .add(Cond[2]) - .addMBB(TBB); + CondMI = BuildMI(&MBB, DL, get(opc[1])) + .add(Cond[0]) + .add(Cond[1]) + .add(Cond[2]) + .addMBB(TBB); } + if (Indexes) + Indexes->insertMachineInstrInMaps(*CondMI); if (!FBB) return 1; - BuildMI(&MBB, DL, get(VE::BRCFLa_t)) - .addMBB(FBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(VE::BRCFLa_t)).addMBB(FBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); + return 2; } -unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB, +unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -304,6 +312,8 @@ unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB, !isCondBranchOpcode(I->getOpcode())) break; // Not a branch + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); ++Count; diff --git a/llvm/lib/Target/VE/VEInstrInfo.h b/llvm/lib/Target/VE/VEInstrInfo.h index 4fe56f24116f8..b9d6306f34770 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.h +++ b/llvm/lib/Target/VE/VEInstrInfo.h @@ -67,12 +67,12 @@ class VEInstrInfo : public VEGenInstrInfo { SmallVectorImpl &Cond, bool AllowModify = false) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; bool diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp index 32a4accd040eb..bed6a325c775e 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp @@ -22,6 +22,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" using namespace llvm; #define DEBUG_TYPE "wasm-instr-info" @@ -135,6 +136,7 @@ bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -148,6 +150,8 @@ unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB, if (!I->isTerminator()) break; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.instr_end(); ++Count; @@ -158,27 +162,38 @@ unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB, unsigned WebAssemblyInstrInfo::insertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { + ArrayRef Cond, const DebugLoc &DL, SlotIndexes *Indexes, + int *BytesAdded) const { assert(!BytesAdded && "code size not handled"); if (Cond.empty()) { if (!TBB) return 0; - BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } assert(Cond.size() == 2 && "Expected a flag and a successor block"); - if (Cond[0].getImm()) - BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); - else - BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]); + MachineInstr *CondMI; + if (Cond[0].getImm()) { + CondMI = + BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); + } else { + CondMI = + BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]); + } + if (Indexes) + Indexes->insertMachineInstrInMaps(*CondMI); if (!FBB) return 1; - BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 2; } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h index c1e1a790c60e2..bd671a3ae4c6a 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h @@ -56,11 +56,11 @@ class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo { MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify = false) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; bool reverseBranchCondition(SmallVectorImpl &Cond) const override; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 205fd24e6d402..a5380c47e56e6 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -3343,6 +3343,7 @@ bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB, } unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -3357,6 +3358,8 @@ unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB, X86::getCondFromBranch(*I) == X86::COND_INVALID) break; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); ++Count; @@ -3369,7 +3372,7 @@ unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes, int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "insertBranch must not be told to insert a fallthrough"); @@ -3380,7 +3383,9 @@ unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB, if (Cond.empty()) { // Unconditional branch? assert(!FBB && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB); + MachineInstr *MI = BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB); + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } @@ -3388,15 +3393,15 @@ unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB, bool FallThru = FBB == nullptr; // Conditional branch. - unsigned Count = 0; + SmallVector Instrs; X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); switch (CC) { case X86::COND_NE_OR_P: // Synthesize NE_OR_P with two branches. - BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE); - ++Count; - BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P); - ++Count; + Instrs.push_back( + BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE)); + Instrs.push_back( + BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P)); break; case X86::COND_E_AND_NP: // Use the next block of MBB as FBB if it is null. @@ -3406,22 +3411,24 @@ unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB, "body is a fall-through."); } // Synthesize COND_E_AND_NP with two branches. - BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE); - ++Count; - BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP); - ++Count; + Instrs.push_back( + BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE)); + Instrs.push_back( + BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP)); break; default: { - BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC); - ++Count; + Instrs.push_back(BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC)); } } if (!FallThru) { // Two-way Conditional branch. Insert the second branch. - BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB); - ++Count; + Instrs.push_back(BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB)); } - return Count; + if (Indexes) { + for (MachineInstr *MI : Instrs) + Indexes->insertMachineInstrInMaps(*MI); + } + return Instrs.size(); } bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index 9a072c6569fe9..2ab3e3093b600 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -349,11 +349,11 @@ class X86InstrInfo final : public X86GenInstrInfo { TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify = false) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; bool canInsertSelect(const MachineBasicBlock &, ArrayRef Cond, Register, Register, Register, int &, int &, diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index d8a8e2cddf154..3b92d40d1c2d4 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -18,6 +18,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Function.h" #include "llvm/MC/MCContext.h" @@ -272,7 +273,7 @@ unsigned XCoreInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes, int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "insertBranch must not be told to insert a fallthrough"); @@ -281,29 +282,36 @@ unsigned XCoreInstrInfo::insertBranch(MachineBasicBlock &MBB, assert(!BytesAdded && "code size not handled"); if (!FBB) { // One way branch. + MachineInstr *MI; if (Cond.empty()) { // Unconditional branch - BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB); + MI = BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB); } else { // Conditional branch. unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); - BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) - .addMBB(TBB); + MI = BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB); } + if (Indexes) + Indexes->insertMachineInstrInMaps(*MI); return 1; } // Two-way Conditional branch. assert(Cond.size() == 2 && "Unexpected number of components!"); unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); - BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) - .addMBB(TBB); - BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB); + MachineInstr *CondBr = + BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB); + MachineInstr *UncondBr = BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB); + if (Indexes) { + Indexes->insertMachineInstrInMaps(*CondBr); + Indexes->insertMachineInstrInMaps(*UncondBr); + } return 2; } -unsigned -XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { +unsigned XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, + SlotIndexes *Indexes, + int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); @@ -314,6 +322,8 @@ XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { return 0; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); I = MBB.end(); @@ -324,6 +334,8 @@ XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { return 1; // Remove the branch. + if (Indexes) + Indexes->removeMachineInstrFromMaps(*I); I->eraseFromParent(); return 2; } diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h index 9bf7e2dcccb7d..461f11a0645d2 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.h +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h @@ -56,10 +56,10 @@ class XCoreInstrInfo : public XCoreGenInstrInfo { unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, + const DebugLoc &DL, SlotIndexes *Indexes = nullptr, int *BytesAdded = nullptr) const override; - unsigned removeBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr, int *BytesRemoved = nullptr) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,