diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
index 6ddb1cc3afb0d..45028f156166d 100644
--- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td
+++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
@@ -476,21 +476,6 @@ def SETHIXi : F2_1<0b100,
 
 // ATOMICS.
 let Predicates = [Is64Bit, HasV9], Constraints = "$swap = $rd" in {
-  let asi = 0b10000000 in
-    def CASXrr: F3_1_asi<3, 0b111110,
-                (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
-                                     I64Regs:$swap),
-                 "casx [$rs1], $rs2, $rd",
-                 [(set i64:$rd,
-                     (atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap))]>;
-
-  let asi = 0b10001000 in
-    def CASXLrr: F3_1_asi<3, 0b111110,
-                (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
-                                     I64Regs:$swap),
-                 "casxl [$rs1], $rs2, $rd",
-                 []>;
-
   def CASXArr: F3_1_asi<3, 0b111110,
                 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
                                      I64Regs:$swap, ASITag:$asi),
@@ -515,6 +500,9 @@ def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>;
 def : Pat<(atomic_store_64 i64:$val, ADDRrr:$dst), (STXrr ADDRrr:$dst, $val)>;
 def : Pat<(atomic_store_64 i64:$val, ADDRri:$dst), (STXri ADDRri:$dst, $val)>;
 
+def : Pat<(atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap),
+          (CASXArr $rs1, $rs2, $swap, 0x80)>;
+
 } // Predicates = [Is64Bit]
 
 let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in
diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index dcc6ec3c97145..5ee8ff978a242 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -464,6 +464,24 @@ def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
 // neg reg, rd -> sub %g0, reg, rd
 def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
 
+let Predicates = [HasV9] in {
+  // cas [rs1], rs2, rd -> casa [rs1] #ASI_P, rs2, rd
+  def : InstAlias<"cas [$rs1], $rs2, $rd",
+                  (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x80)>;
+
+  // casl [rs1], rs2, rd -> casa [rs1] #ASI_P_L, rs2, rd
+  def : InstAlias<"casl [$rs1], $rs2, $rd",
+                  (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x88)>;
+
+  // casx [rs1], rs2, rd -> casxa [rs1] #ASI_P, rs2, rd
+  def : InstAlias<"casx [$rs1], $rs2, $rd",
+                  (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x80)>;
+
+  // casxl [rs1], rs2, rd -> casxa [rs1] #ASI_P_L, rs2, rd
+  def : InstAlias<"casxl [$rs1], $rs2, $rd",
+                  (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x88)>;
+}
+
 // inc rd -> add rd, 1, rd
 def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
 
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 1d625b608a2b5..0ae0dfbb00503 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -1703,41 +1703,7 @@ let Predicates = [HasV9], rd = 15, rs1 = 0b00000 in
                 (ins simm13Op:$simm13),
                  "sir $simm13", []>;
 
-// The CAS instruction, unlike other instructions, only comes in a
-// form which requires an ASI be provided.
-let Predicates = [HasV9], Constraints = "$swap = $rd" in {
-  // The ASI value hardcoded here is ASI_PRIMARY, the default
-  // unprivileged ASI for SparcV9.
-  let asi = 0b10000000 in
-    def CASrr: F3_1_asi<3, 0b111100,
-                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
-                                     IntRegs:$swap),
-                 "cas [$rs1], $rs2, $rd",
-                 [(set i32:$rd,
-                     (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
-
-  // SparcV9 also specifies a CASL alias, which uses ASI_PRIMARY_LITTLE.
-  let asi = 0b10001000 in
-    def CASLrr: F3_1_asi<3, 0b111100,
-                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
-                                     IntRegs:$swap),
-                 "casl [$rs1], $rs2, $rd",
-                 []>;
-}
-
-// CASA is supported as an instruction on some LEON3 and all LEON4 processors.
-// This version can be automatically lowered from C code, selecting ASI 10
-let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in
-  def CASAasi10: F3_1_asi<3, 0b111100,
-                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
-                                     IntRegs:$swap),
-                 "casa [$rs1] 10, $rs2, $rd",
-                 [(set i32:$rd,
-                     (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
-
 // CASA supported on all V9, some LEON3 and all LEON4 processors.
-// Same pattern as CASrr above, but with a different ASI.
-// This version is supported for inline assembly lowering only.
 let Predicates = [HasCASA], Constraints = "$swap = $rd" in
   def CASArr: F3_1_asi<3, 0b111100,
                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
@@ -1938,6 +1904,15 @@ def : Pat<(atomic_store_16 i32:$val, ADDRri:$dst), (STHri ADDRri:$dst, $val)>;
 def : Pat<(atomic_store_32 i32:$val, ADDRrr:$dst), (STrr ADDRrr:$dst, $val)>;
 def : Pat<(atomic_store_32 i32:$val, ADDRri:$dst), (STri ADDRri:$dst, $val)>;
 
+let Predicates = [HasV9] in
+def : Pat<(atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap),
+          (CASArr $rs1, $rs2, $swap, 0x80)>;
+
+// Same pattern as CASArr above, but with a different ASI.
+let Predicates = [HasLeonCASA] in
+def : Pat<(atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap),
+          (CASArr $rs1, $rs2, $swap, 0x0A)>;
+
 // A register pair with zero upper half.
 // The upper part is done with ORrr instead of `COPY G0`
 // or a normal register copy, since `COPY G0`s in that place
diff --git a/llvm/test/MC/Sparc/sparc-cas-instructions.s b/llvm/test/MC/Sparc/sparc-cas-instructions.s
index c0cf72dda208b..4e30fed378beb 100644
--- a/llvm/test/MC/Sparc/sparc-cas-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-cas-instructions.s
@@ -28,12 +28,12 @@ casxl [%i0], %l6, %o2
 casxa [%i0] %asi, %l6, %o2
 
 ! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casxa [%i0] #ASI_P, %l6, %o2   ! encoding: [0xd5,0xf6,0x10,0x16]
+! V9: casx [%i0], %l6, %o2   ! encoding: [0xd5,0xf6,0x10,0x16]
 ! LEON: error: instruction requires a CPU feature not currently enabled
 casxa [%i0] 0x80, %l6, %o2
 
 ! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casxa [%i0] #ASI_P, %l6, %o2   ! encoding: [0xd5,0xf6,0x10,0x16]
+! V9: casx [%i0], %l6, %o2   ! encoding: [0xd5,0xf6,0x10,0x16]
 ! LEON: error: instruction requires a CPU feature not currently enabled
 casxa [%i0] (0x40+0x40), %l6, %o2
 
@@ -43,11 +43,11 @@ casxa [%i0] (0x40+0x40), %l6, %o2
 casa [%i0] %asi, %l6, %o2
 
 ! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casa [%i0] #ASI_P, %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
+! V9: cas [%i0], %l6, %o2          ! encoding: [0xd5,0xe6,0x10,0x16]
 ! LEON: casa [%i0] 128, %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
 casa [%i0] 0x80, %l6, %o2
 
 ! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casa [%i0] #ASI_P, %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
+! V9: cas [%i0], %l6, %o2          ! encoding: [0xd5,0xe6,0x10,0x16]
 ! LEON: casa [%i0] 128, %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
 casa [%i0] (0x40+0x40), %l6, %o2
diff --git a/llvm/test/MC/Sparc/sparcv9-asi-names.s b/llvm/test/MC/Sparc/sparcv9-asi-names.s
index 042d62380b03a..a27d1a0c30d8d 100644
--- a/llvm/test/MC/Sparc/sparcv9-asi-names.s
+++ b/llvm/test/MC/Sparc/sparcv9-asi-names.s
@@ -13,7 +13,7 @@ casxa [%i0] #ASI_AIUS, %l6, %o2
 casxa [%i0] #ASI_AIUP_L, %l6, %o2
 ! V9: casxa [%i0] #ASI_AIUS_L, %l6, %o2       ! encoding: [0xd5,0xf6,0x03,0x36]
 casxa [%i0] #ASI_AIUS_L, %l6, %o2
-! V9: casxa [%i0] #ASI_P, %l6, %o2            ! encoding: [0xd5,0xf6,0x10,0x16]
+! V9: casx [%i0], %l6, %o2                    ! encoding: [0xd5,0xf6,0x10,0x16]
 casxa [%i0] #ASI_P, %l6, %o2
 ! V9: casxa [%i0] #ASI_S, %l6, %o2            ! encoding: [0xd5,0xf6,0x10,0x36]
 casxa [%i0] #ASI_S, %l6, %o2
@@ -21,7 +21,7 @@ casxa [%i0] #ASI_S, %l6, %o2
 casxa [%i0] #ASI_PNF, %l6, %o2
 ! V9: casxa [%i0] #ASI_SNF, %l6, %o2          ! encoding: [0xd5,0xf6,0x10,0x76]
 casxa [%i0] #ASI_SNF, %l6, %o2
-! V9: casxa [%i0] #ASI_P_L, %l6, %o2          ! encoding: [0xd5,0xf6,0x11,0x16]
+! V9: casxl [%i0], %l6, %o2                   ! encoding: [0xd5,0xf6,0x11,0x16]
 casxa [%i0] #ASI_P_L, %l6, %o2
 ! V9: casxa [%i0] #ASI_S_L, %l6, %o2          ! encoding: [0xd5,0xf6,0x11,0x36]
 casxa [%i0] #ASI_S_L, %l6, %o2
@@ -43,7 +43,7 @@ casxa [%i0] #ASI_AS_IF_USER_SECONDARY, %l6, %o2
 casxa [%i0] #ASI_AS_IF_USER_PRIMARY_LITTLE, %l6, %o2
 ! V9: casxa [%i0] #ASI_AIUS_L, %l6, %o2       ! encoding: [0xd5,0xf6,0x03,0x36]
 casxa [%i0] #ASI_AS_IF_USER_SECONDARY_LITTLE, %l6, %o2
-! V9: casxa [%i0] #ASI_P, %l6, %o2            ! encoding: [0xd5,0xf6,0x10,0x16]
+! V9: casx [%i0], %l6, %o2                    ! encoding: [0xd5,0xf6,0x10,0x16]
 casxa [%i0] #ASI_PRIMARY, %l6, %o2
 ! V9: casxa [%i0] #ASI_S, %l6, %o2            ! encoding: [0xd5,0xf6,0x10,0x36]
 casxa [%i0] #ASI_SECONDARY, %l6, %o2
@@ -51,7 +51,7 @@ casxa [%i0] #ASI_SECONDARY, %l6, %o2
 casxa [%i0] #ASI_PRIMARY_NOFAULT, %l6, %o2
 ! V9: casxa [%i0] #ASI_SNF, %l6, %o2          ! encoding: [0xd5,0xf6,0x10,0x76]
 casxa [%i0] #ASI_SECONDARY_NOFAULT, %l6, %o2
-! V9: casxa [%i0] #ASI_P_L, %l6, %o2          ! encoding: [0xd5,0xf6,0x11,0x16]
+! V9: casxl [%i0], %l6, %o2                   ! encoding: [0xd5,0xf6,0x11,0x16]
 casxa [%i0] #ASI_PRIMARY_LITTLE, %l6, %o2
 ! V9: casxa [%i0] #ASI_S_L, %l6, %o2          ! encoding: [0xd5,0xf6,0x11,0x36]
 casxa [%i0] #ASI_SECONDARY_LITTLE, %l6, %o2