From a9a3bd843b86cef887ebfb04693e1d280d3dc13a Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 5 Sep 2023 17:26:59 +0100 Subject: [PATCH 1/2] [RISCV] Refactor extract_subvector slightly. NFC This patch refactors extract_subvector to lower to extract_subreg directly, and to shortcut whenever the index is 0 when extracting a scalable vector. This doesn't change any of the existing behaviour, but makes an upcoming patch that extends the scalable path slightly easier to read. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 22 +++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index d7112461a1815..41d38a0d4483c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -8735,16 +8735,17 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op, } } + // With an index of 0 this is a cast-like subvector, which can be performed + // with subregister operations. + if (OrigIdx == 0) + return Op; + // If the subvector vector is a fixed-length type, we cannot use subregister // manipulation to simplify the codegen; we don't know which register of a // LMUL group contains the specific subvector as we only know the minimum // register size. Therefore we must slide the vector group down the full // amount. if (SubVecVT.isFixedLengthVector()) { - // With an index of 0 this is a cast-like subvector, which can be performed - // with subregister operations. - if (OrigIdx == 0) - return Op; MVT ContainerVT = VecVT; if (VecVT.isFixedLengthVector()) { ContainerVT = getContainerForFixedLengthVector(VecVT); @@ -8776,17 +8777,18 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op, if (RemIdx == 0) return Op; - // Else we must shift our vector register directly to extract the subvector. - // Do this using VSLIDEDOWN. + // Else SubVecVT is a fractional LMUL and may need to be slid down. + assert(RISCVVType::decodeVLMUL(getLMUL(SubVecVT)).second); // If the vector type is an LMUL-group type, extract a subvector equal to the - // nearest full vector register type. This should resolve to a EXTRACT_SUBREG - // instruction. + // nearest full vector register type. MVT InterSubVT = VecVT; if (VecVT.bitsGT(getLMUL1VT(VecVT))) { + // If VecVT has an LMUL > 1, then SubVecVT should have a smaller LMUL, and + // we should have successfully decomposed the extract into a subregister. + assert(SubRegIdx != RISCV::NoRegister); InterSubVT = getLMUL1VT(VecVT); - Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InterSubVT, Vec, - DAG.getConstant(OrigIdx - RemIdx, DL, XLenVT)); + Vec = DAG.getTargetExtractSubreg(SubRegIdx, DL, InterSubVT, Vec); } // Slide this vector register down by the desired number of elements in order From 3463e51a543a1526d7682cc2933e0257fd606b6b Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Mon, 11 Sep 2023 16:35:12 +0100 Subject: [PATCH 2/2] Use NoSubRegister instead of NoRegister --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 41d38a0d4483c..ad56bc757115f 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -8786,7 +8786,7 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op, if (VecVT.bitsGT(getLMUL1VT(VecVT))) { // If VecVT has an LMUL > 1, then SubVecVT should have a smaller LMUL, and // we should have successfully decomposed the extract into a subregister. - assert(SubRegIdx != RISCV::NoRegister); + assert(SubRegIdx != RISCV::NoSubRegister); InterSubVT = getLMUL1VT(VecVT); Vec = DAG.getTargetExtractSubreg(SubRegIdx, DL, InterSubVT, Vec); }