From 7054fac527dbeef9ac000119937e9eb4bad0ab29 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 6 Aug 2025 15:40:27 -0700 Subject: [PATCH] [llvm][RISCV] Add bf16 vfabs and vfneg intrinsics for zvfbfa. These are pseudoinstruction aliases for vfsgnjx and vfsgnjn. --- clang/include/clang/Basic/riscv_vector.td | 4 + .../zvfbfa/non-policy/non-overloaded/vfabs.c | 129 +++++++++ .../zvfbfa/non-policy/non-overloaded/vfneg.c | 129 +++++++++ .../zvfbfa/non-policy/overloaded/vfabs.c | 129 +++++++++ .../zvfbfa/non-policy/overloaded/vfneg.c | 129 +++++++++ .../zvfbfa/policy/non-overloaded/vfabs.c | 249 ++++++++++++++++++ .../zvfbfa/policy/non-overloaded/vfneg.c | 249 ++++++++++++++++++ .../zvfbfa/policy/overloaded/vfabs.c | 249 ++++++++++++++++++ .../zvfbfa/policy/overloaded/vfneg.c | 249 ++++++++++++++++++ 9 files changed, 1516 insertions(+) create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index 96d8300a0faf3..b45f863803968 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -1214,9 +1214,13 @@ defm vfsgnjx : RVVFloatingBinBuiltinSet; defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "fd">; let RequiredFeatures = ["zvfh"] in defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "x">; +let RequiredFeatures = ["zvfbfa"] in + defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "y">; defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "fd">; let RequiredFeatures = ["zvfh"] in defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "x">; +let RequiredFeatures = ["zvfbfa"] in + defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "y">; // 13.13. Vector Floating-Point Compare Instructions let MaskedPolicyScheme = HasPassthruOperand, diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c new file mode 100644 index 0000000000000..ae4a915c97a1d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c @@ -0,0 +1,129 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfa -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4(vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf4(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2(vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf2(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1(vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m1(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2(vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m2(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4(vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m4(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8(vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m8(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4_m(vbool64_t mask, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf4_m(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2_m(vbool32_t mask, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf2_m(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1_m(vbool16_t mask, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m1_m(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2_m(vbool8_t mask, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m2_m(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv16bf16.nxv16bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4_m(vbool4_t mask, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m4_m(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv32bf16.nxv32bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8_m(vbool2_t mask, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m8_m(mask, op1, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c new file mode 100644 index 0000000000000..7ecd853277ace --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c @@ -0,0 +1,129 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfa -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4(vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf4(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2(vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf2(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1(vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m1(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2(vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m2(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4(vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m4(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8(vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m8(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4_m(vbool64_t mask, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf4_m(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2_m(vbool32_t mask, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf2_m(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1_m(vbool16_t mask, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m1_m(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2_m(vbool8_t mask, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m2_m(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv16bf16.nxv16bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4_m(vbool4_t mask, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m4_m(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv32bf16.nxv32bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8_m(vbool2_t mask, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m8_m(mask, op1, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c new file mode 100644 index 0000000000000..975f0484b2198 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c @@ -0,0 +1,129 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfa -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4(vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2(vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1(vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2(vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4(vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8(vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4_m(vbool64_t mask, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2_m(vbool32_t mask, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1_m(vbool16_t mask, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2_m(vbool8_t mask, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv16bf16.nxv16bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4_m(vbool4_t mask, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv32bf16.nxv32bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8_m(vbool2_t mask, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs(mask, op1, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c new file mode 100644 index 0000000000000..a47d0d407fecb --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c @@ -0,0 +1,129 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfa -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4(vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2(vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1(vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2(vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4(vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( poison, [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8(vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg(op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4_m(vbool64_t mask, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2_m(vbool32_t mask, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1_m(vbool16_t mask, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2_m(vbool8_t mask, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv16bf16.nxv16bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4_m(vbool4_t mask, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg(mask, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv32bf16.nxv32bf16.i64( poison, [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8_m(vbool2_t mask, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg(mask, op1, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c new file mode 100644 index 0000000000000..f466ad6544bb6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfa -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4_tu(vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf4_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2_tu(vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf2_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1_tu(vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m1_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2_tu(vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m2_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4_tu(vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m4_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8_tu(vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m8_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4_tum(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf4_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2_tum(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf2_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1_tum(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m1_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2_tum(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m2_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4_tum(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m4_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8_tum(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m8_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4_tumu(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf4_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2_tumu(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf2_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1_tumu(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m1_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2_tumu(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m2_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4_tumu(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m4_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8_tumu(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m8_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4_mu(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf4_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2_mu(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16mf2_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1_mu(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m1_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2_mu(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m2_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4_mu(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m4_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8_mu(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs_v_bf16m8_mu(mask, maskedoff, op1, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c new file mode 100644 index 0000000000000..d83d680676896 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfa -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4_tu(vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf4_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2_tu(vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf2_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1_tu(vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m1_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2_tu(vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m2_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4_tu(vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m4_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8_tu(vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m8_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4_tum(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf4_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2_tum(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf2_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1_tum(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m1_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2_tum(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m2_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4_tum(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m4_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8_tum(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m8_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4_tumu(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf4_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2_tumu(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf2_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1_tumu(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m1_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2_tumu(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m2_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4_tumu(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m4_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8_tumu(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m8_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4_mu(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf4_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2_mu(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16mf2_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1_mu(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m1_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2_mu(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m2_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4_mu(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m4_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8_mu(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg_v_bf16m8_mu(mask, maskedoff, op1, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c new file mode 100644 index 0000000000000..8ff54022f9528 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfa -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4_tu(vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2_tu(vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1_tu(vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2_tu(vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4_tu(vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8_tu(vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4_tum(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2_tum(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1_tum(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2_tum(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4_tum(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8_tum(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4_tumu(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2_tumu(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1_tumu(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2_tumu(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4_tumu(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8_tumu(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfabs_v_bf16mf4_mu(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfabs_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfabs_v_bf16mf2_mu(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfabs_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfabs_v_bf16m1_mu(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfabs_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfabs_v_bf16m2_mu(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfabs_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfabs_v_bf16m4_mu(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfabs_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfabs_v_bf16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjx.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfabs_v_bf16m8_mu(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfabs_mu(mask, maskedoff, op1, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c new file mode 100644 index 0000000000000..7b5f87b6b797c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfa -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4_tu(vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2_tu(vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1_tu(vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2_tu(vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4_tu(vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8_tu +// CHECK-RV64-SAME: ( [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8_tu(vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg_tu(maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4_tum(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2_tum(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1_tum(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2_tum(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4_tum(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8_tum +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8_tum(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg_tum(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4_tumu(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2_tumu(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1_tumu(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2_tumu(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4_tumu(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8_tumu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8_tumu(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg_tumu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vfneg_v_bf16mf4_mu(vbool64_t mask, vbfloat16mf4_t maskedoff, vbfloat16mf4_t op1, size_t vl) { + return __riscv_vfneg_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vfneg_v_bf16mf2_mu(vbool32_t mask, vbfloat16mf2_t maskedoff, vbfloat16mf2_t op1, size_t vl) { + return __riscv_vfneg_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vfneg_v_bf16m1_mu(vbool16_t mask, vbfloat16m1_t maskedoff, vbfloat16m1_t op1, size_t vl) { + return __riscv_vfneg_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vfneg_v_bf16m2_mu(vbool8_t mask, vbfloat16m2_t maskedoff, vbfloat16m2_t op1, size_t vl) { + return __riscv_vfneg_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv16bf16.nxv16bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vfneg_v_bf16m4_mu(vbool4_t mask, vbfloat16m4_t maskedoff, vbfloat16m4_t op1, size_t vl) { + return __riscv_vfneg_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfneg_v_bf16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfsgnjn.mask.nxv32bf16.nxv32bf16.i64( [[MASKEDOFF]], [[OP1]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vfneg_v_bf16m8_mu(vbool2_t mask, vbfloat16m8_t maskedoff, vbfloat16m8_t op1, size_t vl) { + return __riscv_vfneg_mu(mask, maskedoff, op1, vl); +} +