From 973cccaf71bd6074208446e8082d34281bee87d5 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Wed, 3 Dec 2025 15:04:32 +0800 Subject: [PATCH 1/6] [RISCV] Add precommit test that copy is killed --- .../CodeGen/RISCV/rvv/vmerge-peephole.mir | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir index 338732c53aa3e..6f2eb744fc65e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir @@ -136,3 +136,30 @@ body: | %y:vrnov0 = COPY %x %z:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %y, %mask, %avl, 5 /* e32 */ ... +--- +name: copy_is_killed +body: | + bb.0: + liveins: $v0, $v8, $v9 + ; CHECK-LABEL: name: copy_is_killed + ; CHECK: liveins: $v0, $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = COPY $v8 + ; CHECK-NEXT: %y:vr = COPY $v9 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %add0:vr = PseudoVADD_VV_M1 $noreg, %x, %y, -1, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: %add1:vrnov0 = COPY killed %add:vrnov0 + ; CHECK-NEXT: %merge:vrnov0 = PseudoVOR_VV_M1_MASK %add:vrnov0, %add1, %y, %mask, -1, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: $v8 = COPY %merge + ; CHECK-NEXT: PseudoRET implicit $v8 + %x:vr = COPY $v8 + %y:vr = COPY $v9 + %mask:vmv0 = COPY $v0 + %add0:vr = PseudoVADD_VV_M1 $noreg, %x:vr, %y:vr, -1, 5, 3 + %add1:vrnov0 = COPY killed %add:vr + %or:vrnov0 = PseudoVOR_VV_M1 $noreg, %add1:vrnov0, %y:vr, -1, 5, 3 + %merge:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %add1:vrnov0, killed %or:vrnov0, killed %mask:vmv0, -1, 5 /* e32 */ + $v8 = COPY %merge:vrnov0 + PseudoRET implicit $v8 +... + From 38ad8f6f2ea68111526ae321beb896872aecf528 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Wed, 3 Dec 2025 15:09:19 +0800 Subject: [PATCH 2/6] [RISCV] Clear kill flags for FalseReg in foldVMergeToMask Or we can't pass the MachineVerifier because of using a killed virtual register. This was found when backporting #170070 to 21.x branch. --- llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 2 ++ llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp index 5acb7f5bcd56a..66001ff8cbd03 100644 --- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp +++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp @@ -834,6 +834,8 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const { MRI->constrainRegClass( MO.getReg(), True.getRegClassConstraint(MO.getOperandNo(), TII, TRI)); } + // We should clear the IsKill flag since we have an use now. + MRI->clearKillFlags(FalseReg); MI.eraseFromParent(); return true; diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir index 6f2eb744fc65e..59a4cccf29c35 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir @@ -148,7 +148,7 @@ body: | ; CHECK-NEXT: %y:vr = COPY $v9 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 ; CHECK-NEXT: %add0:vr = PseudoVADD_VV_M1 $noreg, %x, %y, -1, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: %add1:vrnov0 = COPY killed %add:vrnov0 + ; CHECK-NEXT: %add1:vrnov0 = COPY %add:vrnov0 ; CHECK-NEXT: %merge:vrnov0 = PseudoVOR_VV_M1_MASK %add:vrnov0, %add1, %y, %mask, -1, 5 /* e32 */, 1 /* ta, mu */ ; CHECK-NEXT: $v8 = COPY %merge ; CHECK-NEXT: PseudoRET implicit $v8 From 6005bae1214656ce7ebbd9018f7c4bc06eae5520 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Wed, 3 Dec 2025 17:13:39 +0800 Subject: [PATCH 3/6] Add precommit test for multiple use --- .../CodeGen/RISCV/rvv/vmerge-peephole.mir | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir index 59a4cccf29c35..71419159fcc5f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir @@ -162,4 +162,24 @@ body: | $v8 = COPY %merge:vrnov0 PseudoRET implicit $v8 ... - +--- +name: copy_multiple_use +body: | + bb.0: + liveins: $x8, $v0, $v8 + ; CHECK-LABEL: name: copy_multiple_use + ; CHECK: liveins: $x8, $v0, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %copy:vrnov0 = COPY %y + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %y:vrnov0 = PseudoVLE32_V_M1_MASK %passthru, $noreg, %mask, %avl, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: PseudoVSE8_V_M1 %copy, $noreg, %avl, 5 /* e32 */ + %avl:gprnox0 = COPY $x8 + %passthru:vrnov0 = COPY $v8 + %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) + %copy:vrnov0 = COPY %x + %mask:vmv0 = COPY $v0 + PseudoVSE8_V_M1 %copy, $noreg, %avl, 5 /* e8 */ + %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %copy, %mask, %avl, 5 /* e32 */ From 1f216ed092a152dc7760903fe350606a6de94d9f Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Wed, 3 Dec 2025 18:17:20 +0800 Subject: [PATCH 4/6] look through COPYs with one non-debug use --- llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 10 +++++++--- llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir | 5 +++-- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp index 66001ff8cbd03..0b4227da3926e 100644 --- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp +++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp @@ -73,7 +73,7 @@ class RISCVVectorPeephole : public MachineFunctionPass { bool isAllOnesMask(const MachineInstr *MaskDef) const; std::optional getConstant(const MachineOperand &VL) const; bool ensureDominates(const MachineOperand &Use, MachineInstr &Src) const; - Register lookThruCopies(Register Reg) const; + Register lookThruCopies(Register Reg, bool OneUseOnly = false) const; }; } // namespace @@ -389,13 +389,16 @@ bool RISCVVectorPeephole::convertAllOnesVMergeToVMv(MachineInstr &MI) const { // If \p Reg is defined by one or more COPYs of virtual registers, traverses // the chain and returns the root non-COPY source. -Register RISCVVectorPeephole::lookThruCopies(Register Reg) const { +Register RISCVVectorPeephole::lookThruCopies(Register Reg, + bool OneUseOnly) const { while (MachineInstr *Def = MRI->getUniqueVRegDef(Reg)) { if (!Def->isFullCopy()) break; Register Src = Def->getOperand(1).getReg(); if (!Src.isVirtual()) break; + if (OneUseOnly && !MRI->hasOneNonDBGUse(Reg)) + break; Reg = Src; } return Reg; @@ -715,7 +718,8 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const { Register PassthruReg = lookThruCopies(MI.getOperand(1).getReg()); Register FalseReg = lookThruCopies(MI.getOperand(2).getReg()); - Register TrueReg = lookThruCopies(MI.getOperand(3).getReg()); + Register TrueReg = + lookThruCopies(MI.getOperand(3).getReg(), /*OneUseOnly=*/true); if (!TrueReg.isVirtual() || !MRI->hasOneUse(TrueReg)) return false; MachineInstr &True = *MRI->getUniqueVRegDef(TrueReg); diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir index 71419159fcc5f..e462fef59f148 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir @@ -172,10 +172,11 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 - ; CHECK-NEXT: %copy:vrnov0 = COPY %y + ; CHECK-NEXT: %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %copy:vrnov0 = COPY %x ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %y:vrnov0 = PseudoVLE32_V_M1_MASK %passthru, $noreg, %mask, %avl, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) ; CHECK-NEXT: PseudoVSE8_V_M1 %copy, $noreg, %avl, 5 /* e32 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %copy, %mask, %avl, 5 /* e32 */ %avl:gprnox0 = COPY $x8 %passthru:vrnov0 = COPY $v8 %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) From 40704538f8babc09ec77af156db6ef8fd9c6feb4 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Wed, 3 Dec 2025 19:33:55 +0800 Subject: [PATCH 5/6] Apply suggestions --- llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 2 +- llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp index 0b4227da3926e..6ddca4a3e0909 100644 --- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp +++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp @@ -838,7 +838,7 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const { MRI->constrainRegClass( MO.getReg(), True.getRegClassConstraint(MO.getOperandNo(), TII, TRI)); } - // We should clear the IsKill flag since we have an use now. + // We should clear the IsKill flag since we have a new use now. MRI->clearKillFlags(FalseReg); MI.eraseFromParent(); diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir index e462fef59f148..234218103adce 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir @@ -159,8 +159,7 @@ body: | %add1:vrnov0 = COPY killed %add:vr %or:vrnov0 = PseudoVOR_VV_M1 $noreg, %add1:vrnov0, %y:vr, -1, 5, 3 %merge:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %add1:vrnov0, killed %or:vrnov0, killed %mask:vmv0, -1, 5 /* e32 */ - $v8 = COPY %merge:vrnov0 - PseudoRET implicit $v8 + ... --- name: copy_multiple_use From 3b5e1032b7cf7c97e2c017984a0206c5d4d0672b Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Wed, 3 Dec 2025 19:37:28 +0800 Subject: [PATCH 6/6] update test --- llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir index 234218103adce..81a271bd975e3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir @@ -150,8 +150,6 @@ body: | ; CHECK-NEXT: %add0:vr = PseudoVADD_VV_M1 $noreg, %x, %y, -1, 5 /* e32 */, 3 /* ta, ma */ ; CHECK-NEXT: %add1:vrnov0 = COPY %add:vrnov0 ; CHECK-NEXT: %merge:vrnov0 = PseudoVOR_VV_M1_MASK %add:vrnov0, %add1, %y, %mask, -1, 5 /* e32 */, 1 /* ta, mu */ - ; CHECK-NEXT: $v8 = COPY %merge - ; CHECK-NEXT: PseudoRET implicit $v8 %x:vr = COPY $v8 %y:vr = COPY $v9 %mask:vmv0 = COPY $v0