From b127324c314288ebf7989facc0b3646cfbd2a261 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 5 Aug 2025 01:45:48 +0300 Subject: [PATCH 1/4] [Xtensa] Implement Xtensa S32C1I Option and atomics lowering. Implement Xtensa S32C1I Option and use s32c1i instruction to implement atomics operations. --- .../Disassembler/XtensaDisassembler.cpp | 67 +- .../MCTargetDesc/XtensaMCTargetDesc.cpp | 3 + llvm/lib/Target/Xtensa/XtensaFeatures.td | 16 + llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 863 +++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 19 + llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 158 + llvm/lib/Target/Xtensa/XtensaOperators.td | 5 + llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 10 +- llvm/lib/Target/Xtensa/XtensaSubtarget.h | 2 + .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 6 + llvm/test/CodeGen/Xtensa/atomic-load-store.ll | 498 ++ llvm/test/CodeGen/Xtensa/atomic-rmw.ll | 4728 +++++++++++++++++ llvm/test/CodeGen/Xtensa/forced-atomics.ll | 1288 +++++ 13 files changed, 7628 insertions(+), 35 deletions(-) create mode 100644 llvm/test/CodeGen/Xtensa/atomic-load-store.ll create mode 100644 llvm/test/CodeGen/Xtensa/atomic-rmw.ll create mode 100644 llvm/test/CodeGen/Xtensa/forced-atomics.ll diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 2f92f8606fb48..39bec4785c61c 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -145,39 +145,40 @@ struct DecodeRegister { }; const DecodeRegister SRDecoderTable[] = { - {Xtensa::LBEG, 0}, {Xtensa::LEND, 1}, - {Xtensa::LCOUNT, 2}, {Xtensa::SAR, 3}, - {Xtensa::BREG, 4}, {Xtensa::LITBASE, 5}, - {Xtensa::ACCLO, 16}, {Xtensa::ACCHI, 17}, - {Xtensa::M0, 32}, {Xtensa::M1, 33}, - {Xtensa::M2, 34}, {Xtensa::M3, 35}, - {Xtensa::WINDOWBASE, 72}, {Xtensa::WINDOWSTART, 73}, - {Xtensa::IBREAKENABLE, 96}, {Xtensa::MEMCTL, 97}, - {Xtensa::DDR, 104}, {Xtensa::IBREAKA0, 128}, - {Xtensa::IBREAKA1, 129}, {Xtensa::DBREAKA0, 144}, - {Xtensa::DBREAKA1, 145}, {Xtensa::DBREAKC0, 160}, - {Xtensa::DBREAKC1, 161}, {Xtensa::CONFIGID0, 176}, - {Xtensa::EPC1, 177}, {Xtensa::EPC2, 178}, - {Xtensa::EPC3, 179}, {Xtensa::EPC4, 180}, - {Xtensa::EPC5, 181}, {Xtensa::EPC6, 182}, - {Xtensa::EPC7, 183}, {Xtensa::DEPC, 192}, - {Xtensa::EPS2, 194}, {Xtensa::EPS3, 195}, - {Xtensa::EPS4, 196}, {Xtensa::EPS5, 197}, - {Xtensa::EPS6, 198}, {Xtensa::EPS7, 199}, - {Xtensa::CONFIGID1, 208}, {Xtensa::EXCSAVE1, 209}, - {Xtensa::EXCSAVE2, 210}, {Xtensa::EXCSAVE3, 211}, - {Xtensa::EXCSAVE4, 212}, {Xtensa::EXCSAVE5, 213}, - {Xtensa::EXCSAVE6, 214}, {Xtensa::EXCSAVE7, 215}, - {Xtensa::CPENABLE, 224}, {Xtensa::INTERRUPT, 226}, - {Xtensa::INTCLEAR, 227}, {Xtensa::INTENABLE, 228}, - {Xtensa::PS, 230}, {Xtensa::VECBASE, 231}, - {Xtensa::EXCCAUSE, 232}, {Xtensa::DEBUGCAUSE, 233}, - {Xtensa::CCOUNT, 234}, {Xtensa::PRID, 235}, - {Xtensa::ICOUNT, 236}, {Xtensa::ICOUNTLEVEL, 237}, - {Xtensa::EXCVADDR, 238}, {Xtensa::CCOMPARE0, 240}, - {Xtensa::CCOMPARE1, 241}, {Xtensa::CCOMPARE2, 242}, - {Xtensa::MISC0, 244}, {Xtensa::MISC1, 245}, - {Xtensa::MISC2, 246}, {Xtensa::MISC3, 247}}; + {Xtensa::LBEG, 0}, {Xtensa::LEND, 1}, + {Xtensa::LCOUNT, 2}, {Xtensa::SAR, 3}, + {Xtensa::BREG, 4}, {Xtensa::LITBASE, 5}, + {Xtensa::SCOMPARE1, 12}, {Xtensa::ACCLO, 16}, + {Xtensa::ACCHI, 17}, {Xtensa::M0, 32}, + {Xtensa::M1, 33}, {Xtensa::M2, 34}, + {Xtensa::M3, 35}, {Xtensa::WINDOWBASE, 72}, + {Xtensa::WINDOWSTART, 73}, {Xtensa::IBREAKENABLE, 96}, + {Xtensa::MEMCTL, 97}, {Xtensa::ATOMCTL, 99}, + {Xtensa::DDR, 104}, {Xtensa::IBREAKA0, 128}, + {Xtensa::IBREAKA1, 129}, {Xtensa::DBREAKA0, 144}, + {Xtensa::DBREAKA1, 145}, {Xtensa::DBREAKC0, 160}, + {Xtensa::DBREAKC1, 161}, {Xtensa::CONFIGID0, 176}, + {Xtensa::EPC1, 177}, {Xtensa::EPC2, 178}, + {Xtensa::EPC3, 179}, {Xtensa::EPC4, 180}, + {Xtensa::EPC5, 181}, {Xtensa::EPC6, 182}, + {Xtensa::EPC7, 183}, {Xtensa::DEPC, 192}, + {Xtensa::EPS2, 194}, {Xtensa::EPS3, 195}, + {Xtensa::EPS4, 196}, {Xtensa::EPS5, 197}, + {Xtensa::EPS6, 198}, {Xtensa::EPS7, 199}, + {Xtensa::CONFIGID1, 208}, {Xtensa::EXCSAVE1, 209}, + {Xtensa::EXCSAVE2, 210}, {Xtensa::EXCSAVE3, 211}, + {Xtensa::EXCSAVE4, 212}, {Xtensa::EXCSAVE5, 213}, + {Xtensa::EXCSAVE6, 214}, {Xtensa::EXCSAVE7, 215}, + {Xtensa::CPENABLE, 224}, {Xtensa::INTERRUPT, 226}, + {Xtensa::INTCLEAR, 227}, {Xtensa::INTENABLE, 228}, + {Xtensa::PS, 230}, {Xtensa::VECBASE, 231}, + {Xtensa::EXCCAUSE, 232}, {Xtensa::DEBUGCAUSE, 233}, + {Xtensa::CCOUNT, 234}, {Xtensa::PRID, 235}, + {Xtensa::ICOUNT, 236}, {Xtensa::ICOUNTLEVEL, 237}, + {Xtensa::EXCVADDR, 238}, {Xtensa::CCOMPARE0, 240}, + {Xtensa::CCOMPARE1, 241}, {Xtensa::CCOMPARE2, 242}, + {Xtensa::MISC0, 244}, {Xtensa::MISC1, 245}, + {Xtensa::MISC2, 246}, {Xtensa::MISC3, 247}}; static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp index 821cba0fc25c2..080a9c0bdd9e0 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp @@ -200,6 +200,9 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits, case Xtensa::WINDOWBASE: case Xtensa::WINDOWSTART: return FeatureBits[Xtensa::FeatureWindowed]; + case Xtensa::ATOMCTL: + case Xtensa::SCOMPARE1: + return FeatureBits[Xtensa::FeatureWindowed]; case Xtensa::NoRegister: return false; } diff --git a/llvm/lib/Target/Xtensa/XtensaFeatures.td b/llvm/lib/Target/Xtensa/XtensaFeatures.td index 97d5472f3e96c..d6f3ef0f15e32 100644 --- a/llvm/lib/Target/Xtensa/XtensaFeatures.td +++ b/llvm/lib/Target/Xtensa/XtensaFeatures.td @@ -73,6 +73,22 @@ def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true", def HasDiv32 : Predicate<"Subtarget->hasDiv32()">, AssemblerPredicate<(all_of FeatureDiv32)>; +def FeatureS32C1I : SubtargetFeature<"s32c1i", "HasS32C1I", "true", + "Enable Xtensa S32C1I option">; +def HasS32C1I : Predicate<"Subtarget->hasS32C1I()">, + AssemblerPredicate<(all_of FeatureS32C1I)>; + +// Assume that lock-free native-width atomics are available, even if the target +// and operating system combination would not usually provide them. The user +// is responsible for providing any necessary __sync implementations. Code +// built with this feature is not ABI-compatible with code built without this +// feature, if atomic variables are exposed across the ABI boundary. +def FeatureForcedAtomics : SubtargetFeature<"forced-atomics", "HasForcedAtomics", "true", + "Assume that lock-free native-width atomics are available">; +def HasForcedAtomics : Predicate<"Subtarget->hasForcedAtomics()">, + AssemblerPredicate<(all_of FeatureForcedAtomics)>; +def HasAtomicLdSt : Predicate<"Subtarget->hasS32C1I() || Subtarget->hasForcedAtomics()">; + def FeatureRegionProtection : SubtargetFeature<"regprotect", "HasRegionProtection", "true", "Enable Xtensa Region Protection option">; def HasRegionProtection : Predicate<"Subtarget->hasRegionProtection()">, diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index fd42fd2e010ba..c56327b8c7334 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -250,6 +250,40 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM, // Floating-point truncation and stores need to be done separately. setTruncStoreAction(MVT::f64, MVT::f32, Expand); + // to have the best chance and doing something good with fences custom lower + // them + setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); + + if (!Subtarget.hasS32C1I()) { + for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE; + I <= MVT::LAST_INTEGER_VALUETYPE; ++I) { + MVT VT = MVT::SimpleValueType(I); + if (isTypeLegal(VT)) { + setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); + setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand); + } + } + } + + if (Subtarget.hasS32C1I()) { + setMaxAtomicSizeInBitsSupported(32); + setMinCmpXchgSizeInBits(32); + } else if (Subtarget.hasForcedAtomics()) { + setMaxAtomicSizeInBitsSupported(32); + } else { + setMaxAtomicSizeInBitsSupported(0); + } + // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); } @@ -1448,6 +1482,13 @@ bool XtensaTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT, return false; } +SDValue XtensaTargetLowering::LowerATOMIC_FENCE(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Chain = Op.getOperand(0); + return DAG.getNode(XtensaISD::MEMW, DL, MVT::Other, Chain); +} + SDValue XtensaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { @@ -1491,6 +1532,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerShiftRightParts(Op, DAG, true); case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false); + case ISD::ATOMIC_FENCE: + return LowerATOMIC_FENCE(Op, DAG); default: report_fatal_error("Unexpected node to lower"); } @@ -1630,6 +1673,731 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI, return SinkMBB; } +// Emit instructions for atomic_cmp_swap node for 8/16 bit operands +MachineBasicBlock * +XtensaTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, MachineBasicBlock *BB, + int isByteOperand) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + + MachineBasicBlock *thisBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(It, BBLoop); + F->insert(It, BBExit); + + // Transfer the remainder of BB and its successor edges to BBExit. + BBExit->splice(BBExit->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + BBExit->transferSuccessorsAndUpdatePHIs(BB); + + BB->addSuccessor(BBLoop); + + MachineOperand &Res = MI.getOperand(0); + MachineOperand &AtomValAddr = MI.getOperand(1); + MachineOperand &CmpVal = MI.getOperand(2); + MachineOperand &SwpVal = MI.getOperand(3); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R1).addImm(3); + + unsigned ByteOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), ByteOffs) + .addReg(R1) + .addReg(AtomValAddr.getReg()); + + unsigned AddrAlign = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SUB), AddrAlign) + .addReg(AtomValAddr.getReg()) + .addReg(ByteOffs); + + unsigned BitOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), BitOffs) + .addReg(ByteOffs) + .addImm(3); + + unsigned Mask1 = MRI.createVirtualRegister(RC); + if (isByteOperand) { + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), Mask1).addImm(0xff); + } else { + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(1); + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), R3).addReg(R2).addImm(16); + BuildMI(*BB, MI, DL, TII.get(Xtensa::ADDI), Mask1).addReg(R3).addImm(-1); + } + + BuildMI(*BB, MI, DL, TII.get(Xtensa::SSL)).addReg(BitOffs); + + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(-1); + + unsigned Mask2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Mask2).addReg(Mask1); + + unsigned Mask3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::XOR), Mask3).addReg(Mask2).addReg(R2); + + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R3).addReg(AddrAlign).addImm(0); + + unsigned R4 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), R4).addReg(R3).addReg(Mask3); + + unsigned Cmp1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Cmp1).addReg(CmpVal.getReg()); + + unsigned Swp1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Swp1).addReg(SwpVal.getReg()); + + BB = BBLoop; + + unsigned MaskPhi = MRI.createVirtualRegister(RC); + unsigned MaskLoop = MRI.createVirtualRegister(RC); + + BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), MaskPhi) + .addReg(MaskLoop) + .addMBB(BBLoop) + .addReg(R4) + .addMBB(thisBB); + + unsigned Cmp2 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), Cmp2).addReg(Cmp1).addReg(MaskPhi); + + unsigned Swp2 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), Swp2).addReg(Swp1).addReg(MaskPhi); + + BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(Cmp2); + + unsigned Swp3 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::S32C1I), Swp3) + .addReg(Swp2) + .addReg(AddrAlign) + .addImm(0); + + BuildMI(BB, DL, TII.get(Xtensa::AND), MaskLoop).addReg(Swp3).addReg(Mask3); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(MaskLoop) + .addReg(MaskPhi) + .addMBB(BBLoop); + + BB->addSuccessor(BBLoop); + BB->addSuccessor(BBExit); + + BB = BBExit; + auto St = BBExit->begin(); + + unsigned R5 = MRI.createVirtualRegister(RC); + BuildMI(*BB, St, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); + + BuildMI(*BB, St, DL, TII.get(Xtensa::SRL), R5).addReg(Swp3); + + BuildMI(*BB, St, DL, TII.get(Xtensa::AND), Res.getReg()) + .addReg(R5) + .addReg(Mask1); + + MI.eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + +// Emit instructions for atomic_swap node for 8/16 bit operands +MachineBasicBlock * +XtensaTargetLowering::emitAtomicSwap(MachineInstr &MI, MachineBasicBlock *BB, + int isByteOperand) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + + MachineFunction *F = BB->getParent(); + MachineBasicBlock *BBLoop1 = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBLoop2 = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBLoop3 = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBLoop4 = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(It, BBLoop1); + F->insert(It, BBLoop2); + F->insert(It, BBLoop3); + F->insert(It, BBLoop4); + F->insert(It, BBExit); + + // Transfer the remainder of BB and its successor edges to BBExit. + BBExit->splice(BBExit->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + BBExit->transferSuccessorsAndUpdatePHIs(BB); + + BB->addSuccessor(BBLoop1); + BBLoop1->addSuccessor(BBLoop2); + BBLoop2->addSuccessor(BBLoop3); + BBLoop2->addSuccessor(BBLoop4); + BBLoop3->addSuccessor(BBLoop2); + BBLoop3->addSuccessor(BBLoop4); + BBLoop4->addSuccessor(BBLoop1); + BBLoop4->addSuccessor(BBExit); + + MachineOperand &Res = MI.getOperand(0); + MachineOperand &AtomValAddr = MI.getOperand(1); + MachineOperand &SwpVal = MI.getOperand(2); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R1).addImm(3); + + unsigned ByteOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), ByteOffs) + .addReg(R1) + .addReg(AtomValAddr.getReg()); + + unsigned AddrAlign = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SUB), AddrAlign) + .addReg(AtomValAddr.getReg()) + .addReg(ByteOffs); + + unsigned BitOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), BitOffs) + .addReg(ByteOffs) + .addImm(3); + + unsigned Mask1 = MRI.createVirtualRegister(RC); + if (isByteOperand) { + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), Mask1).addImm(0xff); + } else { + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(1); + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), R3).addReg(R2).addImm(16); + BuildMI(*BB, MI, DL, TII.get(Xtensa::ADDI), Mask1).addReg(R3).addImm(-1); + } + + BuildMI(*BB, MI, DL, TII.get(Xtensa::SSL)).addReg(BitOffs); + + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(-1); + + unsigned Mask2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Mask2).addReg(Mask1); + + unsigned Mask3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::XOR), Mask3).addReg(Mask2).addReg(R2); + + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R3).addReg(AddrAlign).addImm(0); + + unsigned R4 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), R4).addReg(R3).addReg(Mask3); + + unsigned SwpValShifted = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), SwpValShifted) + .addReg(SwpVal.getReg()); + + unsigned R5 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R5).addReg(AddrAlign).addImm(0); + + unsigned AtomVal = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), AtomVal).addReg(R5).addReg(Mask2); + + unsigned AtomValPhi = MRI.createVirtualRegister(RC); + unsigned AtomValLoop = MRI.createVirtualRegister(RC); + + BuildMI(*BBLoop1, BBLoop1->begin(), DL, TII.get(Xtensa::PHI), AtomValPhi) + .addReg(AtomValLoop) + .addMBB(BBLoop4) + .addReg(AtomVal) + .addMBB(BB); + + BB = BBLoop1; + + BuildMI(BB, DL, TII.get(Xtensa::MEMW)); + + unsigned R6 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::L32I), R6).addReg(AddrAlign).addImm(0); + + unsigned R7 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R7).addReg(R6).addReg(Mask3); + + unsigned MaskPhi = MRI.createVirtualRegister(RC); + unsigned MaskLoop = MRI.createVirtualRegister(RC); + + BuildMI(*BBLoop2, BBLoop2->begin(), DL, TII.get(Xtensa::PHI), MaskPhi) + .addReg(MaskLoop) + .addMBB(BBLoop3) + .addReg(R7) + .addMBB(BBLoop1); + + BB = BBLoop2; + + unsigned Swp1 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), Swp1) + .addReg(SwpValShifted) + .addReg(MaskPhi); + + unsigned AtomVal1 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), AtomVal1) + .addReg(AtomValPhi) + .addReg(MaskPhi); + + BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(AtomVal1); + + unsigned Swp2 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::S32C1I), Swp2) + .addReg(Swp1) + .addReg(AddrAlign) + .addImm(0); + + BuildMI(BB, DL, TII.get(Xtensa::BEQ)) + .addReg(AtomVal1) + .addReg(Swp2) + .addMBB(BBLoop4); + + BB = BBLoop3; + + BuildMI(BB, DL, TII.get(Xtensa::AND), MaskLoop).addReg(Swp2).addReg(Mask3); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(MaskLoop) + .addReg(MaskPhi) + .addMBB(BBLoop2); + + BB = BBLoop4; + + BuildMI(BB, DL, TII.get(Xtensa::AND), AtomValLoop).addReg(Swp2).addReg(Mask2); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(AtomValLoop) + .addReg(AtomValPhi) + .addMBB(BBLoop1); + + BB = BBExit; + + auto St = BB->begin(); + + unsigned R8 = MRI.createVirtualRegister(RC); + + BuildMI(*BB, St, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); + BuildMI(*BB, St, DL, TII.get(Xtensa::SRL), R8).addReg(AtomValLoop); + + if (isByteOperand) { + BuildMI(*BB, St, DL, TII.get(Xtensa::SEXT), Res.getReg()) + .addReg(R8) + .addImm(7); + } else { + BuildMI(*BB, St, DL, TII.get(Xtensa::SEXT), Res.getReg()) + .addReg(R8) + .addImm(15); + } + + MI.eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + +// Emit instructions for atomic_swap node for 32 bit operands +MachineBasicBlock * +XtensaTargetLowering::emitAtomicSwap(MachineInstr &MI, + MachineBasicBlock *BB) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + + MachineFunction *F = BB->getParent(); + MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(It, BBLoop); + F->insert(It, BBExit); + + // Transfer the remainder of BB and its successor edges to BBExit. + BBExit->splice(BBExit->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + BBExit->transferSuccessorsAndUpdatePHIs(BB); + + BB->addSuccessor(BBLoop); + BBLoop->addSuccessor(BBLoop); + BBLoop->addSuccessor(BBExit); + + MachineOperand &Res = MI.getOperand(0); + MachineOperand &AtomValAddr = MI.getOperand(1); + MachineOperand &SwpVal = MI.getOperand(2); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + + BuildMI(*BB, MI, DL, TII.get(Xtensa::MEMW)); + + unsigned AtomVal = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), AtomVal) + .addReg(AtomValAddr.getReg()) + .addImm(0); + + unsigned AtomValLoop = MRI.createVirtualRegister(RC); + + BuildMI(*BBLoop, BBLoop->begin(), DL, TII.get(Xtensa::PHI), Res.getReg()) + .addReg(AtomValLoop) + .addMBB(BBLoop) + .addReg(AtomVal) + .addMBB(BB); + + BB = BBLoop; + + BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(Res.getReg()); + + BuildMI(BB, DL, TII.get(Xtensa::S32C1I), AtomValLoop) + .addReg(SwpVal.getReg()) + .addReg(AtomValAddr.getReg()) + .addImm(0); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(AtomValLoop) + .addReg(Res.getReg()) + .addMBB(BBLoop); + + MI.eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + +MachineBasicBlock *XtensaTargetLowering::emitAtomicRMW(MachineInstr &MI, + MachineBasicBlock *BB, + unsigned Opcode, + bool inv, + bool minmax) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + + MachineBasicBlock *ThisBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(It, BBLoop); + F->insert(It, BBExit); + + // Transfer the remainder of BB and its successor edges to BB2. + BBExit->splice(BBExit->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + BBExit->transferSuccessorsAndUpdatePHIs(BB); + + BB->addSuccessor(BBLoop); + + MachineOperand &Res = MI.getOperand(0); + MachineOperand &AtomicValAddr = MI.getOperand(1); + MachineOperand &Val = MI.getOperand(2); + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R1) + .addReg(AtomicValAddr.getReg()) + .addImm(0); + + BB = BBLoop; + + unsigned AtomicValPhi = MRI.createVirtualRegister(RC); + unsigned AtomicValLoop = MRI.createVirtualRegister(RC); + unsigned R2 = MRI.createVirtualRegister(RC); + + if (minmax) { + MachineBasicBlock *BBLoop1 = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(++BB->getIterator(), BBLoop1); + BB->addSuccessor(BBLoop1); + MachineBasicBlock *BBLoop2 = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(++BB->getIterator(), BBLoop2); + BB->addSuccessor(BBLoop2); + BBLoop2->addSuccessor(BBLoop1); + + BuildMI(BB, DL, TII.get(Opcode)) + .addReg(AtomicValPhi) + .addReg(Val.getReg()) + .addMBB(BBLoop1); + + unsigned R7 = MRI.createVirtualRegister(RC); + BuildMI(BBLoop2, DL, TII.get(Xtensa::MOV_N), R7).addReg(Val.getReg()); + + BB = BBLoop1; + unsigned R8 = MRI.createVirtualRegister(RC); + BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), R8) + .addReg(R7) + .addMBB(BBLoop2) + .addReg(AtomicValPhi) + .addMBB(BBLoop); + BuildMI(BB, DL, TII.get(Xtensa::MOV_N), R2).addReg(R8); + } else { + BuildMI(BB, DL, TII.get(Opcode), R2) + .addReg(AtomicValPhi) + .addReg(Val.getReg()); + if (inv) { + unsigned Rtmp1 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::MOVI), Rtmp1).addImm(-1); + unsigned Rtmp2 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::XOR), Rtmp2).addReg(R2).addReg(Rtmp1); + R2 = Rtmp2; + } + } + + BuildMI(*BBLoop, BBLoop->begin(), DL, TII.get(Xtensa::PHI), AtomicValPhi) + .addReg(AtomicValLoop) + .addMBB(BB) + .addReg(R1) + .addMBB(ThisBB); + + unsigned R4 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(AtomicValPhi); + BuildMI(BB, DL, TII.get(Xtensa::S32C1I), R4) + .addReg(R2) + .addReg(AtomicValAddr.getReg(), getKillRegState(AtomicValAddr.isDead())) + .addImm(0); + + BuildMI(BB, DL, TII.get(Xtensa::MOV_N), AtomicValLoop).addReg(R4); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(AtomicValPhi) + .addReg(R4) + .addMBB(BBLoop); + + BB->addSuccessor(BBLoop); + BB->addSuccessor(BBExit); + + BB = BBExit; + auto St = BBExit->begin(); + + BuildMI(*BB, St, DL, TII.get(Xtensa::MOV_N), Res.getReg()).addReg(R4); + + MI.eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + +MachineBasicBlock * +XtensaTargetLowering::emitAtomicRMW(MachineInstr &MI, MachineBasicBlock *BB, + bool isByteOperand, unsigned Opcode, + bool inv, bool minmax) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + + MachineBasicBlock *ThisBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(It, BBLoop); + F->insert(It, BBExit); + + // Transfer the remainder of BB and its successor edges to BB2. + BBExit->splice(BBExit->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + BBExit->transferSuccessorsAndUpdatePHIs(BB); + + BB->addSuccessor(BBLoop); + + MachineOperand &Res = MI.getOperand(0); + MachineOperand &AtomValAddr = MI.getOperand(1); + MachineOperand &Val = MI.getOperand(2); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R1).addImm(3); + + unsigned ByteOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), ByteOffs) + .addReg(R1) + .addReg(AtomValAddr.getReg()); + + unsigned AddrAlign = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SUB), AddrAlign) + .addReg(AtomValAddr.getReg()) + .addReg(ByteOffs); + + unsigned BitOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), BitOffs) + .addReg(ByteOffs) + .addImm(3); + + unsigned Mask1 = MRI.createVirtualRegister(RC); + if (isByteOperand) { + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), Mask1).addImm(0xff); + } else { + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(1); + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), R3).addReg(R2).addImm(16); + BuildMI(*BB, MI, DL, TII.get(Xtensa::ADDI), Mask1).addReg(R3).addImm(-1); + } + + BuildMI(*BB, MI, DL, TII.get(Xtensa::SSL)).addReg(BitOffs); + + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(-1); + + unsigned Mask2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Mask2).addReg(Mask1); + + unsigned Mask3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::XOR), Mask3).addReg(Mask2).addReg(R2); + + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R3).addReg(AddrAlign).addImm(0); + + unsigned Val1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Val1).addReg(Val.getReg()); + + BB = BBLoop; + + unsigned AtomicValPhi = MRI.createVirtualRegister(RC); + unsigned AtomicValLoop = MRI.createVirtualRegister(RC); + unsigned Swp2; + + if (minmax) { + MachineBasicBlock *BBLoop1 = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(++BB->getIterator(), BBLoop1); + BB->addSuccessor(BBLoop1); + MachineBasicBlock *BBLoop2 = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(++BB->getIterator(), BBLoop2); + BB->addSuccessor(BBLoop2); + BBLoop2->addSuccessor(BBLoop1); + + unsigned R1 = MRI.createVirtualRegister(RC); + unsigned R2 = MRI.createVirtualRegister(RC); + unsigned R3 = MRI.createVirtualRegister(RC); + unsigned R4 = MRI.createVirtualRegister(RC); + + unsigned R5 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R5) + .addReg(AtomicValPhi) + .addReg(Mask2); + + BuildMI(BB, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); + BuildMI(BB, DL, TII.get(Xtensa::SRL), R1).addReg(R5); + BuildMI(BB, DL, TII.get(Xtensa::SRL), R2).addReg(Val1); + + if ((Opcode == Xtensa::BLT) || (Opcode == Xtensa::BGE)) { + if (isByteOperand) { + BuildMI(BB, DL, TII.get(Xtensa::SEXT), R3).addReg(R1).addImm(7); + BuildMI(BB, DL, TII.get(Xtensa::SEXT), R4).addReg(R2).addImm(7); + } else { + BuildMI(BB, DL, TII.get(Xtensa::SEXT), R3).addReg(R1).addImm(15); + BuildMI(BB, DL, TII.get(Xtensa::SEXT), R4).addReg(R2).addImm(15); + } + } else { + R3 = R1; + R4 = R2; + } + + BuildMI(BB, DL, TII.get(Opcode)).addReg(R3).addReg(R4).addMBB(BBLoop1); + unsigned R7 = MRI.createVirtualRegister(RC); + BuildMI(BBLoop2, DL, TII.get(Xtensa::MOV_N), R7).addReg(Val1); + + BB = BBLoop1; + unsigned R9 = MRI.createVirtualRegister(RC); + BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), R9) + .addReg(R7) + .addMBB(BBLoop2) + .addReg(AtomicValPhi) + .addMBB(BBLoop); + + unsigned R10 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R10) + .addReg(AtomicValPhi) + .addReg(Mask3); + + unsigned R11 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R11).addReg(R9).addReg(Mask2); + + Swp2 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), Swp2).addReg(R10).addReg(R11); + } else { + unsigned R4 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R4) + .addReg(AtomicValPhi) + .addReg(Mask2); + + unsigned Res1 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Opcode), Res1).addReg(R4).addReg(Val1); + + unsigned Swp1 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), Swp1).addReg(Res1).addReg(Mask2); + + unsigned R5 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R5) + .addReg(AtomicValPhi) + .addReg(Mask3); + + if (inv) { + unsigned Rtmp1 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::XOR), Rtmp1) + .addReg(AtomicValPhi) + .addReg(Mask2); + R5 = Rtmp1; + } + + Swp2 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), Swp2).addReg(Swp1).addReg(R5); + } + + BuildMI(*BBLoop, BBLoop->begin(), DL, TII.get(Xtensa::PHI), AtomicValPhi) + .addReg(AtomicValLoop) + .addMBB(BB) + .addReg(R3) + .addMBB(ThisBB); + + unsigned Swp3 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(AtomicValPhi); + BuildMI(BB, DL, TII.get(Xtensa::S32C1I), Swp3) + .addReg(Swp2) + .addReg(AddrAlign) + .addImm(0); + + BuildMI(BB, DL, TII.get(Xtensa::MOV_N), AtomicValLoop).addReg(Swp3); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(Swp3) + .addReg(AtomicValPhi) + .addMBB(BBLoop); + + BB->addSuccessor(BBLoop); + BB->addSuccessor(BBExit); + BB = BBExit; + auto St = BBExit->begin(); + + unsigned R6 = MRI.createVirtualRegister(RC); + + BuildMI(*BB, St, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); + + BuildMI(*BB, St, DL, TII.get(Xtensa::SRL), R6).addReg(AtomicValLoop); + + BuildMI(*BB, St, DL, TII.get(Xtensa::AND), Res.getReg()) + .addReg(R6) + .addReg(Mask1); + + MI.eraseFromParent(); // The pseudo instruction is gone now. + + return BB; +} + MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( MachineInstr &MI, MachineBasicBlock *MBB) const { DebugLoc DL = MI.getDebugLoc(); @@ -1696,6 +2464,101 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( return MBB; } + case Xtensa::ATOMIC_CMP_SWAP_8_P: { + return emitAtomicCmpSwap(MI, MBB, 1); + } + case Xtensa::ATOMIC_CMP_SWAP_16_P: { + return emitAtomicCmpSwap(MI, MBB, 0); + } + case Xtensa::ATOMIC_CMP_SWAP_32_P: { + MachineOperand &R = MI.getOperand(0); + MachineOperand &Addr = MI.getOperand(1); + MachineOperand &Cmp = MI.getOperand(2); + MachineOperand &Swap = MI.getOperand(3); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1) + .addReg(Cmp.getReg()); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::S32C1I), R.getReg()) + .addReg(Swap.getReg()) + .addReg(Addr.getReg()) + .addImm(0); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::ATOMIC_SWAP_8_P: { + return emitAtomicSwap(MI, MBB, 1); + } + case Xtensa::ATOMIC_SWAP_16_P: { + return emitAtomicSwap(MI, MBB, 0); + } + case Xtensa::ATOMIC_SWAP_32_P: { + return emitAtomicSwap(MI, MBB); + } + case Xtensa::ATOMIC_LOAD_ADD_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::ADD, false, false); + case Xtensa::ATOMIC_LOAD_SUB_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::SUB, false, false); + case Xtensa::ATOMIC_LOAD_OR_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::OR, false, false); + case Xtensa::ATOMIC_LOAD_XOR_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::XOR, false, false); + case Xtensa::ATOMIC_LOAD_AND_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::AND, false, false); + case Xtensa::ATOMIC_LOAD_NAND_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::AND, true, false); + case Xtensa::ATOMIC_LOAD_MIN_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::BGE, false, true); + case Xtensa::ATOMIC_LOAD_MAX_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::BLT, false, true); + case Xtensa::ATOMIC_LOAD_UMIN_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::BGEU, false, true); + case Xtensa::ATOMIC_LOAD_UMAX_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::BLTU, false, true); + + case Xtensa::ATOMIC_LOAD_ADD_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::ADD, false, false); + case Xtensa::ATOMIC_LOAD_SUB_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::SUB, false, false); + case Xtensa::ATOMIC_LOAD_OR_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::OR, false, false); + case Xtensa::ATOMIC_LOAD_XOR_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::XOR, false, false); + case Xtensa::ATOMIC_LOAD_AND_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::AND, false, false); + case Xtensa::ATOMIC_LOAD_NAND_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::AND, true, false); + case Xtensa::ATOMIC_LOAD_MIN_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::BGE, false, true); + case Xtensa::ATOMIC_LOAD_MAX_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::BLT, false, true); + case Xtensa::ATOMIC_LOAD_UMIN_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::BGEU, false, true); + case Xtensa::ATOMIC_LOAD_UMAX_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::BLTU, false, true); + + case Xtensa::ATOMIC_LOAD_ADD_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::ADD, false, false); + case Xtensa::ATOMIC_LOAD_SUB_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::SUB, false, false); + case Xtensa::ATOMIC_LOAD_OR_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::OR, false, false); + case Xtensa::ATOMIC_LOAD_XOR_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::XOR, false, false); + case Xtensa::ATOMIC_LOAD_AND_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::AND, false, false); + case Xtensa::ATOMIC_LOAD_NAND_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::AND, true, false); + case Xtensa::ATOMIC_LOAD_MIN_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::BGE, false, true); + case Xtensa::ATOMIC_LOAD_MAX_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::BLT, false, true); + case Xtensa::ATOMIC_LOAD_UMIN_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::BGEU, false, true); + case Xtensa::ATOMIC_LOAD_UMAX_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::BLTU, false, true); + default: llvm_unreachable("Unexpected instr type to insert"); } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index e6ddf9864932a..c3b1f858c8983 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -37,6 +37,7 @@ enum { // of the field [1..16] EXTUI, + MEMW, MOVSP, // Wraps a TargetGlobalAddress that should be loaded using PC-relative @@ -145,6 +146,10 @@ class XtensaTargetLowering : public TargetLowering { const SmallVectorImpl &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override; + bool shouldInsertFencesForAtomic(const Instruction *I) const override { + return true; + } + bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override; @@ -195,12 +200,26 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; + SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; + SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const; CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; MachineBasicBlock *emitSelectCC(MachineInstr &MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitAtomicSwap(MachineInstr &MI, MachineBasicBlock *BB, + int isByteOperand) const; + MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI, MachineBasicBlock *BB, + int isByteOperand) const; + MachineBasicBlock *emitAtomicSwap(MachineInstr &MI, + MachineBasicBlock *BB) const; + MachineBasicBlock *emitAtomicRMW(MachineInstr &MI, MachineBasicBlock *BB, + bool isByteOperand, unsigned Opcode, + bool inv, bool minmax) const; + MachineBasicBlock *emitAtomicRMW(MachineInstr &MI, MachineBasicBlock *BB, + unsigned Opcode, bool inv, + bool minmax) const; }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 31608f4659365..06a9de1bce7e5 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -496,6 +496,8 @@ def EXTW : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins), let hasSideEffects = 1; } +def : Pat<(Xtensa_mem_barrier), (MEMW)>; + //===----------------------------------------------------------------------===// // Illegal instructions //===----------------------------------------------------------------------===// @@ -1498,6 +1500,162 @@ def RFI : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins uimm4:$imm), let t = 0x1; } +//===----------------------------------------------------------------------===// +// S32C1I +//===----------------------------------------------------------------------===// + +let mayStore = 1, mayLoad = 1, Predicates = [HasS32C1I] in { + def S32C1I : RRI8_Inst<0x02, (outs AR:$a), (ins AR:$t, mem32:$addr), + "s32c1i\t$t, $addr", []> { + bits<12> addr; + + let r = 0x0e; + let Uses = [SCOMPARE1]; + let Constraints = "$a = $t"; + let imm8{7-0} = addr{11-4}; + let s{3-0} = addr{3-0}; + } +} + +//===----------------------------------------------------------------------===// +// Atomic patterns +//===----------------------------------------------------------------------===// + +// Atomic load/store are available under both +s32c1i and +force-atomics. +// Fences will be inserted for atomic load/stores according to the logic in +// XtensaTargetLowering. +let Predicates = [HasAtomicLdSt] in { + def : Pat<(i32 (atomic_load_8 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>; + def : Pat<(i32 (atomic_load_16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>; + def : Pat<(i32 (atomic_load_32 addr_ish4:$addr)), (L32I addr_ish4:$addr)>; + + def : Pat<(atomic_store_8 AR:$t, addr_ish1:$addr), (S8I AR:$t, addr_ish1:$addr)>; + def : Pat<(atomic_store_16 AR:$t, addr_ish2:$addr), (S16I AR:$t, addr_ish2:$addr)>; + def : Pat<(atomic_store_32 AR:$t, addr_ish4:$addr), (S32I AR:$t, addr_ish4:$addr)>; +} + +let usesCustomInserter = 1, Predicates = [HasS32C1I] in { + def ATOMIC_CMP_SWAP_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap), + "!atomic_cmp_swap_8_p, $dst, $ptr, $cmp, $swap", + [(set AR:$dst, (atomic_cmp_swap_i8 AR:$ptr, AR:$cmp, AR:$swap))]>; + def ATOMIC_CMP_SWAP_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap), + "!atomic_cmp_swap_16_p, $dst, $ptr, $cmp, $swap", + [(set AR:$dst, (atomic_cmp_swap_i16 AR:$ptr, AR:$cmp, AR:$swap))]>; + def ATOMIC_CMP_SWAP_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap), + "!atomic_cmp_swap_32_p, $dst, $ptr, $cmp, $swap", + [(set AR:$dst, (atomic_cmp_swap_i32 AR:$ptr, AR:$cmp, AR:$swap))]>; + + def ATOMIC_SWAP_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$swap), + "!atomic_swap_8_p, $dst, $ptr, $swap", + [(set AR:$dst, (atomic_swap_i8 AR:$ptr, AR:$swap))]>; + def ATOMIC_SWAP_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$swap), + "!atomic_swap_16_p, $dst, $ptr, $swap", + [(set AR:$dst, (atomic_swap_i16 AR:$ptr, AR:$swap))]>; + def ATOMIC_SWAP_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$swap), + "!atomic_swap_32_p, $dst, $ptr, $swap", + [(set AR:$dst, (atomic_swap_i32 AR:$ptr, AR:$swap))]>; + + def ATOMIC_LOAD_ADD_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_add_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_add_i8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_ADD_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_add_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_add_i16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_ADD_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_add_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_add_i32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_SUB_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_sub_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_sub_i8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_SUB_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_sub_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_sub_i16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_SUB_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_sub_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_sub_i32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_AND_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_and_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_and_i8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_AND_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_and_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_and_i16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_AND_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_and_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_and_i32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_OR_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_or_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_or_i8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_OR_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_or_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_or_i16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_OR_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_or_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_or_i32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_XOR_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_xor_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_xor_i8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_XOR_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_xor_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_xor_i16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_XOR_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_xor_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_xor_i32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_NAND_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_nand_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_nand_i8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_NAND_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_nand_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_nand_i16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_NAND_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_nand_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_nand_i32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_MIN_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_min_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_min_i8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_MIN_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_min_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_min_i16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_MIN_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_min_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_min_i32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_MAX_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_max_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_max_i8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_MAX_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_max_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_max_i16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_MAX_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_max_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_max_i32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_UMIN_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umin_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umin_i8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_UMIN_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umin_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umin_i16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_UMIN_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umin_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umin_i32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_UMAX_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umax_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umax_i8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_UMAX_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umax_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umax_i16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_UMAX_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umax_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umax_i32 AR:$ptr, AR:$arg))]>; +} + //===----------------------------------------------------------------------===// // DSP Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index 56be3d51505e1..ce882b3ce4ea0 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -39,6 +39,8 @@ def SDT_XtensaEXTUI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCi def SDT_XtensaMOVSP : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; +def SDT_XtensaMEMBARRIER : SDTypeProfile<0, 0, []>; + def SDT_XtensaRUR : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; //===----------------------------------------------------------------------===// @@ -79,6 +81,9 @@ def Xtensa_extui: SDNode<"XtensaISD::EXTUI", SDT_XtensaEXTUI>; def Xtensa_movsp: SDNode<"XtensaISD::MOVSP", SDT_XtensaMOVSP, [SDNPHasChain, SDNPSideEffect, SDNPInGlue]>; +def Xtensa_mem_barrier: SDNode<"XtensaISD::MEMW", SDT_XtensaMEMBARRIER, + [SDNPHasChain, SDNPSideEffect]>; + def Xtensa_rur: SDNode<"XtensaISD::RUR", SDT_XtensaRUR, [SDNPInGlue]>; diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index 596c4105c1118..d1f2c6b8e43a3 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -84,6 +84,9 @@ def SAR : SRReg<3, "sar", ["SAR","3"]>; // Boolean Register def BREG : SRReg<4, "br", ["BR","4"]>; +// Expected data value for S32C1I operation +def SCOMPARE1 : SRReg<12, "scompare1", ["SCOMPARE1", "12"]>; + // Literal base def LITBASE : SRReg<5, "litbase", ["LITBASE", "5"]>; @@ -97,6 +100,9 @@ def IBREAKENABLE : SRReg<96, "ibreakenable", ["IBREAKENABLE", "96"]>; // Memory Control Register def MEMCTL : SRReg<97, "memctl", ["MEMCTL", "97"]>; +// Atomic Operation Control +def ATOMCTL : SRReg<99, "atomctl", ["ATOMCTL", "99"]>; + def DDR : SRReg<104, "ddr", ["DDR", "104"]>; // Instuction break address register 0 @@ -218,8 +224,8 @@ def MR23 : RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>; def MR : RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>; def SR : RegisterClass<"Xtensa", [i32], 32, (add - LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, ACCLO, ACCHI, MR, - WINDOWBASE, WINDOWSTART, IBREAKENABLE, MEMCTL, DDR, IBREAKA0, IBREAKA1, + LBEG, LEND, LCOUNT, SAR, BREG, SCOMPARE1, LITBASE, ACCLO, ACCHI, MR, + WINDOWBASE, WINDOWSTART, IBREAKENABLE, MEMCTL, ATOMCTL, DDR, IBREAKA0, IBREAKA1, DBREAKA0, DBREAKA1, DBREAKC0, DBREAKC1, CONFIGID0, EPC1, EPC2, EPC3, EPC4, EPC5, EPC6, EPC7, DEPC, EPS2, EPS3, EPS4, EPS5, EPS6, EPS7, CONFIGID1, EXCSAVE1, EXCSAVE2, EXCSAVE3, EXCSAVE4, EXCSAVE5, EXCSAVE6, EXCSAVE7, CPENABLE, INTERRUPT, INTSET, INTCLEAR, INTENABLE, diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index fd677a451f3fd..b406534a0ec77 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -77,6 +77,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasMul32() const { return HasMul32; } bool hasMul32High() const { return HasMul32High; } bool hasDiv32() const { return HasDiv32; } + bool hasS32C1I() const { return HasS32C1I; } + bool hasForcedAtomics() const { return HasForcedAtomics; } bool hasSingleFloat() const { return HasSingleFloat; } bool hasRegionProtection() const { return HasRegionProtection; } bool hasRelocatableVector() const { return HasRelocatableVector; } diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index 8d2dca6c23721..c9f1ca8b46dab 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -107,6 +107,7 @@ class XtensaPassConfig : public TargetPassConfig { } bool addInstSelector() override; + void addIRPasses() override; void addPreEmitPass() override; }; } // end anonymous namespace @@ -116,6 +117,11 @@ bool XtensaPassConfig::addInstSelector() { return false; } +void XtensaPassConfig::addIRPasses() { + addPass(createAtomicExpandLegacyPass()); + TargetPassConfig::addIRPasses(); +} + void XtensaPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); } TargetPassConfig *XtensaTargetMachine::createPassConfig(PassManagerBase &PM) { diff --git a/llvm/test/CodeGen/Xtensa/atomic-load-store.ll b/llvm/test/CodeGen/Xtensa/atomic-load-store.ll new file mode 100644 index 0000000000000..4f7266195db28 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/atomic-load-store.ll @@ -0,0 +1,498 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=xtensa -mattr=+windowed -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA +; RUN: llc -mtriple=xtensa -mattr=+windowed,s32c1i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC + +define i8 @atomic_load_i8_unordered(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i8_unordered: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: l32r a8, .LCPI0_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i8_unordered: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l8ui a2, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i8, ptr %a unordered, align 1 + ret i8 %1 +} + +define i8 @atomic_load_i8_monotonic(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i8_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: l32r a8, .LCPI1_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i8_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l8ui a2, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i8, ptr %a monotonic, align 1 + ret i8 %1 +} + +define i8 @atomic_load_i8_acquire(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i8_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 2 +; XTENSA-NEXT: l32r a8, .LCPI2_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i8_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l8ui a2, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i8, ptr %a acquire, align 1 + ret i8 %1 +} + +define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i8_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 5 +; XTENSA-NEXT: l32r a8, .LCPI3_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i8_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l8ui a2, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i8, ptr %a seq_cst, align 1 + ret i8 %1 +} + +define i16 @atomic_load_i16_unordered(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i16_unordered: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: l32r a8, .LCPI4_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i16_unordered: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l16ui a2, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i16, ptr %a unordered, align 2 + ret i16 %1 +} + +define i16 @atomic_load_i16_monotonic(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: l32r a8, .LCPI5_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l16ui a2, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i16, ptr %a monotonic, align 2 + ret i16 %1 +} + +define i16 @atomic_load_i16_acquire(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 2 +; XTENSA-NEXT: l32r a8, .LCPI6_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l16ui a2, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i16, ptr %a acquire, align 2 + ret i16 %1 +} + +define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 5 +; XTENSA-NEXT: l32r a8, .LCPI7_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l16ui a2, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i16, ptr %a seq_cst, align 2 + ret i16 %1 +} + +define i32 @atomic_load_i32_unordered(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i32_unordered: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: l32r a8, .LCPI8_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i32_unordered: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a2, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i32, ptr %a unordered, align 4 + ret i32 %1 +} + +define i32 @atomic_load_i32_monotonic(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: l32r a8, .LCPI9_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a2, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i32, ptr %a monotonic, align 4 + ret i32 %1 +} + +define i32 @atomic_load_i32_acquire(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 2 +; XTENSA-NEXT: l32r a8, .LCPI10_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a2, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i32, ptr %a acquire, align 4 + ret i32 %1 +} + +define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind { +; XTENSA-LABEL: atomic_load_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 5 +; XTENSA-NEXT: l32r a8, .LCPI11_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_load_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a2, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = load atomic i32, ptr %a seq_cst, align 4 + ret i32 %1 +} + +define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomic_store_i8_unordered: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI12_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i8_unordered: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: s8i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i8 %b, ptr %a unordered, align 1 + ret void +} + +define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomic_store_i8_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI13_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i8_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: s8i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i8 %b, ptr %a monotonic, align 1 + ret void +} + +define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomic_store_i8_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI14_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i8_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: s8i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i8 %b, ptr %a release, align 1 + ret void +} + +define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomic_store_i8_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI15_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i8_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: s8i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + store atomic i8 %b, ptr %a seq_cst, align 1 + ret void +} + +define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomic_store_i16_unordered: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI16_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i16_unordered: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: s16i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i16 %b, ptr %a unordered, align 2 + ret void +} + +define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomic_store_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI17_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: s16i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i16 %b, ptr %a monotonic, align 2 + ret void +} + +define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomic_store_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI18_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: s16i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i16 %b, ptr %a release, align 2 + ret void +} + +define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomic_store_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI19_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: s16i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + store atomic i16 %b, ptr %a seq_cst, align 2 + ret void +} + +define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomic_store_i32_unordered: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI20_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i32_unordered: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: s32i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i32 %b, ptr %a unordered, align 4 + ret void +} + +define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomic_store_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI21_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: s32i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i32 %b, ptr %a monotonic, align 4 + ret void +} + +define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomic_store_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI22_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: s32i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i32 %b, ptr %a release, align 4 + ret void +} + +define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomic_store_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI23_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomic_store_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: s32i a3, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + store atomic i32 %b, ptr %a seq_cst, align 4 + ret void +} diff --git a/llvm/test/CodeGen/Xtensa/atomic-rmw.ll b/llvm/test/CodeGen/Xtensa/atomic-rmw.ll new file mode 100644 index 0000000000000..43a9ba247e10d --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/atomic-rmw.ll @@ -0,0 +1,4728 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=xtensa -mattr=+windowed -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA +; RUN: llc -mtriple=xtensa -mattr=+windowed,s32c1i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC + +define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i8_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI0_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: and a14, a13, a10 +; XTENSA-ATOMIC-NEXT: .LBB0_1: # =>This Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: # Child Loop BB0_2 Depth 2 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: .LBB0_2: # Parent Loop BB0_1 Depth=1 +; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a12, a15 +; XTENSA-ATOMIC-NEXT: or a7, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB0_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB0_2 Depth=2 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB0_2 +; XTENSA-ATOMIC-NEXT: .LBB0_4: # in Loop: Header=BB0_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a14, a10 +; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB0_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: sext a2, a8, 7 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i8_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI1_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: and a14, a13, a10 +; XTENSA-ATOMIC-NEXT: .LBB1_1: # =>This Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: # Child Loop BB1_2 Depth 2 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: .LBB1_2: # Parent Loop BB1_1 Depth=1 +; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a12, a15 +; XTENSA-ATOMIC-NEXT: or a7, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB1_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=2 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB1_2 +; XTENSA-ATOMIC-NEXT: .LBB1_4: # in Loop: Header=BB1_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a14, a10 +; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB1_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: sext a2, a8, 7 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i8 %b acquire + ret i8 %1 +} + +define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i8_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI2_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: and a14, a13, a10 +; XTENSA-ATOMIC-NEXT: .LBB2_1: # =>This Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: # Child Loop BB2_2 Depth 2 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: .LBB2_2: # Parent Loop BB2_1 Depth=1 +; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a12, a15 +; XTENSA-ATOMIC-NEXT: or a7, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB2_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB2_2 Depth=2 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB2_2 +; XTENSA-ATOMIC-NEXT: .LBB2_4: # in Loop: Header=BB2_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a14, a10 +; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB2_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: sext a2, a8, 7 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i8 %b release + ret i8 %1 +} + +define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i8_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI3_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: and a14, a13, a10 +; XTENSA-ATOMIC-NEXT: .LBB3_1: # =>This Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: # Child Loop BB3_2 Depth 2 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: .LBB3_2: # Parent Loop BB3_1 Depth=1 +; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a12, a15 +; XTENSA-ATOMIC-NEXT: or a7, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB3_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB3_2 Depth=2 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB3_2 +; XTENSA-ATOMIC-NEXT: .LBB3_4: # in Loop: Header=BB3_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a14, a10 +; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB3_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: sext a2, a8, 7 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i8 %b acq_rel + ret i8 %1 +} + +define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i8_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI4_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: and a14, a13, a10 +; XTENSA-ATOMIC-NEXT: .LBB4_1: # =>This Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: # Child Loop BB4_2 Depth 2 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: .LBB4_2: # Parent Loop BB4_1 Depth=1 +; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a12, a15 +; XTENSA-ATOMIC-NEXT: or a7, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB4_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB4_2 Depth=2 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB4_2 +; XTENSA-ATOMIC-NEXT: .LBB4_4: # in Loop: Header=BB4_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a14, a10 +; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB4_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: sext a2, a8, 7 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i8 %b seq_cst + ret i8 %1 +} + +define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i8_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI5_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB5_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i8_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI6_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB6_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i8 %b acquire + ret i8 %1 +} + +define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i8_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI7_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB7_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i8 %b release + ret i8 %1 +} + +define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i8_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI8_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB8_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i8 %b acq_rel + ret i8 %1 +} + +define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i8_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI9_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB9_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i8 %b seq_cst + ret i8 %1 +} + +define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i8_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI10_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB10_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i8_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI11_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB11_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i8 %b acquire + ret i8 %1 +} + +define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i8_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI12_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB12_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i8 %b release + ret i8 %1 +} + +define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i8_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI13_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB13_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i8 %b acq_rel + ret i8 %1 +} + +define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i8_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI14_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB14_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i8 %b seq_cst + ret i8 %1 +} + +define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i8_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI15_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: and a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB15_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i8_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI16_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: and a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB16_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i8 %b acquire + ret i8 %1 +} + +define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i8_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI17_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: and a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB17_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i8 %b release + ret i8 %1 +} + +define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i8_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI18_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: and a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB18_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i8 %b acq_rel + ret i8 %1 +} + +define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i8_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI19_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: and a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB19_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i8 %b seq_cst + ret i8 %1 +} + +define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i8_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI20_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: and a13, a14, a11 +; XTENSA-ATOMIC-NEXT: and a13, a13, a12 +; XTENSA-ATOMIC-NEXT: and a13, a13, a11 +; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 +; XTENSA-ATOMIC-NEXT: or a15, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a13, a15 +; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB20_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a13 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw nand ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i8_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI21_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: and a13, a14, a11 +; XTENSA-ATOMIC-NEXT: and a13, a13, a12 +; XTENSA-ATOMIC-NEXT: and a13, a13, a11 +; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 +; XTENSA-ATOMIC-NEXT: or a15, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a13, a15 +; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB21_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a13 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw nand ptr %a, i8 %b acquire + ret i8 %1 +} + +define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i8_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI22_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: and a13, a14, a11 +; XTENSA-ATOMIC-NEXT: and a13, a13, a12 +; XTENSA-ATOMIC-NEXT: and a13, a13, a11 +; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 +; XTENSA-ATOMIC-NEXT: or a15, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a13, a15 +; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB22_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a13 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw nand ptr %a, i8 %b release + ret i8 %1 +} + +define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i8_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI23_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: and a13, a14, a11 +; XTENSA-ATOMIC-NEXT: and a13, a13, a12 +; XTENSA-ATOMIC-NEXT: and a13, a13, a11 +; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 +; XTENSA-ATOMIC-NEXT: or a15, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a13, a15 +; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB23_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a13 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw nand ptr %a, i8 %b acq_rel + ret i8 %1 +} + +define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i8_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI24_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: and a13, a14, a11 +; XTENSA-ATOMIC-NEXT: and a13, a13, a12 +; XTENSA-ATOMIC-NEXT: and a13, a13, a11 +; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 +; XTENSA-ATOMIC-NEXT: or a15, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a13, a15 +; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB24_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a13 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw nand ptr %a, i8 %b seq_cst + ret i8 %1 +} + +define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i8_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI25_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: or a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB25_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i8_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI26_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: or a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB26_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i8 %b acquire + ret i8 %1 +} + +define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i8_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI27_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: or a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB27_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i8 %b release + ret i8 %1 +} + +define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i8_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI28_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: or a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB28_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i8 %b acq_rel + ret i8 %1 +} + +define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i8_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI29_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: or a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB29_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i8 %b seq_cst + ret i8 %1 +} + +define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i8_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI30_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB30_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i8_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI31_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB31_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i8 %b acquire + ret i8 %1 +} + +define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i8_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI32_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB32_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i8 %b release + ret i8 %1 +} + +define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i8_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI33_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB33_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i8 %b acq_rel + ret i8 %1 +} + +define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i8_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI34_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB34_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i8 %b seq_cst + ret i8 %1 +} + +;define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw max ptr %a, i8 %b monotonic +; ret i8 %1 +;} + +;define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw max ptr %a, i8 %b acquire +; ret i8 %1 +;} + +;define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw max ptr %a, i8 %b release +; ret i8 %1 +;} + +;define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw max ptr %a, i8 %b acq_rel +; ret i8 %1 +;} + +;define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw max ptr %a, i8 %b seq_cst +; ret i8 %1 +;} + +;define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw min ptr %a, i8 %b monotonic +; ret i8 %1 +;} + +;define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw min ptr %a, i8 %b acquire +; ret i8 %1 +;} +; +;define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw min ptr %a, i8 %b release +; ret i8 %1 +;} +; +;define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw min ptr %a, i8 %b acq_rel +; ret i8 %1 +;} +; +;define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw min ptr %a, i8 %b seq_cst +; ret i8 %1 +;} + +;define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i8 %b monotonic +; ret i8 %1 +;} +; +;define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i8 %b acquire +; ret i8 %1 +;} +; +;define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i8 %b release +; ret i8 %1 +;} +; +;define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i8 %b acq_rel +; ret i8 %1 +;} +; +;define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i8 %b seq_cst +; ret i8 %1 +;} + +;define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i8 %b monotonic +; ret i8 %1 +;} +; +;define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i8 %b acquire +; ret i8 %1 +;} +; +;define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i8 %b release +; ret i8 %1 +;} +; +;define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i8 %b acq_rel +; ret i8 %1 +;} +; +;define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i8 %b seq_cst +; ret i8 %1 +;} + +define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI35_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: and a14, a13, a10 +; XTENSA-ATOMIC-NEXT: .LBB35_1: # =>This Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: # Child Loop BB35_2 Depth 2 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: .LBB35_2: # Parent Loop BB35_1 Depth=1 +; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a12, a15 +; XTENSA-ATOMIC-NEXT: or a7, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB35_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB35_2 Depth=2 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB35_2 +; XTENSA-ATOMIC-NEXT: .LBB35_4: # in Loop: Header=BB35_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a14, a10 +; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB35_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: sext a2, a8, 15 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI36_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: and a14, a13, a10 +; XTENSA-ATOMIC-NEXT: .LBB36_1: # =>This Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: # Child Loop BB36_2 Depth 2 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: .LBB36_2: # Parent Loop BB36_1 Depth=1 +; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a12, a15 +; XTENSA-ATOMIC-NEXT: or a7, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB36_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB36_2 Depth=2 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB36_2 +; XTENSA-ATOMIC-NEXT: .LBB36_4: # in Loop: Header=BB36_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a14, a10 +; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB36_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: sext a2, a8, 15 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i16 %b acquire + ret i16 %1 +} + +define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI37_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: and a14, a13, a10 +; XTENSA-ATOMIC-NEXT: .LBB37_1: # =>This Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: # Child Loop BB37_2 Depth 2 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: .LBB37_2: # Parent Loop BB37_1 Depth=1 +; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a12, a15 +; XTENSA-ATOMIC-NEXT: or a7, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB37_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB37_2 Depth=2 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB37_2 +; XTENSA-ATOMIC-NEXT: .LBB37_4: # in Loop: Header=BB37_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a14, a10 +; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB37_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: sext a2, a8, 15 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i16 %b release + ret i16 %1 +} + +define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i16_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI38_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: and a14, a13, a10 +; XTENSA-ATOMIC-NEXT: .LBB38_1: # =>This Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: # Child Loop BB38_2 Depth 2 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: .LBB38_2: # Parent Loop BB38_1 Depth=1 +; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a12, a15 +; XTENSA-ATOMIC-NEXT: or a7, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB38_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB38_2 Depth=2 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB38_2 +; XTENSA-ATOMIC-NEXT: .LBB38_4: # in Loop: Header=BB38_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a14, a10 +; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB38_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: sext a2, a8, 15 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i16 %b acq_rel + ret i16 %1 +} + +define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI39_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: and a14, a13, a10 +; XTENSA-ATOMIC-NEXT: .LBB39_1: # =>This Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: # Child Loop BB39_2 Depth 2 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: .LBB39_2: # Parent Loop BB39_1 Depth=1 +; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a12, a15 +; XTENSA-ATOMIC-NEXT: or a7, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB39_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB39_2 Depth=2 +; XTENSA-ATOMIC-NEXT: and a7, a14, a11 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB39_2 +; XTENSA-ATOMIC-NEXT: .LBB39_4: # in Loop: Header=BB39_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a14, a10 +; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB39_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: sext a2, a8, 15 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i16 %b seq_cst + ret i16 %1 +} + +define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI40_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB40_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI41_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB41_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i16 %b acquire + ret i16 %1 +} + +define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI42_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB42_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i16 %b release + ret i16 %1 +} + +define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i16_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI43_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB43_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i16 %b acq_rel + ret i16 %1 +} + +define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI44_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB44_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i16 %b seq_cst + ret i16 %1 +} + +define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI45_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB45_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI46_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB46_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i16 %b acquire + ret i16 %1 +} + +define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI47_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB47_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i16 %b release + ret i16 %1 +} + +define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i16_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI48_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB48_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i16 %b acq_rel + ret i16 %1 +} + +define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI49_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB49_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i16 %b seq_cst + ret i16 %1 +} + +define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI50_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: and a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB50_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI51_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: and a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB51_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i16 %b acquire + ret i16 %1 +} + +define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI52_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: and a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB52_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i16 %b release + ret i16 %1 +} + +define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i16_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI53_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: and a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB53_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i16 %b acq_rel + ret i16 %1 +} + +define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI54_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: and a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB54_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i16 %b seq_cst + ret i16 %1 +} + +define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI55_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: and a13, a14, a11 +; XTENSA-ATOMIC-NEXT: and a13, a13, a12 +; XTENSA-ATOMIC-NEXT: and a13, a13, a11 +; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 +; XTENSA-ATOMIC-NEXT: or a15, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a13, a15 +; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB55_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a13 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw nand ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI56_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: and a13, a14, a11 +; XTENSA-ATOMIC-NEXT: and a13, a13, a12 +; XTENSA-ATOMIC-NEXT: and a13, a13, a11 +; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 +; XTENSA-ATOMIC-NEXT: or a15, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a13, a15 +; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB56_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a13 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw nand ptr %a, i16 %b acquire + ret i16 %1 +} + +define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI57_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: and a13, a14, a11 +; XTENSA-ATOMIC-NEXT: and a13, a13, a12 +; XTENSA-ATOMIC-NEXT: and a13, a13, a11 +; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 +; XTENSA-ATOMIC-NEXT: or a15, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a13, a15 +; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB57_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a13 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw nand ptr %a, i16 %b release + ret i16 %1 +} + +define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i16_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI58_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: and a13, a14, a11 +; XTENSA-ATOMIC-NEXT: and a13, a13, a12 +; XTENSA-ATOMIC-NEXT: and a13, a13, a11 +; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 +; XTENSA-ATOMIC-NEXT: or a15, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a13, a15 +; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB58_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a13 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw nand ptr %a, i16 %b acq_rel + ret i16 %1 +} + +define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI59_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a12, a3 +; XTENSA-ATOMIC-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: and a13, a14, a11 +; XTENSA-ATOMIC-NEXT: and a13, a13, a12 +; XTENSA-ATOMIC-NEXT: and a13, a13, a11 +; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 +; XTENSA-ATOMIC-NEXT: or a15, a13, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a13, a15 +; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB59_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a13 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw nand ptr %a, i16 %b seq_cst + ret i16 %1 +} + +define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI60_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: or a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB60_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI61_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: or a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB61_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i16 %b acquire + ret i16 %1 +} + +define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI62_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: or a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB62_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i16 %b release + ret i16 %1 +} + +define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i16_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI63_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: or a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB63_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i16 %b acq_rel + ret i16 %1 +} + +define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI64_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: or a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB64_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i16 %b seq_cst + ret i16 %1 +} + +define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI65_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB65_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI66_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB66_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i16 %b acquire + ret i16 %1 +} + +define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI67_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB67_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i16 %b release + ret i16 %1 +} + +define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i16_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI68_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB68_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i16 %b acq_rel + ret i16 %1 +} + +define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI69_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 +; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a10 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a3 +; XTENSA-ATOMIC-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB69_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i16 %b seq_cst + ret i16 %1 +} + +;define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw max ptr %a, i16 %b monotonic +; ret i16 %1 +;} +; +;define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw max ptr %a, i16 %b acquire +; ret i16 %1 +;} +; +;define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw max ptr %a, i16 %b release +; ret i16 %1 +;} +; +;define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw max ptr %a, i16 %b acq_rel +; ret i16 %1 +;} +; +;define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw max ptr %a, i16 %b seq_cst +; ret i16 %1 +;} + +;define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw min ptr %a, i16 %b monotonic +; ret i16 %1 +;} +; +;define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw min ptr %a, i16 %b acquire +; ret i16 %1 +;} +; +;define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw min ptr %a, i16 %b release +; ret i16 %1 +;} +; +;define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw min ptr %a, i16 %b acq_rel +; ret i16 %1 +;} +; +;define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw min ptr %a, i16 %b seq_cst +; ret i16 %1 +;} + +;define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i16 %b monotonic +; ret i16 %1 +;} +; +;define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i16 %b acquire +; ret i16 %1 +;} +; +;define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i16 %b release +; ret i16 %1 +;} +; +;define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i16 %b acq_rel +; ret i16 %1 +;} +; +;define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i16 %b seq_cst +; ret i16 %1 +;} + +;define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i16 %b monotonic +; ret i16 %1 +;} +; +;define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i16 %b acquire +; ret i16 %1 +;} +; +;define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i16 %b release +; ret i16 %1 +;} +; +;define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i16 %b acq_rel +; ret i16 %1 +;} +; +;define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i16 %b seq_cst +; ret i16 %1 +;} + +define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI70_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB70_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a9, a9 +; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 +; XTENSA-ATOMIC-NEXT: or a9, a3, a3 +; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: bne a9, a8, .LBB70_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI71_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB71_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a9, a9 +; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 +; XTENSA-ATOMIC-NEXT: or a9, a3, a3 +; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: bne a9, a8, .LBB71_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i32 %b acquire + ret i32 %1 +} + +define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI72_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB72_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a9, a9 +; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 +; XTENSA-ATOMIC-NEXT: or a9, a3, a3 +; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: bne a9, a8, .LBB72_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i32 %b release + ret i32 %1 +} + +define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI73_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB73_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a9, a9 +; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 +; XTENSA-ATOMIC-NEXT: or a9, a3, a3 +; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: bne a9, a8, .LBB73_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i32 %b acq_rel + ret i32 %1 +} + +define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI74_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB74_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a9, a9 +; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 +; XTENSA-ATOMIC-NEXT: or a9, a3, a3 +; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: bne a9, a8, .LBB74_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xchg ptr %a, i32 %b seq_cst + ret i32 %1 +} + +define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI75_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: add a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB75_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI76_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: add a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB76_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i32 %b acquire + ret i32 %1 +} + +define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI77_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: add a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB77_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i32 %b release + ret i32 %1 +} + +define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI78_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: add a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB78_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i32 %b acq_rel + ret i32 %1 +} + +define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI79_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: add a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB79_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw add ptr %a, i32 %b seq_cst + ret i32 %1 +} + +define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI80_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: sub a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB80_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI81_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: sub a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB81_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i32 %b acquire + ret i32 %1 +} + +define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI82_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: sub a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB82_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i32 %b release + ret i32 %1 +} + +define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI83_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: sub a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB83_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i32 %b acq_rel + ret i32 %1 +} + +define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI84_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: sub a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB84_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw sub ptr %a, i32 %b seq_cst + ret i32 %1 +} + +define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI85_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: and a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB85_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI86_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: and a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB86_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i32 %b acquire + ret i32 %1 +} + +define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI87_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: and a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB87_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i32 %b release + ret i32 %1 +} + +define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI88_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: and a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB88_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i32 %b acq_rel + ret i32 %1 +} + +define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI89_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: and a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB89_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw and ptr %a, i32 %b seq_cst + ret i32 %1 +} + +;define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw nand ptr %a, i32 %b monotonic +; ret i32 %1 +;} +; +;define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw nand ptr %a, i32 %b acquire +; ret i32 %1 +;} +; +;define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw nand ptr %a, i32 %b release +; ret i32 %1 +;} +; +;define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw nand ptr %a, i32 %b acq_rel +; ret i32 %1 +;} +; +;define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw nand ptr %a, i32 %b seq_cst +; ret i32 %1 +;} + +define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI90_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: or a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB90_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI91_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: or a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB91_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i32 %b acquire + ret i32 %1 +} + +define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI92_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: or a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB92_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i32 %b release + ret i32 %1 +} + +define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI93_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: or a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB93_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i32 %b acq_rel + ret i32 %1 +} + +define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI94_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: or a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB94_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw or ptr %a, i32 %b seq_cst + ret i32 %1 +} + +define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI95_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: xor a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB95_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI96_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: xor a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB96_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i32 %b acquire + ret i32 %1 +} + +define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI97_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: xor a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB97_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i32 %b release + ret i32 %1 +} + +define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI98_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: xor a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB98_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i32 %b acq_rel + ret i32 %1 +} + +define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI99_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: xor a8, a10, a3 +; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a9, a8 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB99_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %1 = atomicrmw xor ptr %a, i32 %b seq_cst + ret i32 %1 +} + +;define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw max ptr %a, i32 %b monotonic +; ret i32 %1 +;} +; +;define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw max ptr %a, i32 %b acquire +; ret i32 %1 +;} +; +;define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw max ptr %a, i32 %b release +; ret i32 %1 +;} +; +;define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw max ptr %a, i32 %b acq_rel +; ret i32 %1 +;} +; +;define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw max ptr %a, i32 %b seq_cst +; ret i32 %1 +;} + +;define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw min ptr %a, i32 %b monotonic +; ret i32 %1 +;} +; +;define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw min ptr %a, i32 %b acquire +; ret i32 %1 +;} +; +;define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw min ptr %a, i32 %b release +; ret i32 %1 +;} +; +;define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw min ptr %a, i32 %b acq_rel +; ret i32 %1 +;} +; +;define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw min ptr %a, i32 %b seq_cst +; ret i32 %1 +;} + +;define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i32 %b monotonic +; ret i32 %1 +;} +; +;define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i32 %b acquire +; ret i32 %1 +;} +; +;define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i32 %b release +; ret i32 %1 +;} +; +;define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i32 %b acq_rel +; ret i32 %1 +;} +; +;define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw umax ptr %a, i32 %b seq_cst +; ret i32 %1 +;} +; +;define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i32 %b monotonic +; ret i32 %1 +;} +; +;define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i32 %b acquire +; ret i32 %1 +;} +; +;define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i32 %b release +; ret i32 %1 +;} +; +;define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i32 %b acq_rel +; ret i32 %1 +;} +; +;define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind { +; %1 = atomicrmw umin ptr %a, i32 %b seq_cst +; ret i32 %1 +;} diff --git a/llvm/test/CodeGen/Xtensa/forced-atomics.ll b/llvm/test/CodeGen/Xtensa/forced-atomics.ll new file mode 100644 index 0000000000000..f803f90d23073 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/forced-atomics.ll @@ -0,0 +1,1288 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=xtensa -mattr=+windowed -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA +; RUN: llc -mtriple=xtensa -mattr=+windowed,s32c1i -mattr=+forced-atomics -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC + +define i8 @load8(ptr %p) nounwind { +; XTENSA-LABEL: load8: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 5 +; XTENSA-NEXT: l32r a8, .LCPI0_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: load8: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l8ui a2, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = load atomic i8, ptr %p seq_cst, align 1 + ret i8 %v +} + +define void @store8(ptr %p) nounwind { +; XTENSA-LABEL: store8: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI1_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: store8: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 0 +; XTENSA-ATOMIC-NEXT: s8i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + store atomic i8 0, ptr %p seq_cst, align 1 + ret void +} + +define i8 @rmw8(ptr %p) nounwind { +; XTENSA-LABEL: rmw8: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 1 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI2_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw8: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 +; XTENSA-ATOMIC-NEXT: movi a8, 255 +; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a8 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a13 +; XTENSA-ATOMIC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB2_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a9 +; XTENSA-ATOMIC-NEXT: srl a9, a14 +; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw add ptr %p, i8 1 seq_cst, align 1 + ret i8 %v +} + +define i8 @cmpxchg8(ptr %p) nounwind { +; XTENSA-LABEL: cmpxchg8: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a8, 0 +; XTENSA-NEXT: s8i a8, a1, 0 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: movi a12, 1 +; XTENSA-NEXT: movi a13, 5 +; XTENSA-NEXT: l32r a8, .LCPI3_0 +; XTENSA-NEXT: or a14, a13, a13 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: l8ui a2, a1, 0 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: cmpxchg8: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a10, 0 +; XTENSA-ATOMIC-NEXT: and a7, a11, a9 +; XTENSA-ATOMIC-NEXT: movi a11, 1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a12, a11 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: .LBB3_1: # %partword.cmpxchg.loop +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a15, a12 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a11, a11 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB3_3 +; XTENSA-ATOMIC-NEXT: # %bb.2: # %partword.cmpxchg.loop +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB3_1 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: .LBB3_3: # %partword.cmpxchg.loop +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB3_1 Depth=1 +; XTENSA-ATOMIC-NEXT: bnez a7, .LBB3_5 +; XTENSA-ATOMIC-NEXT: # %bb.4: # %partword.cmpxchg.failure +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB3_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: bne a15, a7, .LBB3_1 +; XTENSA-ATOMIC-NEXT: .LBB3_5: # %partword.cmpxchg.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = cmpxchg ptr %p, i8 0, i8 1 seq_cst seq_cst + %res.0 = extractvalue { i8, i1 } %res, 0 + ret i8 %res.0 +} + +define i16 @load16(ptr %p) nounwind { +; XTENSA-LABEL: load16: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 5 +; XTENSA-NEXT: l32r a8, .LCPI4_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: load16: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l16ui a2, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = load atomic i16, ptr %p seq_cst, align 2 + ret i16 %v +} + +define void @store16(ptr %p) nounwind { +; XTENSA-LABEL: store16: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI5_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: store16: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 0 +; XTENSA-ATOMIC-NEXT: s16i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + store atomic i16 0, ptr %p seq_cst, align 2 + ret void +} + +define i16 @rmw16(ptr %p) nounwind { +; XTENSA-LABEL: rmw16: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 1 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI6_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw16: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: movi a8, 3 +; XTENSA-ATOMIC-NEXT: and a8, a8, a2 +; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 +; XTENSA-ATOMIC-NEXT: slli a9, a13, 16 +; XTENSA-ATOMIC-NEXT: addi a9, a9, -1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: movi a12, -1 +; XTENSA-ATOMIC-NEXT: sll a11, a9 +; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: sll a13, a13 +; XTENSA-ATOMIC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: and a14, a15, a11 +; XTENSA-ATOMIC-NEXT: add a14, a14, a13 +; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: and a7, a15, a12 +; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 +; XTENSA-ATOMIC-NEXT: mov.n a14, a7 +; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB6_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a8, a14 +; XTENSA-ATOMIC-NEXT: and a2, a8, a9 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw add ptr %p, i16 1 seq_cst, align 2 + ret i16 %v +} + +define i16 @cmpxchg16(ptr %p) nounwind { +; XTENSA-LABEL: cmpxchg16: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a8, 0 +; XTENSA-NEXT: s16i a8, a1, 0 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: movi a12, 1 +; XTENSA-NEXT: movi a13, 5 +; XTENSA-NEXT: l32r a8, .LCPI7_0 +; XTENSA-NEXT: or a14, a13, a13 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: cmpxchg16: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI7_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a10, 0 +; XTENSA-ATOMIC-NEXT: and a7, a11, a9 +; XTENSA-ATOMIC-NEXT: movi a11, 1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a12, a11 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: .LBB7_1: # %partword.cmpxchg.loop +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: or a14, a15, a12 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a11, a11 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB7_3 +; XTENSA-ATOMIC-NEXT: # %bb.2: # %partword.cmpxchg.loop +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB7_1 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: .LBB7_3: # %partword.cmpxchg.loop +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB7_1 Depth=1 +; XTENSA-ATOMIC-NEXT: bnez a7, .LBB7_5 +; XTENSA-ATOMIC-NEXT: # %bb.4: # %partword.cmpxchg.failure +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB7_1 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: bne a15, a7, .LBB7_1 +; XTENSA-ATOMIC-NEXT: .LBB7_5: # %partword.cmpxchg.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = cmpxchg ptr %p, i16 0, i16 1 seq_cst seq_cst + %res.0 = extractvalue { i16, i1 } %res, 0 + ret i16 %res.0 +} + +define i32 @load32_unordered(ptr %p) nounwind { +; XTENSA-LABEL: load32_unordered: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: l32r a8, .LCPI8_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: load32_unordered: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a2, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + %v = load atomic i32, ptr %p unordered, align 4 + ret i32 %v +} + +define i32 @load32_monotonic(ptr %p) nounwind { +; XTENSA-LABEL: load32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: l32r a8, .LCPI9_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: load32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a2, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + %v = load atomic i32, ptr %p monotonic, align 4 + ret i32 %v +} + +define i32 @load32_acquire(ptr %p) nounwind { +; XTENSA-LABEL: load32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 2 +; XTENSA-NEXT: l32r a8, .LCPI10_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: load32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a2, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = load atomic i32, ptr %p acquire, align 4 + ret i32 %v +} + +define i32 @load32_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: load32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 5 +; XTENSA-NEXT: l32r a8, .LCPI11_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: load32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a2, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = load atomic i32, ptr %p seq_cst, align 4 + ret i32 %v +} + +define void @store32_unordered(ptr %p) nounwind { +; XTENSA-LABEL: store32_unordered: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: l32r a8, .LCPI12_0 +; XTENSA-NEXT: or a12, a11, a11 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: store32_unordered: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 0 +; XTENSA-ATOMIC-NEXT: s32i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i32 0, ptr %p unordered, align 4 + ret void +} + +define void @store32_monotonic(ptr %p) nounwind { +; XTENSA-LABEL: store32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: l32r a8, .LCPI13_0 +; XTENSA-NEXT: or a12, a11, a11 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: store32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 0 +; XTENSA-ATOMIC-NEXT: s32i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i32 0, ptr %p monotonic, align 4 + ret void +} + +define void @store32_release(ptr %p) nounwind { +; XTENSA-LABEL: store32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI14_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: store32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 0 +; XTENSA-ATOMIC-NEXT: s32i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: retw + store atomic i32 0, ptr %p release, align 4 + ret void +} + +define void @store32_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: store32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 0 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI15_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: store32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 0 +; XTENSA-ATOMIC-NEXT: s32i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + store atomic i32 0, ptr %p seq_cst, align 4 + ret void +} + +define i32 @rmw32_add_monotonic(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_add_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 1 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI16_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_add_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a10, a10 +; XTENSA-ATOMIC-NEXT: add a9, a11, a8 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a10, a9 +; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB16_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw add ptr %p, i32 1 monotonic, align 4 + ret i32 %v +} + +define i32 @rmw32_add_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_add_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 1 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI17_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_add_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a10, a10 +; XTENSA-ATOMIC-NEXT: add a9, a11, a8 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a10, a9 +; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB17_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw add ptr %p, i32 1 seq_cst, align 4 + ret i32 %v +} + +define i32 @rmw32_sub_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_sub_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 1 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI18_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_sub_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a10, a10 +; XTENSA-ATOMIC-NEXT: sub a9, a11, a8 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a10, a9 +; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB18_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw sub ptr %p, i32 1 seq_cst, align 4 + ret i32 %v +} + +define i32 @rmw32_and_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_and_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 1 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI19_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_and_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a10, a10 +; XTENSA-ATOMIC-NEXT: and a9, a11, a8 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a10, a9 +; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB19_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw and ptr %p, i32 1 seq_cst, align 4 + ret i32 %v +} + +define i32 @rmw32_nand_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_nand_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 1 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI20_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_nand_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, -1 +; XTENSA-ATOMIC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a11, a11 +; XTENSA-ATOMIC-NEXT: and a10, a12, a8 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a9 +; XTENSA-ATOMIC-NEXT: wsr a12, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a11, a10 +; XTENSA-ATOMIC-NEXT: bne a12, a10, .LBB20_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw nand ptr %p, i32 1 seq_cst, align 4 + ret i32 %v +} + +define i32 @rmw32_or_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_or_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 1 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI21_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_or_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a10, a10 +; XTENSA-ATOMIC-NEXT: or a9, a11, a8 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a10, a9 +; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB21_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw or ptr %p, i32 1 seq_cst, align 4 + ret i32 %v +} + +define i32 @rmw32_xor_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_xor_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 1 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI22_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_xor_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a10, a10 +; XTENSA-ATOMIC-NEXT: xor a9, a11, a8 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a10, a9 +; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB22_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw xor ptr %p, i32 1 seq_cst, align 4 + ret i32 %v +} + +define i32 @rmw32_max_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_max_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a5, 1 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a4, .LCPI23_0 +; XTENSA-NEXT: j .LBB23_2 +; XTENSA-NEXT: .LBB23_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB23_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB23_4 +; XTENSA-NEXT: .LBB23_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a5, a5 +; XTENSA-NEXT: bge a5, a2, .LBB23_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB23_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB23_1 +; XTENSA-NEXT: .LBB23_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_max_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a9, a11, a11 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: blt a9, a8, .LBB23_3 +; XTENSA-ATOMIC-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1 +; XTENSA-ATOMIC-NEXT: mov.n a10, a8 +; XTENSA-ATOMIC-NEXT: .LBB23_3: # in Loop: Header=BB23_1 Depth=1 +; XTENSA-ATOMIC-NEXT: mov.n a10, a10 +; XTENSA-ATOMIC-NEXT: wsr a9, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a11, a10 +; XTENSA-ATOMIC-NEXT: bne a9, a10, .LBB23_1 +; XTENSA-ATOMIC-NEXT: # %bb.4: +; XTENSA-ATOMIC-NEXT: mov.n a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw max ptr %p, i32 1 seq_cst, align 4 + ret i32 %v +} + +define i32 @rmw32_min_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_min_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: l32i a12, a2, 0 +; XTENSA-NEXT: movi a6, 1 +; XTENSA-NEXT: movi a5, 2 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a4, .LCPI24_0 +; XTENSA-NEXT: j .LBB24_2 +; XTENSA-NEXT: .LBB24_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB24_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a12, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB24_4 +; XTENSA-NEXT: .LBB24_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a12, a1, 0 +; XTENSA-NEXT: blt a12, a5, .LBB24_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB24_2 Depth=1 +; XTENSA-NEXT: or a12, a6, a6 +; XTENSA-NEXT: j .LBB24_1 +; XTENSA-NEXT: .LBB24_4: # %atomicrmw.end +; XTENSA-NEXT: or a2, a12, a12 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_min_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a9, a11, a11 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: bge a9, a8, .LBB24_3 +; XTENSA-ATOMIC-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1 +; XTENSA-ATOMIC-NEXT: mov.n a10, a8 +; XTENSA-ATOMIC-NEXT: .LBB24_3: # in Loop: Header=BB24_1 Depth=1 +; XTENSA-ATOMIC-NEXT: mov.n a10, a10 +; XTENSA-ATOMIC-NEXT: wsr a9, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a11, a10 +; XTENSA-ATOMIC-NEXT: bne a9, a10, .LBB24_1 +; XTENSA-ATOMIC-NEXT: # %bb.4: +; XTENSA-ATOMIC-NEXT: mov.n a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw min ptr %p, i32 1 seq_cst, align 4 + ret i32 %v +} + +define i32 @rmw32_umax_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_umax_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a5, 1 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a4, .LCPI25_0 +; XTENSA-NEXT: j .LBB25_2 +; XTENSA-NEXT: .LBB25_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB25_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB25_4 +; XTENSA-NEXT: .LBB25_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a5, a5 +; XTENSA-NEXT: bgeu a5, a2, .LBB25_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB25_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB25_1 +; XTENSA-NEXT: .LBB25_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_umax_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a9, a11, a11 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: bltu a9, a8, .LBB25_3 +; XTENSA-ATOMIC-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1 +; XTENSA-ATOMIC-NEXT: mov.n a10, a8 +; XTENSA-ATOMIC-NEXT: .LBB25_3: # in Loop: Header=BB25_1 Depth=1 +; XTENSA-ATOMIC-NEXT: mov.n a10, a10 +; XTENSA-ATOMIC-NEXT: wsr a9, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a11, a10 +; XTENSA-ATOMIC-NEXT: bne a9, a10, .LBB25_1 +; XTENSA-ATOMIC-NEXT: # %bb.4: +; XTENSA-ATOMIC-NEXT: mov.n a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw umax ptr %p, i32 1 seq_cst, align 4 + ret i32 %v +} + +define i32 @rmw32_umin_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_umin_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: l32i a12, a2, 0 +; XTENSA-NEXT: movi a6, 1 +; XTENSA-NEXT: movi a5, 2 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a4, .LCPI26_0 +; XTENSA-NEXT: j .LBB26_2 +; XTENSA-NEXT: .LBB26_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB26_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a12, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB26_4 +; XTENSA-NEXT: .LBB26_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a12, a1, 0 +; XTENSA-NEXT: bltu a12, a5, .LBB26_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB26_2 Depth=1 +; XTENSA-NEXT: or a12, a6, a6 +; XTENSA-NEXT: j .LBB26_1 +; XTENSA-NEXT: .LBB26_4: # %atomicrmw.end +; XTENSA-NEXT: or a2, a12, a12 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_umin_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a9, a11, a11 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: bgeu a9, a8, .LBB26_3 +; XTENSA-ATOMIC-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1 +; XTENSA-ATOMIC-NEXT: mov.n a10, a8 +; XTENSA-ATOMIC-NEXT: .LBB26_3: # in Loop: Header=BB26_1 Depth=1 +; XTENSA-ATOMIC-NEXT: mov.n a10, a10 +; XTENSA-ATOMIC-NEXT: wsr a9, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: mov.n a11, a10 +; XTENSA-ATOMIC-NEXT: bne a9, a10, .LBB26_1 +; XTENSA-ATOMIC-NEXT: # %bb.4: +; XTENSA-ATOMIC-NEXT: mov.n a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw umin ptr %p, i32 1 seq_cst, align 4 + ret i32 %v +} + +define i32 @rmw32_xchg_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_xchg_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a11, 1 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI27_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_xchg_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a9, 1 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a10, a10 +; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 +; XTENSA-ATOMIC-NEXT: or a10, a9, a9 +; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB27_1 +; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw xchg ptr %p, i32 1 seq_cst, align 4 + ret i32 %v +} + +define float @rmw32_fadd_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_fadd_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: l32i a10, a2, 0 +; XTENSA-NEXT: l32r a7, .LCPI28_0 +; XTENSA-NEXT: l32r a5, .LCPI28_1 +; XTENSA-NEXT: movi a6, 5 +; XTENSA-NEXT: l32r a4, .LCPI28_2 +; XTENSA-NEXT: .LBB28_1: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a10, a1, 0 +; XTENSA-NEXT: or a11, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: or a12, a10, a10 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: or a13, a6, a6 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: or a8, a10, a10 +; XTENSA-NEXT: l32i a10, a1, 0 +; XTENSA-NEXT: beqz a8, .LBB28_1 +; XTENSA-NEXT: # %bb.2: # %atomicrmw.end +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_fadd_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a6, a2, 0 +; XTENSA-ATOMIC-NEXT: l32r a7, .LCPI28_0 +; XTENSA-ATOMIC-NEXT: l32r a5, .LCPI28_1 +; XTENSA-ATOMIC-NEXT: movi a4, 0 +; XTENSA-ATOMIC-NEXT: movi a3, 1 +; XTENSA-ATOMIC-NEXT: j .LBB28_2 +; XTENSA-ATOMIC-NEXT: .LBB28_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB28_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a10, a10 +; XTENSA-ATOMIC-NEXT: beqi a8, 1, .LBB28_4 +; XTENSA-ATOMIC-NEXT: .LBB28_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a6, a6 +; XTENSA-ATOMIC-NEXT: or a11, a7, a7 +; XTENSA-ATOMIC-NEXT: callx8 a5 +; XTENSA-ATOMIC-NEXT: wsr a6, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: beq a10, a6, .LBB28_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB28_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: j .LBB28_1 +; XTENSA-ATOMIC-NEXT: .LBB28_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a10, a10 +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw fadd ptr %p, float 1.0 seq_cst, align 4 + ret float %v +} + +define float @rmw32_fsub_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_fsub_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: l32i a10, a2, 0 +; XTENSA-NEXT: l32r a7, .LCPI29_0 +; XTENSA-NEXT: l32r a5, .LCPI29_1 +; XTENSA-NEXT: movi a6, 5 +; XTENSA-NEXT: l32r a4, .LCPI29_2 +; XTENSA-NEXT: .LBB29_1: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a10, a1, 0 +; XTENSA-NEXT: or a11, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: or a12, a10, a10 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: or a13, a6, a6 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: or a8, a10, a10 +; XTENSA-NEXT: l32i a10, a1, 0 +; XTENSA-NEXT: beqz a8, .LBB29_1 +; XTENSA-NEXT: # %bb.2: # %atomicrmw.end +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_fsub_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a6, a2, 0 +; XTENSA-ATOMIC-NEXT: l32r a7, .LCPI29_0 +; XTENSA-ATOMIC-NEXT: l32r a5, .LCPI29_1 +; XTENSA-ATOMIC-NEXT: movi a4, 0 +; XTENSA-ATOMIC-NEXT: movi a3, 1 +; XTENSA-ATOMIC-NEXT: j .LBB29_2 +; XTENSA-ATOMIC-NEXT: .LBB29_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB29_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a10, a10 +; XTENSA-ATOMIC-NEXT: beqi a8, 1, .LBB29_4 +; XTENSA-ATOMIC-NEXT: .LBB29_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a6, a6 +; XTENSA-ATOMIC-NEXT: or a11, a7, a7 +; XTENSA-ATOMIC-NEXT: callx8 a5 +; XTENSA-ATOMIC-NEXT: wsr a6, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: beq a10, a6, .LBB29_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB29_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: j .LBB29_1 +; XTENSA-ATOMIC-NEXT: .LBB29_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a10, a10 +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw fsub ptr %p, float 1.0 seq_cst, align 4 + ret float %v +} + +define float @rmw32_fmin_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_fmin_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: l32i a10, a2, 0 +; XTENSA-NEXT: l32r a7, .LCPI30_0 +; XTENSA-NEXT: l32r a5, .LCPI30_1 +; XTENSA-NEXT: movi a6, 5 +; XTENSA-NEXT: l32r a4, .LCPI30_2 +; XTENSA-NEXT: .LBB30_1: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a10, a1, 0 +; XTENSA-NEXT: or a11, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: or a12, a10, a10 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: or a13, a6, a6 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: or a8, a10, a10 +; XTENSA-NEXT: l32i a10, a1, 0 +; XTENSA-NEXT: beqz a8, .LBB30_1 +; XTENSA-NEXT: # %bb.2: # %atomicrmw.end +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_fmin_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a6, a2, 0 +; XTENSA-ATOMIC-NEXT: l32r a7, .LCPI30_0 +; XTENSA-ATOMIC-NEXT: l32r a5, .LCPI30_1 +; XTENSA-ATOMIC-NEXT: movi a4, 0 +; XTENSA-ATOMIC-NEXT: movi a3, 1 +; XTENSA-ATOMIC-NEXT: j .LBB30_2 +; XTENSA-ATOMIC-NEXT: .LBB30_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB30_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a10, a10 +; XTENSA-ATOMIC-NEXT: beqi a8, 1, .LBB30_4 +; XTENSA-ATOMIC-NEXT: .LBB30_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a6, a6 +; XTENSA-ATOMIC-NEXT: or a11, a7, a7 +; XTENSA-ATOMIC-NEXT: callx8 a5 +; XTENSA-ATOMIC-NEXT: wsr a6, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: beq a10, a6, .LBB30_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB30_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: j .LBB30_1 +; XTENSA-ATOMIC-NEXT: .LBB30_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a10, a10 +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw fmin ptr %p, float 1.0 seq_cst, align 4 + ret float %v +} + +define float @rmw32_fmax_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: rmw32_fmax_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: l32i a10, a2, 0 +; XTENSA-NEXT: l32r a7, .LCPI31_0 +; XTENSA-NEXT: l32r a5, .LCPI31_1 +; XTENSA-NEXT: movi a6, 5 +; XTENSA-NEXT: l32r a4, .LCPI31_2 +; XTENSA-NEXT: .LBB31_1: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a10, a1, 0 +; XTENSA-NEXT: or a11, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: or a12, a10, a10 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: or a13, a6, a6 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: or a8, a10, a10 +; XTENSA-NEXT: l32i a10, a1, 0 +; XTENSA-NEXT: beqz a8, .LBB31_1 +; XTENSA-NEXT: # %bb.2: # %atomicrmw.end +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: rmw32_fmax_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a6, a2, 0 +; XTENSA-ATOMIC-NEXT: l32r a7, .LCPI31_0 +; XTENSA-ATOMIC-NEXT: l32r a5, .LCPI31_1 +; XTENSA-ATOMIC-NEXT: movi a4, 0 +; XTENSA-ATOMIC-NEXT: movi a3, 1 +; XTENSA-ATOMIC-NEXT: j .LBB31_2 +; XTENSA-ATOMIC-NEXT: .LBB31_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB31_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a10, a10 +; XTENSA-ATOMIC-NEXT: beqi a8, 1, .LBB31_4 +; XTENSA-ATOMIC-NEXT: .LBB31_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a10, a6, a6 +; XTENSA-ATOMIC-NEXT: or a11, a7, a7 +; XTENSA-ATOMIC-NEXT: callx8 a5 +; XTENSA-ATOMIC-NEXT: wsr a6, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: beq a10, a6, .LBB31_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB31_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: j .LBB31_1 +; XTENSA-ATOMIC-NEXT: .LBB31_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a10, a10 +; XTENSA-ATOMIC-NEXT: retw + %v = atomicrmw fmax ptr %p, float 1.0 seq_cst, align 4 + ret float %v +} + +define i32 @cmpxchg32_monotonic(ptr %p) nounwind { +; XTENSA-LABEL: cmpxchg32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a13, 0 +; XTENSA-NEXT: s32i a13, a1, 0 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: movi a12, 1 +; XTENSA-NEXT: l32r a8, .LCPI32_0 +; XTENSA-NEXT: or a14, a13, a13 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: cmpxchg32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: wsr a9, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = cmpxchg ptr %p, i32 0, i32 1 monotonic monotonic + %res.0 = extractvalue { i32, i1 } %res, 0 + ret i32 %res.0 +} + +define i32 @cmpxchg32_seq_cst(ptr %p) nounwind { +; XTENSA-LABEL: cmpxchg32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a8, 0 +; XTENSA-NEXT: s32i a8, a1, 0 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: movi a12, 1 +; XTENSA-NEXT: movi a13, 5 +; XTENSA-NEXT: l32r a8, .LCPI33_0 +; XTENSA-NEXT: or a14, a13, a13 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: cmpxchg32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: movi a8, 1 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: wsr a9, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = cmpxchg ptr %p, i32 0, i32 1 seq_cst seq_cst + %res.0 = extractvalue { i32, i1 } %res, 0 + ret i32 %res.0 +} From 4ea1f7efcb96b18489de9d7dbf1ddfabd0e48f25 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 5 Aug 2025 19:25:28 +0300 Subject: [PATCH 2/4] [Xtensa] Fix atomics. Remove redundant code. Simplify atomics implementation by using AtomicExpand pass. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 842 +- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 17 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 118 +- llvm/lib/Target/Xtensa/XtensaOperators.td | 5 - llvm/test/CodeGen/Xtensa/atomic-rmw.ll | 11556 ++++++++++++---- llvm/test/CodeGen/Xtensa/forced-atomics.ll | 694 +- 6 files changed, 8987 insertions(+), 4245 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index c56327b8c7334..6a07bd865a15a 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -250,31 +250,6 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM, // Floating-point truncation and stores need to be done separately. setTruncStoreAction(MVT::f64, MVT::f32, Expand); - // to have the best chance and doing something good with fences custom lower - // them - setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); - - if (!Subtarget.hasS32C1I()) { - for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE; - I <= MVT::LAST_INTEGER_VALUETYPE; ++I) { - MVT VT = MVT::SimpleValueType(I); - if (isTypeLegal(VT)) { - setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); - setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); - setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Expand); - setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Expand); - setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Expand); - setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Expand); - setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Expand); - setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand); - setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand); - setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand); - setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand); - setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand); - } - } - } - if (Subtarget.hasS32C1I()) { setMaxAtomicSizeInBitsSupported(32); setMinCmpXchgSizeInBits(32); @@ -1482,13 +1457,6 @@ bool XtensaTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT, return false; } -SDValue XtensaTargetLowering::LowerATOMIC_FENCE(SDValue Op, - SelectionDAG &DAG) const { - SDLoc DL(Op); - SDValue Chain = Op.getOperand(0); - return DAG.getNode(XtensaISD::MEMW, DL, MVT::Other, Chain); -} - SDValue XtensaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { @@ -1532,8 +1500,6 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerShiftRightParts(Op, DAG, true); case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false); - case ISD::ATOMIC_FENCE: - return LowerATOMIC_FENCE(Op, DAG); default: report_fatal_error("Unexpected node to lower"); } @@ -1591,6 +1557,11 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { return nullptr; } +TargetLowering::AtomicExpansionKind +XtensaTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const { + return AtomicExpansionKind::CmpXChg; +} + //===----------------------------------------------------------------------===// // Custom insertion //===----------------------------------------------------------------------===// @@ -1673,731 +1644,6 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI, return SinkMBB; } -// Emit instructions for atomic_cmp_swap node for 8/16 bit operands -MachineBasicBlock * -XtensaTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, MachineBasicBlock *BB, - int isByteOperand) const { - const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); - DebugLoc DL = MI.getDebugLoc(); - - const BasicBlock *LLVM_BB = BB->getBasicBlock(); - MachineFunction::iterator It = ++BB->getIterator(); - - MachineBasicBlock *thisBB = BB; - MachineFunction *F = BB->getParent(); - MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); - MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); - - F->insert(It, BBLoop); - F->insert(It, BBExit); - - // Transfer the remainder of BB and its successor edges to BBExit. - BBExit->splice(BBExit->begin(), BB, - std::next(MachineBasicBlock::iterator(MI)), BB->end()); - BBExit->transferSuccessorsAndUpdatePHIs(BB); - - BB->addSuccessor(BBLoop); - - MachineOperand &Res = MI.getOperand(0); - MachineOperand &AtomValAddr = MI.getOperand(1); - MachineOperand &CmpVal = MI.getOperand(2); - MachineOperand &SwpVal = MI.getOperand(3); - - MachineFunction *MF = BB->getParent(); - MachineRegisterInfo &MRI = MF->getRegInfo(); - const TargetRegisterClass *RC = getRegClassFor(MVT::i32); - - unsigned R1 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R1).addImm(3); - - unsigned ByteOffs = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), ByteOffs) - .addReg(R1) - .addReg(AtomValAddr.getReg()); - - unsigned AddrAlign = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SUB), AddrAlign) - .addReg(AtomValAddr.getReg()) - .addReg(ByteOffs); - - unsigned BitOffs = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), BitOffs) - .addReg(ByteOffs) - .addImm(3); - - unsigned Mask1 = MRI.createVirtualRegister(RC); - if (isByteOperand) { - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), Mask1).addImm(0xff); - } else { - unsigned R2 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(1); - unsigned R3 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), R3).addReg(R2).addImm(16); - BuildMI(*BB, MI, DL, TII.get(Xtensa::ADDI), Mask1).addReg(R3).addImm(-1); - } - - BuildMI(*BB, MI, DL, TII.get(Xtensa::SSL)).addReg(BitOffs); - - unsigned R2 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(-1); - - unsigned Mask2 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Mask2).addReg(Mask1); - - unsigned Mask3 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::XOR), Mask3).addReg(Mask2).addReg(R2); - - unsigned R3 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R3).addReg(AddrAlign).addImm(0); - - unsigned R4 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), R4).addReg(R3).addReg(Mask3); - - unsigned Cmp1 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Cmp1).addReg(CmpVal.getReg()); - - unsigned Swp1 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Swp1).addReg(SwpVal.getReg()); - - BB = BBLoop; - - unsigned MaskPhi = MRI.createVirtualRegister(RC); - unsigned MaskLoop = MRI.createVirtualRegister(RC); - - BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), MaskPhi) - .addReg(MaskLoop) - .addMBB(BBLoop) - .addReg(R4) - .addMBB(thisBB); - - unsigned Cmp2 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::OR), Cmp2).addReg(Cmp1).addReg(MaskPhi); - - unsigned Swp2 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::OR), Swp2).addReg(Swp1).addReg(MaskPhi); - - BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(Cmp2); - - unsigned Swp3 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::S32C1I), Swp3) - .addReg(Swp2) - .addReg(AddrAlign) - .addImm(0); - - BuildMI(BB, DL, TII.get(Xtensa::AND), MaskLoop).addReg(Swp3).addReg(Mask3); - - BuildMI(BB, DL, TII.get(Xtensa::BNE)) - .addReg(MaskLoop) - .addReg(MaskPhi) - .addMBB(BBLoop); - - BB->addSuccessor(BBLoop); - BB->addSuccessor(BBExit); - - BB = BBExit; - auto St = BBExit->begin(); - - unsigned R5 = MRI.createVirtualRegister(RC); - BuildMI(*BB, St, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); - - BuildMI(*BB, St, DL, TII.get(Xtensa::SRL), R5).addReg(Swp3); - - BuildMI(*BB, St, DL, TII.get(Xtensa::AND), Res.getReg()) - .addReg(R5) - .addReg(Mask1); - - MI.eraseFromParent(); // The pseudo instruction is gone now. - return BB; -} - -// Emit instructions for atomic_swap node for 8/16 bit operands -MachineBasicBlock * -XtensaTargetLowering::emitAtomicSwap(MachineInstr &MI, MachineBasicBlock *BB, - int isByteOperand) const { - const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); - DebugLoc DL = MI.getDebugLoc(); - - const BasicBlock *LLVM_BB = BB->getBasicBlock(); - MachineFunction::iterator It = ++BB->getIterator(); - - MachineFunction *F = BB->getParent(); - MachineBasicBlock *BBLoop1 = F->CreateMachineBasicBlock(LLVM_BB); - MachineBasicBlock *BBLoop2 = F->CreateMachineBasicBlock(LLVM_BB); - MachineBasicBlock *BBLoop3 = F->CreateMachineBasicBlock(LLVM_BB); - MachineBasicBlock *BBLoop4 = F->CreateMachineBasicBlock(LLVM_BB); - MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); - - F->insert(It, BBLoop1); - F->insert(It, BBLoop2); - F->insert(It, BBLoop3); - F->insert(It, BBLoop4); - F->insert(It, BBExit); - - // Transfer the remainder of BB and its successor edges to BBExit. - BBExit->splice(BBExit->begin(), BB, - std::next(MachineBasicBlock::iterator(MI)), BB->end()); - BBExit->transferSuccessorsAndUpdatePHIs(BB); - - BB->addSuccessor(BBLoop1); - BBLoop1->addSuccessor(BBLoop2); - BBLoop2->addSuccessor(BBLoop3); - BBLoop2->addSuccessor(BBLoop4); - BBLoop3->addSuccessor(BBLoop2); - BBLoop3->addSuccessor(BBLoop4); - BBLoop4->addSuccessor(BBLoop1); - BBLoop4->addSuccessor(BBExit); - - MachineOperand &Res = MI.getOperand(0); - MachineOperand &AtomValAddr = MI.getOperand(1); - MachineOperand &SwpVal = MI.getOperand(2); - - MachineFunction *MF = BB->getParent(); - MachineRegisterInfo &MRI = MF->getRegInfo(); - const TargetRegisterClass *RC = getRegClassFor(MVT::i32); - - unsigned R1 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R1).addImm(3); - - unsigned ByteOffs = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), ByteOffs) - .addReg(R1) - .addReg(AtomValAddr.getReg()); - - unsigned AddrAlign = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SUB), AddrAlign) - .addReg(AtomValAddr.getReg()) - .addReg(ByteOffs); - - unsigned BitOffs = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), BitOffs) - .addReg(ByteOffs) - .addImm(3); - - unsigned Mask1 = MRI.createVirtualRegister(RC); - if (isByteOperand) { - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), Mask1).addImm(0xff); - } else { - unsigned R2 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(1); - unsigned R3 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), R3).addReg(R2).addImm(16); - BuildMI(*BB, MI, DL, TII.get(Xtensa::ADDI), Mask1).addReg(R3).addImm(-1); - } - - BuildMI(*BB, MI, DL, TII.get(Xtensa::SSL)).addReg(BitOffs); - - unsigned R2 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(-1); - - unsigned Mask2 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Mask2).addReg(Mask1); - - unsigned Mask3 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::XOR), Mask3).addReg(Mask2).addReg(R2); - - unsigned R3 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R3).addReg(AddrAlign).addImm(0); - - unsigned R4 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), R4).addReg(R3).addReg(Mask3); - - unsigned SwpValShifted = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), SwpValShifted) - .addReg(SwpVal.getReg()); - - unsigned R5 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R5).addReg(AddrAlign).addImm(0); - - unsigned AtomVal = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), AtomVal).addReg(R5).addReg(Mask2); - - unsigned AtomValPhi = MRI.createVirtualRegister(RC); - unsigned AtomValLoop = MRI.createVirtualRegister(RC); - - BuildMI(*BBLoop1, BBLoop1->begin(), DL, TII.get(Xtensa::PHI), AtomValPhi) - .addReg(AtomValLoop) - .addMBB(BBLoop4) - .addReg(AtomVal) - .addMBB(BB); - - BB = BBLoop1; - - BuildMI(BB, DL, TII.get(Xtensa::MEMW)); - - unsigned R6 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::L32I), R6).addReg(AddrAlign).addImm(0); - - unsigned R7 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::AND), R7).addReg(R6).addReg(Mask3); - - unsigned MaskPhi = MRI.createVirtualRegister(RC); - unsigned MaskLoop = MRI.createVirtualRegister(RC); - - BuildMI(*BBLoop2, BBLoop2->begin(), DL, TII.get(Xtensa::PHI), MaskPhi) - .addReg(MaskLoop) - .addMBB(BBLoop3) - .addReg(R7) - .addMBB(BBLoop1); - - BB = BBLoop2; - - unsigned Swp1 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::OR), Swp1) - .addReg(SwpValShifted) - .addReg(MaskPhi); - - unsigned AtomVal1 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::OR), AtomVal1) - .addReg(AtomValPhi) - .addReg(MaskPhi); - - BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(AtomVal1); - - unsigned Swp2 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::S32C1I), Swp2) - .addReg(Swp1) - .addReg(AddrAlign) - .addImm(0); - - BuildMI(BB, DL, TII.get(Xtensa::BEQ)) - .addReg(AtomVal1) - .addReg(Swp2) - .addMBB(BBLoop4); - - BB = BBLoop3; - - BuildMI(BB, DL, TII.get(Xtensa::AND), MaskLoop).addReg(Swp2).addReg(Mask3); - - BuildMI(BB, DL, TII.get(Xtensa::BNE)) - .addReg(MaskLoop) - .addReg(MaskPhi) - .addMBB(BBLoop2); - - BB = BBLoop4; - - BuildMI(BB, DL, TII.get(Xtensa::AND), AtomValLoop).addReg(Swp2).addReg(Mask2); - - BuildMI(BB, DL, TII.get(Xtensa::BNE)) - .addReg(AtomValLoop) - .addReg(AtomValPhi) - .addMBB(BBLoop1); - - BB = BBExit; - - auto St = BB->begin(); - - unsigned R8 = MRI.createVirtualRegister(RC); - - BuildMI(*BB, St, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); - BuildMI(*BB, St, DL, TII.get(Xtensa::SRL), R8).addReg(AtomValLoop); - - if (isByteOperand) { - BuildMI(*BB, St, DL, TII.get(Xtensa::SEXT), Res.getReg()) - .addReg(R8) - .addImm(7); - } else { - BuildMI(*BB, St, DL, TII.get(Xtensa::SEXT), Res.getReg()) - .addReg(R8) - .addImm(15); - } - - MI.eraseFromParent(); // The pseudo instruction is gone now. - return BB; -} - -// Emit instructions for atomic_swap node for 32 bit operands -MachineBasicBlock * -XtensaTargetLowering::emitAtomicSwap(MachineInstr &MI, - MachineBasicBlock *BB) const { - const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); - DebugLoc DL = MI.getDebugLoc(); - - const BasicBlock *LLVM_BB = BB->getBasicBlock(); - MachineFunction::iterator It = ++BB->getIterator(); - - MachineFunction *F = BB->getParent(); - MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); - MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); - - F->insert(It, BBLoop); - F->insert(It, BBExit); - - // Transfer the remainder of BB and its successor edges to BBExit. - BBExit->splice(BBExit->begin(), BB, - std::next(MachineBasicBlock::iterator(MI)), BB->end()); - BBExit->transferSuccessorsAndUpdatePHIs(BB); - - BB->addSuccessor(BBLoop); - BBLoop->addSuccessor(BBLoop); - BBLoop->addSuccessor(BBExit); - - MachineOperand &Res = MI.getOperand(0); - MachineOperand &AtomValAddr = MI.getOperand(1); - MachineOperand &SwpVal = MI.getOperand(2); - - MachineFunction *MF = BB->getParent(); - MachineRegisterInfo &MRI = MF->getRegInfo(); - const TargetRegisterClass *RC = getRegClassFor(MVT::i32); - - BuildMI(*BB, MI, DL, TII.get(Xtensa::MEMW)); - - unsigned AtomVal = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), AtomVal) - .addReg(AtomValAddr.getReg()) - .addImm(0); - - unsigned AtomValLoop = MRI.createVirtualRegister(RC); - - BuildMI(*BBLoop, BBLoop->begin(), DL, TII.get(Xtensa::PHI), Res.getReg()) - .addReg(AtomValLoop) - .addMBB(BBLoop) - .addReg(AtomVal) - .addMBB(BB); - - BB = BBLoop; - - BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(Res.getReg()); - - BuildMI(BB, DL, TII.get(Xtensa::S32C1I), AtomValLoop) - .addReg(SwpVal.getReg()) - .addReg(AtomValAddr.getReg()) - .addImm(0); - - BuildMI(BB, DL, TII.get(Xtensa::BNE)) - .addReg(AtomValLoop) - .addReg(Res.getReg()) - .addMBB(BBLoop); - - MI.eraseFromParent(); // The pseudo instruction is gone now. - return BB; -} - -MachineBasicBlock *XtensaTargetLowering::emitAtomicRMW(MachineInstr &MI, - MachineBasicBlock *BB, - unsigned Opcode, - bool inv, - bool minmax) const { - const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); - DebugLoc DL = MI.getDebugLoc(); - - const BasicBlock *LLVM_BB = BB->getBasicBlock(); - MachineFunction::iterator It = ++BB->getIterator(); - - MachineBasicBlock *ThisBB = BB; - MachineFunction *F = BB->getParent(); - MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); - MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); - - F->insert(It, BBLoop); - F->insert(It, BBExit); - - // Transfer the remainder of BB and its successor edges to BB2. - BBExit->splice(BBExit->begin(), BB, - std::next(MachineBasicBlock::iterator(MI)), BB->end()); - BBExit->transferSuccessorsAndUpdatePHIs(BB); - - BB->addSuccessor(BBLoop); - - MachineOperand &Res = MI.getOperand(0); - MachineOperand &AtomicValAddr = MI.getOperand(1); - MachineOperand &Val = MI.getOperand(2); - MachineFunction *MF = BB->getParent(); - MachineRegisterInfo &MRI = MF->getRegInfo(); - const TargetRegisterClass *RC = getRegClassFor(MVT::i32); - - unsigned R1 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R1) - .addReg(AtomicValAddr.getReg()) - .addImm(0); - - BB = BBLoop; - - unsigned AtomicValPhi = MRI.createVirtualRegister(RC); - unsigned AtomicValLoop = MRI.createVirtualRegister(RC); - unsigned R2 = MRI.createVirtualRegister(RC); - - if (minmax) { - MachineBasicBlock *BBLoop1 = F->CreateMachineBasicBlock(LLVM_BB); - F->insert(++BB->getIterator(), BBLoop1); - BB->addSuccessor(BBLoop1); - MachineBasicBlock *BBLoop2 = F->CreateMachineBasicBlock(LLVM_BB); - F->insert(++BB->getIterator(), BBLoop2); - BB->addSuccessor(BBLoop2); - BBLoop2->addSuccessor(BBLoop1); - - BuildMI(BB, DL, TII.get(Opcode)) - .addReg(AtomicValPhi) - .addReg(Val.getReg()) - .addMBB(BBLoop1); - - unsigned R7 = MRI.createVirtualRegister(RC); - BuildMI(BBLoop2, DL, TII.get(Xtensa::MOV_N), R7).addReg(Val.getReg()); - - BB = BBLoop1; - unsigned R8 = MRI.createVirtualRegister(RC); - BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), R8) - .addReg(R7) - .addMBB(BBLoop2) - .addReg(AtomicValPhi) - .addMBB(BBLoop); - BuildMI(BB, DL, TII.get(Xtensa::MOV_N), R2).addReg(R8); - } else { - BuildMI(BB, DL, TII.get(Opcode), R2) - .addReg(AtomicValPhi) - .addReg(Val.getReg()); - if (inv) { - unsigned Rtmp1 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::MOVI), Rtmp1).addImm(-1); - unsigned Rtmp2 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::XOR), Rtmp2).addReg(R2).addReg(Rtmp1); - R2 = Rtmp2; - } - } - - BuildMI(*BBLoop, BBLoop->begin(), DL, TII.get(Xtensa::PHI), AtomicValPhi) - .addReg(AtomicValLoop) - .addMBB(BB) - .addReg(R1) - .addMBB(ThisBB); - - unsigned R4 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(AtomicValPhi); - BuildMI(BB, DL, TII.get(Xtensa::S32C1I), R4) - .addReg(R2) - .addReg(AtomicValAddr.getReg(), getKillRegState(AtomicValAddr.isDead())) - .addImm(0); - - BuildMI(BB, DL, TII.get(Xtensa::MOV_N), AtomicValLoop).addReg(R4); - - BuildMI(BB, DL, TII.get(Xtensa::BNE)) - .addReg(AtomicValPhi) - .addReg(R4) - .addMBB(BBLoop); - - BB->addSuccessor(BBLoop); - BB->addSuccessor(BBExit); - - BB = BBExit; - auto St = BBExit->begin(); - - BuildMI(*BB, St, DL, TII.get(Xtensa::MOV_N), Res.getReg()).addReg(R4); - - MI.eraseFromParent(); // The pseudo instruction is gone now. - return BB; -} - -MachineBasicBlock * -XtensaTargetLowering::emitAtomicRMW(MachineInstr &MI, MachineBasicBlock *BB, - bool isByteOperand, unsigned Opcode, - bool inv, bool minmax) const { - const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); - DebugLoc DL = MI.getDebugLoc(); - - const BasicBlock *LLVM_BB = BB->getBasicBlock(); - MachineFunction::iterator It = ++BB->getIterator(); - - MachineBasicBlock *ThisBB = BB; - MachineFunction *F = BB->getParent(); - MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); - MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); - - F->insert(It, BBLoop); - F->insert(It, BBExit); - - // Transfer the remainder of BB and its successor edges to BB2. - BBExit->splice(BBExit->begin(), BB, - std::next(MachineBasicBlock::iterator(MI)), BB->end()); - BBExit->transferSuccessorsAndUpdatePHIs(BB); - - BB->addSuccessor(BBLoop); - - MachineOperand &Res = MI.getOperand(0); - MachineOperand &AtomValAddr = MI.getOperand(1); - MachineOperand &Val = MI.getOperand(2); - - MachineFunction *MF = BB->getParent(); - MachineRegisterInfo &MRI = MF->getRegInfo(); - const TargetRegisterClass *RC = getRegClassFor(MVT::i32); - - unsigned R1 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R1).addImm(3); - - unsigned ByteOffs = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), ByteOffs) - .addReg(R1) - .addReg(AtomValAddr.getReg()); - - unsigned AddrAlign = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SUB), AddrAlign) - .addReg(AtomValAddr.getReg()) - .addReg(ByteOffs); - - unsigned BitOffs = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), BitOffs) - .addReg(ByteOffs) - .addImm(3); - - unsigned Mask1 = MRI.createVirtualRegister(RC); - if (isByteOperand) { - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), Mask1).addImm(0xff); - } else { - unsigned R2 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(1); - unsigned R3 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), R3).addReg(R2).addImm(16); - BuildMI(*BB, MI, DL, TII.get(Xtensa::ADDI), Mask1).addReg(R3).addImm(-1); - } - - BuildMI(*BB, MI, DL, TII.get(Xtensa::SSL)).addReg(BitOffs); - - unsigned R2 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(-1); - - unsigned Mask2 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Mask2).addReg(Mask1); - - unsigned Mask3 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::XOR), Mask3).addReg(Mask2).addReg(R2); - - unsigned R3 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R3).addReg(AddrAlign).addImm(0); - - unsigned Val1 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Val1).addReg(Val.getReg()); - - BB = BBLoop; - - unsigned AtomicValPhi = MRI.createVirtualRegister(RC); - unsigned AtomicValLoop = MRI.createVirtualRegister(RC); - unsigned Swp2; - - if (minmax) { - MachineBasicBlock *BBLoop1 = F->CreateMachineBasicBlock(LLVM_BB); - F->insert(++BB->getIterator(), BBLoop1); - BB->addSuccessor(BBLoop1); - MachineBasicBlock *BBLoop2 = F->CreateMachineBasicBlock(LLVM_BB); - F->insert(++BB->getIterator(), BBLoop2); - BB->addSuccessor(BBLoop2); - BBLoop2->addSuccessor(BBLoop1); - - unsigned R1 = MRI.createVirtualRegister(RC); - unsigned R2 = MRI.createVirtualRegister(RC); - unsigned R3 = MRI.createVirtualRegister(RC); - unsigned R4 = MRI.createVirtualRegister(RC); - - unsigned R5 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::AND), R5) - .addReg(AtomicValPhi) - .addReg(Mask2); - - BuildMI(BB, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); - BuildMI(BB, DL, TII.get(Xtensa::SRL), R1).addReg(R5); - BuildMI(BB, DL, TII.get(Xtensa::SRL), R2).addReg(Val1); - - if ((Opcode == Xtensa::BLT) || (Opcode == Xtensa::BGE)) { - if (isByteOperand) { - BuildMI(BB, DL, TII.get(Xtensa::SEXT), R3).addReg(R1).addImm(7); - BuildMI(BB, DL, TII.get(Xtensa::SEXT), R4).addReg(R2).addImm(7); - } else { - BuildMI(BB, DL, TII.get(Xtensa::SEXT), R3).addReg(R1).addImm(15); - BuildMI(BB, DL, TII.get(Xtensa::SEXT), R4).addReg(R2).addImm(15); - } - } else { - R3 = R1; - R4 = R2; - } - - BuildMI(BB, DL, TII.get(Opcode)).addReg(R3).addReg(R4).addMBB(BBLoop1); - unsigned R7 = MRI.createVirtualRegister(RC); - BuildMI(BBLoop2, DL, TII.get(Xtensa::MOV_N), R7).addReg(Val1); - - BB = BBLoop1; - unsigned R9 = MRI.createVirtualRegister(RC); - BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), R9) - .addReg(R7) - .addMBB(BBLoop2) - .addReg(AtomicValPhi) - .addMBB(BBLoop); - - unsigned R10 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::AND), R10) - .addReg(AtomicValPhi) - .addReg(Mask3); - - unsigned R11 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::AND), R11).addReg(R9).addReg(Mask2); - - Swp2 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::OR), Swp2).addReg(R10).addReg(R11); - } else { - unsigned R4 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::AND), R4) - .addReg(AtomicValPhi) - .addReg(Mask2); - - unsigned Res1 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Opcode), Res1).addReg(R4).addReg(Val1); - - unsigned Swp1 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::AND), Swp1).addReg(Res1).addReg(Mask2); - - unsigned R5 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::AND), R5) - .addReg(AtomicValPhi) - .addReg(Mask3); - - if (inv) { - unsigned Rtmp1 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::XOR), Rtmp1) - .addReg(AtomicValPhi) - .addReg(Mask2); - R5 = Rtmp1; - } - - Swp2 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::OR), Swp2).addReg(Swp1).addReg(R5); - } - - BuildMI(*BBLoop, BBLoop->begin(), DL, TII.get(Xtensa::PHI), AtomicValPhi) - .addReg(AtomicValLoop) - .addMBB(BB) - .addReg(R3) - .addMBB(ThisBB); - - unsigned Swp3 = MRI.createVirtualRegister(RC); - BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(AtomicValPhi); - BuildMI(BB, DL, TII.get(Xtensa::S32C1I), Swp3) - .addReg(Swp2) - .addReg(AddrAlign) - .addImm(0); - - BuildMI(BB, DL, TII.get(Xtensa::MOV_N), AtomicValLoop).addReg(Swp3); - - BuildMI(BB, DL, TII.get(Xtensa::BNE)) - .addReg(Swp3) - .addReg(AtomicValPhi) - .addMBB(BBLoop); - - BB->addSuccessor(BBLoop); - BB->addSuccessor(BBExit); - BB = BBExit; - auto St = BBExit->begin(); - - unsigned R6 = MRI.createVirtualRegister(RC); - - BuildMI(*BB, St, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); - - BuildMI(*BB, St, DL, TII.get(Xtensa::SRL), R6).addReg(AtomicValLoop); - - BuildMI(*BB, St, DL, TII.get(Xtensa::AND), Res.getReg()) - .addReg(R6) - .addReg(Mask1); - - MI.eraseFromParent(); // The pseudo instruction is gone now. - - return BB; -} - MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( MachineInstr &MI, MachineBasicBlock *MBB) const { DebugLoc DL = MI.getDebugLoc(); @@ -2464,12 +1710,6 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( return MBB; } - case Xtensa::ATOMIC_CMP_SWAP_8_P: { - return emitAtomicCmpSwap(MI, MBB, 1); - } - case Xtensa::ATOMIC_CMP_SWAP_16_P: { - return emitAtomicCmpSwap(MI, MBB, 0); - } case Xtensa::ATOMIC_CMP_SWAP_32_P: { MachineOperand &R = MI.getOperand(0); MachineOperand &Addr = MI.getOperand(1); @@ -2487,78 +1727,6 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( MI.eraseFromParent(); return MBB; } - case Xtensa::ATOMIC_SWAP_8_P: { - return emitAtomicSwap(MI, MBB, 1); - } - case Xtensa::ATOMIC_SWAP_16_P: { - return emitAtomicSwap(MI, MBB, 0); - } - case Xtensa::ATOMIC_SWAP_32_P: { - return emitAtomicSwap(MI, MBB); - } - case Xtensa::ATOMIC_LOAD_ADD_8_P: - return emitAtomicRMW(MI, MBB, true, Xtensa::ADD, false, false); - case Xtensa::ATOMIC_LOAD_SUB_8_P: - return emitAtomicRMW(MI, MBB, true, Xtensa::SUB, false, false); - case Xtensa::ATOMIC_LOAD_OR_8_P: - return emitAtomicRMW(MI, MBB, true, Xtensa::OR, false, false); - case Xtensa::ATOMIC_LOAD_XOR_8_P: - return emitAtomicRMW(MI, MBB, true, Xtensa::XOR, false, false); - case Xtensa::ATOMIC_LOAD_AND_8_P: - return emitAtomicRMW(MI, MBB, true, Xtensa::AND, false, false); - case Xtensa::ATOMIC_LOAD_NAND_8_P: - return emitAtomicRMW(MI, MBB, true, Xtensa::AND, true, false); - case Xtensa::ATOMIC_LOAD_MIN_8_P: - return emitAtomicRMW(MI, MBB, true, Xtensa::BGE, false, true); - case Xtensa::ATOMIC_LOAD_MAX_8_P: - return emitAtomicRMW(MI, MBB, true, Xtensa::BLT, false, true); - case Xtensa::ATOMIC_LOAD_UMIN_8_P: - return emitAtomicRMW(MI, MBB, true, Xtensa::BGEU, false, true); - case Xtensa::ATOMIC_LOAD_UMAX_8_P: - return emitAtomicRMW(MI, MBB, true, Xtensa::BLTU, false, true); - - case Xtensa::ATOMIC_LOAD_ADD_16_P: - return emitAtomicRMW(MI, MBB, false, Xtensa::ADD, false, false); - case Xtensa::ATOMIC_LOAD_SUB_16_P: - return emitAtomicRMW(MI, MBB, false, Xtensa::SUB, false, false); - case Xtensa::ATOMIC_LOAD_OR_16_P: - return emitAtomicRMW(MI, MBB, false, Xtensa::OR, false, false); - case Xtensa::ATOMIC_LOAD_XOR_16_P: - return emitAtomicRMW(MI, MBB, false, Xtensa::XOR, false, false); - case Xtensa::ATOMIC_LOAD_AND_16_P: - return emitAtomicRMW(MI, MBB, false, Xtensa::AND, false, false); - case Xtensa::ATOMIC_LOAD_NAND_16_P: - return emitAtomicRMW(MI, MBB, false, Xtensa::AND, true, false); - case Xtensa::ATOMIC_LOAD_MIN_16_P: - return emitAtomicRMW(MI, MBB, false, Xtensa::BGE, false, true); - case Xtensa::ATOMIC_LOAD_MAX_16_P: - return emitAtomicRMW(MI, MBB, false, Xtensa::BLT, false, true); - case Xtensa::ATOMIC_LOAD_UMIN_16_P: - return emitAtomicRMW(MI, MBB, false, Xtensa::BGEU, false, true); - case Xtensa::ATOMIC_LOAD_UMAX_16_P: - return emitAtomicRMW(MI, MBB, false, Xtensa::BLTU, false, true); - - case Xtensa::ATOMIC_LOAD_ADD_32_P: - return emitAtomicRMW(MI, MBB, Xtensa::ADD, false, false); - case Xtensa::ATOMIC_LOAD_SUB_32_P: - return emitAtomicRMW(MI, MBB, Xtensa::SUB, false, false); - case Xtensa::ATOMIC_LOAD_OR_32_P: - return emitAtomicRMW(MI, MBB, Xtensa::OR, false, false); - case Xtensa::ATOMIC_LOAD_XOR_32_P: - return emitAtomicRMW(MI, MBB, Xtensa::XOR, false, false); - case Xtensa::ATOMIC_LOAD_AND_32_P: - return emitAtomicRMW(MI, MBB, Xtensa::AND, false, false); - case Xtensa::ATOMIC_LOAD_NAND_32_P: - return emitAtomicRMW(MI, MBB, Xtensa::AND, true, false); - case Xtensa::ATOMIC_LOAD_MIN_32_P: - return emitAtomicRMW(MI, MBB, Xtensa::BGE, false, true); - case Xtensa::ATOMIC_LOAD_MAX_32_P: - return emitAtomicRMW(MI, MBB, Xtensa::BLT, false, true); - case Xtensa::ATOMIC_LOAD_UMIN_32_P: - return emitAtomicRMW(MI, MBB, Xtensa::BGEU, false, true); - case Xtensa::ATOMIC_LOAD_UMAX_32_P: - return emitAtomicRMW(MI, MBB, Xtensa::BLTU, false, true); - default: llvm_unreachable("Unexpected instr type to insert"); } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index c3b1f858c8983..d84cbdb6afcef 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -37,7 +37,6 @@ enum { // of the field [1..16] EXTUI, - MEMW, MOVSP, // Wraps a TargetGlobalAddress that should be loaded using PC-relative @@ -150,6 +149,8 @@ class XtensaTargetLowering : public TargetLowering { return true; } + AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; + bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override; @@ -200,26 +201,12 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; - SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; - SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const; CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; MachineBasicBlock *emitSelectCC(MachineInstr &MI, MachineBasicBlock *BB) const; - MachineBasicBlock *emitAtomicSwap(MachineInstr &MI, MachineBasicBlock *BB, - int isByteOperand) const; - MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI, MachineBasicBlock *BB, - int isByteOperand) const; - MachineBasicBlock *emitAtomicSwap(MachineInstr &MI, - MachineBasicBlock *BB) const; - MachineBasicBlock *emitAtomicRMW(MachineInstr &MI, MachineBasicBlock *BB, - bool isByteOperand, unsigned Opcode, - bool inv, bool minmax) const; - MachineBasicBlock *emitAtomicRMW(MachineInstr &MI, MachineBasicBlock *BB, - unsigned Opcode, bool inv, - bool minmax) const; }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 06a9de1bce7e5..edcf2473d45cd 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -496,7 +496,7 @@ def EXTW : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins), let hasSideEffects = 1; } -def : Pat<(Xtensa_mem_barrier), (MEMW)>; +def : Pat<(atomic_fence timm, timm), (MEMW)>; //===----------------------------------------------------------------------===// // Illegal instructions @@ -1535,125 +1535,9 @@ let Predicates = [HasAtomicLdSt] in { } let usesCustomInserter = 1, Predicates = [HasS32C1I] in { - def ATOMIC_CMP_SWAP_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap), - "!atomic_cmp_swap_8_p, $dst, $ptr, $cmp, $swap", - [(set AR:$dst, (atomic_cmp_swap_i8 AR:$ptr, AR:$cmp, AR:$swap))]>; - def ATOMIC_CMP_SWAP_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap), - "!atomic_cmp_swap_16_p, $dst, $ptr, $cmp, $swap", - [(set AR:$dst, (atomic_cmp_swap_i16 AR:$ptr, AR:$cmp, AR:$swap))]>; def ATOMIC_CMP_SWAP_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap), "!atomic_cmp_swap_32_p, $dst, $ptr, $cmp, $swap", [(set AR:$dst, (atomic_cmp_swap_i32 AR:$ptr, AR:$cmp, AR:$swap))]>; - - def ATOMIC_SWAP_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$swap), - "!atomic_swap_8_p, $dst, $ptr, $swap", - [(set AR:$dst, (atomic_swap_i8 AR:$ptr, AR:$swap))]>; - def ATOMIC_SWAP_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$swap), - "!atomic_swap_16_p, $dst, $ptr, $swap", - [(set AR:$dst, (atomic_swap_i16 AR:$ptr, AR:$swap))]>; - def ATOMIC_SWAP_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$swap), - "!atomic_swap_32_p, $dst, $ptr, $swap", - [(set AR:$dst, (atomic_swap_i32 AR:$ptr, AR:$swap))]>; - - def ATOMIC_LOAD_ADD_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_add_8_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_add_i8 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_ADD_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_add_16_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_add_i16 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_ADD_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_add_32_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_add_i32 AR:$ptr, AR:$arg))]>; - - def ATOMIC_LOAD_SUB_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_sub_8_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_sub_i8 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_SUB_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_sub_16_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_sub_i16 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_SUB_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_sub_32_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_sub_i32 AR:$ptr, AR:$arg))]>; - - def ATOMIC_LOAD_AND_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_and_8_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_and_i8 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_AND_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_and_16_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_and_i16 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_AND_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_and_32_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_and_i32 AR:$ptr, AR:$arg))]>; - - def ATOMIC_LOAD_OR_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_or_8_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_or_i8 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_OR_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_or_16_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_or_i16 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_OR_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_or_32_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_or_i32 AR:$ptr, AR:$arg))]>; - - def ATOMIC_LOAD_XOR_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_xor_8_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_xor_i8 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_XOR_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_xor_16_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_xor_i16 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_XOR_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_xor_32_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_xor_i32 AR:$ptr, AR:$arg))]>; - - def ATOMIC_LOAD_NAND_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_nand_8_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_nand_i8 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_NAND_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_nand_16_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_nand_i16 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_NAND_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_nand_32_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_nand_i32 AR:$ptr, AR:$arg))]>; - - def ATOMIC_LOAD_MIN_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_min_8_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_min_i8 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_MIN_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_min_16_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_min_i16 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_MIN_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_min_32_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_min_i32 AR:$ptr, AR:$arg))]>; - - def ATOMIC_LOAD_MAX_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_max_8_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_max_i8 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_MAX_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_max_16_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_max_i16 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_MAX_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_max_32_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_max_i32 AR:$ptr, AR:$arg))]>; - - def ATOMIC_LOAD_UMIN_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_umin_8_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_umin_i8 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_UMIN_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_umin_16_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_umin_i16 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_UMIN_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_umin_32_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_umin_i32 AR:$ptr, AR:$arg))]>; - - def ATOMIC_LOAD_UMAX_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_umax_8_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_umax_i8 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_UMAX_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_umax_16_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_umax_i16 AR:$ptr, AR:$arg))]>; - def ATOMIC_LOAD_UMAX_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), - "!atomic_load_umax_32_p, $dst, $ptr, $arg", - [(set AR:$dst, (atomic_load_umax_i32 AR:$ptr, AR:$arg))]>; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index ce882b3ce4ea0..56be3d51505e1 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -39,8 +39,6 @@ def SDT_XtensaEXTUI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCi def SDT_XtensaMOVSP : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; -def SDT_XtensaMEMBARRIER : SDTypeProfile<0, 0, []>; - def SDT_XtensaRUR : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; //===----------------------------------------------------------------------===// @@ -81,9 +79,6 @@ def Xtensa_extui: SDNode<"XtensaISD::EXTUI", SDT_XtensaEXTUI>; def Xtensa_movsp: SDNode<"XtensaISD::MOVSP", SDT_XtensaMOVSP, [SDNPHasChain, SDNPSideEffect, SDNPInGlue]>; -def Xtensa_mem_barrier: SDNode<"XtensaISD::MEMW", SDT_XtensaMEMBARRIER, - [SDNPHasChain, SDNPSideEffect]>; - def Xtensa_rur: SDNode<"XtensaISD::RUR", SDT_XtensaRUR, [SDNPInGlue]>; diff --git a/llvm/test/CodeGen/Xtensa/atomic-rmw.ll b/llvm/test/CodeGen/Xtensa/atomic-rmw.ll index 43a9ba247e10d..c2b0092f226b5 100644 --- a/llvm/test/CodeGen/Xtensa/atomic-rmw.ll +++ b/llvm/test/CodeGen/Xtensa/atomic-rmw.ll @@ -17,46 +17,45 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 ; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a11, -1 ; XTENSA-ATOMIC-NEXT: sll a10, a10 -; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 -; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: and a14, a13, a10 -; XTENSA-ATOMIC-NEXT: .LBB0_1: # =>This Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: # Child Loop BB0_2 Depth 2 -; XTENSA-ATOMIC-NEXT: or a13, a14, a14 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: .LBB0_2: # Parent Loop BB0_1 Depth=1 -; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 -; XTENSA-ATOMIC-NEXT: or a15, a7, a7 -; XTENSA-ATOMIC-NEXT: or a14, a12, a15 -; XTENSA-ATOMIC-NEXT: or a7, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB0_4 -; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB0_2 Depth=2 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB0_2 -; XTENSA-ATOMIC-NEXT: .LBB0_4: # in Loop: Header=BB0_1 Depth=1 -; XTENSA-ATOMIC-NEXT: and a14, a14, a10 -; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB0_1 -; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB0_2 +; XTENSA-ATOMIC-NEXT: .LBB0_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB0_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB0_4 +; XTENSA-ATOMIC-NEXT: .LBB0_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a15, a10 +; XTENSA-ATOMIC-NEXT: or a14, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a11, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB0_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB0_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB0_1 +; XTENSA-ATOMIC-NEXT: .LBB0_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: sext a2, a8, 7 +; XTENSA-ATOMIC-NEXT: srl a2, a14 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i8 %b monotonic - ret i8 %1 + %res = atomicrmw xchg ptr %a, i8 %b monotonic + ret i8 %res } define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { @@ -74,47 +73,46 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 ; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a11, -1 ; XTENSA-ATOMIC-NEXT: sll a10, a10 -; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 -; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: and a14, a13, a10 -; XTENSA-ATOMIC-NEXT: .LBB1_1: # =>This Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: # Child Loop BB1_2 Depth 2 -; XTENSA-ATOMIC-NEXT: or a13, a14, a14 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: .LBB1_2: # Parent Loop BB1_1 Depth=1 -; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 -; XTENSA-ATOMIC-NEXT: or a15, a7, a7 -; XTENSA-ATOMIC-NEXT: or a14, a12, a15 -; XTENSA-ATOMIC-NEXT: or a7, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB1_4 -; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=2 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB1_2 -; XTENSA-ATOMIC-NEXT: .LBB1_4: # in Loop: Header=BB1_1 Depth=1 -; XTENSA-ATOMIC-NEXT: and a14, a14, a10 -; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB1_1 -; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB1_2 +; XTENSA-ATOMIC-NEXT: .LBB1_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB1_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB1_4 +; XTENSA-ATOMIC-NEXT: .LBB1_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a15, a10 +; XTENSA-ATOMIC-NEXT: or a14, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a11, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB1_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB1_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB1_1 +; XTENSA-ATOMIC-NEXT: .LBB1_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: sext a2, a8, 7 +; XTENSA-ATOMIC-NEXT: srl a2, a14 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i8 %b acquire - ret i8 %1 + %res = atomicrmw xchg ptr %a, i8 %b acquire + ret i8 %res } define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { @@ -132,47 +130,46 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 ; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a11, -1 ; XTENSA-ATOMIC-NEXT: sll a10, a10 -; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 -; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: and a14, a13, a10 -; XTENSA-ATOMIC-NEXT: .LBB2_1: # =>This Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: # Child Loop BB2_2 Depth 2 -; XTENSA-ATOMIC-NEXT: or a13, a14, a14 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: .LBB2_2: # Parent Loop BB2_1 Depth=1 -; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 -; XTENSA-ATOMIC-NEXT: or a15, a7, a7 -; XTENSA-ATOMIC-NEXT: or a14, a12, a15 -; XTENSA-ATOMIC-NEXT: or a7, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB2_4 -; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB2_2 Depth=2 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB2_2 -; XTENSA-ATOMIC-NEXT: .LBB2_4: # in Loop: Header=BB2_1 Depth=1 -; XTENSA-ATOMIC-NEXT: and a14, a14, a10 -; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB2_1 -; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB2_2 +; XTENSA-ATOMIC-NEXT: .LBB2_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB2_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB2_4 +; XTENSA-ATOMIC-NEXT: .LBB2_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a15, a10 +; XTENSA-ATOMIC-NEXT: or a14, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a11, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB2_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB2_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB2_1 +; XTENSA-ATOMIC-NEXT: .LBB2_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: sext a2, a8, 7 +; XTENSA-ATOMIC-NEXT: srl a2, a14 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i8 %b release - ret i8 %1 + %res = atomicrmw xchg ptr %a, i8 %b release + ret i8 %res } define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { @@ -190,48 +187,47 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 ; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a11, -1 ; XTENSA-ATOMIC-NEXT: sll a10, a10 -; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 -; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: and a14, a13, a10 -; XTENSA-ATOMIC-NEXT: .LBB3_1: # =>This Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: # Child Loop BB3_2 Depth 2 -; XTENSA-ATOMIC-NEXT: or a13, a14, a14 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: .LBB3_2: # Parent Loop BB3_1 Depth=1 -; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 -; XTENSA-ATOMIC-NEXT: or a15, a7, a7 -; XTENSA-ATOMIC-NEXT: or a14, a12, a15 -; XTENSA-ATOMIC-NEXT: or a7, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB3_4 -; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB3_2 Depth=2 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB3_2 -; XTENSA-ATOMIC-NEXT: .LBB3_4: # in Loop: Header=BB3_1 Depth=1 -; XTENSA-ATOMIC-NEXT: and a14, a14, a10 -; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB3_1 -; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB3_2 +; XTENSA-ATOMIC-NEXT: .LBB3_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB3_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB3_4 +; XTENSA-ATOMIC-NEXT: .LBB3_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a15, a10 +; XTENSA-ATOMIC-NEXT: or a14, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a11, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB3_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB3_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB3_1 +; XTENSA-ATOMIC-NEXT: .LBB3_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: sext a2, a8, 7 +; XTENSA-ATOMIC-NEXT: srl a2, a14 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i8 %b acq_rel - ret i8 %1 + %res = atomicrmw xchg ptr %a, i8 %b acq_rel + ret i8 %res } define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { @@ -249,48 +245,47 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 ; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a11, -1 ; XTENSA-ATOMIC-NEXT: sll a10, a10 -; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 -; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: and a14, a13, a10 -; XTENSA-ATOMIC-NEXT: .LBB4_1: # =>This Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: # Child Loop BB4_2 Depth 2 -; XTENSA-ATOMIC-NEXT: or a13, a14, a14 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: .LBB4_2: # Parent Loop BB4_1 Depth=1 -; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 -; XTENSA-ATOMIC-NEXT: or a15, a7, a7 -; XTENSA-ATOMIC-NEXT: or a14, a12, a15 -; XTENSA-ATOMIC-NEXT: or a7, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB4_4 -; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB4_2 Depth=2 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB4_2 -; XTENSA-ATOMIC-NEXT: .LBB4_4: # in Loop: Header=BB4_1 Depth=1 -; XTENSA-ATOMIC-NEXT: and a14, a14, a10 -; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB4_1 -; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB4_2 +; XTENSA-ATOMIC-NEXT: .LBB4_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB4_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB4_4 +; XTENSA-ATOMIC-NEXT: .LBB4_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a15, a10 +; XTENSA-ATOMIC-NEXT: or a14, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a11, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB4_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB4_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB4_1 +; XTENSA-ATOMIC-NEXT: .LBB4_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: sext a2, a8, 7 +; XTENSA-ATOMIC-NEXT: srl a2, a14 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i8 %b seq_cst - ret i8 %1 + %res = atomicrmw xchg ptr %a, i8 %b seq_cst + ret i8 %res } define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { @@ -308,35 +303,47 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB5_2 +; XTENSA-ATOMIC-NEXT: .LBB5_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB5_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB5_4 +; XTENSA-ATOMIC-NEXT: .LBB5_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: add a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB5_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB5_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB5_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB5_1 +; XTENSA-ATOMIC-NEXT: .LBB5_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i8 %b monotonic - ret i8 %1 + %res = atomicrmw add ptr %a, i8 %b monotonic + ret i8 %res } define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { @@ -354,36 +361,48 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB6_2 +; XTENSA-ATOMIC-NEXT: .LBB6_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB6_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB6_4 +; XTENSA-ATOMIC-NEXT: .LBB6_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: add a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB6_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB6_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB6_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB6_1 +; XTENSA-ATOMIC-NEXT: .LBB6_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i8 %b acquire - ret i8 %1 + %res = atomicrmw add ptr %a, i8 %b acquire + ret i8 %res } define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { @@ -401,36 +420,48 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB7_2 +; XTENSA-ATOMIC-NEXT: .LBB7_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB7_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB7_4 +; XTENSA-ATOMIC-NEXT: .LBB7_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: add a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB7_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB7_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB7_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB7_1 +; XTENSA-ATOMIC-NEXT: .LBB7_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i8 %b release - ret i8 %1 + %res = atomicrmw add ptr %a, i8 %b release + ret i8 %res } define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { @@ -448,37 +479,49 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB8_2 +; XTENSA-ATOMIC-NEXT: .LBB8_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB8_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB8_4 +; XTENSA-ATOMIC-NEXT: .LBB8_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: add a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB8_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB8_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB8_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB8_1 +; XTENSA-ATOMIC-NEXT: .LBB8_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i8 %b acq_rel - ret i8 %1 + %res = atomicrmw add ptr %a, i8 %b acq_rel + ret i8 %res } define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { @@ -496,37 +539,49 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB9_2 +; XTENSA-ATOMIC-NEXT: .LBB9_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB9_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB9_4 +; XTENSA-ATOMIC-NEXT: .LBB9_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: add a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB9_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB9_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB9_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB9_1 +; XTENSA-ATOMIC-NEXT: .LBB9_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i8 %b seq_cst - ret i8 %1 + %res = atomicrmw add ptr %a, i8 %b seq_cst + ret i8 %res } define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { @@ -544,35 +599,47 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB10_2 +; XTENSA-ATOMIC-NEXT: .LBB10_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB10_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB10_4 +; XTENSA-ATOMIC-NEXT: .LBB10_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB10_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB10_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB10_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB10_1 +; XTENSA-ATOMIC-NEXT: .LBB10_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i8 %b monotonic - ret i8 %1 + %res = atomicrmw sub ptr %a, i8 %b monotonic + ret i8 %res } define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { @@ -590,36 +657,48 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB11_2 +; XTENSA-ATOMIC-NEXT: .LBB11_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB11_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB11_4 +; XTENSA-ATOMIC-NEXT: .LBB11_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB11_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB11_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB11_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB11_1 +; XTENSA-ATOMIC-NEXT: .LBB11_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i8 %b acquire - ret i8 %1 + %res = atomicrmw sub ptr %a, i8 %b acquire + ret i8 %res } define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { @@ -637,36 +716,48 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB12_2 +; XTENSA-ATOMIC-NEXT: .LBB12_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB12_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB12_4 +; XTENSA-ATOMIC-NEXT: .LBB12_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB12_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB12_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB12_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB12_1 +; XTENSA-ATOMIC-NEXT: .LBB12_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i8 %b release - ret i8 %1 + %res = atomicrmw sub ptr %a, i8 %b release + ret i8 %res } define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { @@ -684,37 +775,49 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB13_2 +; XTENSA-ATOMIC-NEXT: .LBB13_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB13_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB13_4 +; XTENSA-ATOMIC-NEXT: .LBB13_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB13_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB13_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB13_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB13_1 +; XTENSA-ATOMIC-NEXT: .LBB13_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i8 %b acq_rel - ret i8 %1 + %res = atomicrmw sub ptr %a, i8 %b acq_rel + ret i8 %res } define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { @@ -732,37 +835,49 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB14_2 +; XTENSA-ATOMIC-NEXT: .LBB14_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB14_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB14_4 +; XTENSA-ATOMIC-NEXT: .LBB14_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB14_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB14_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB14_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB14_1 +; XTENSA-ATOMIC-NEXT: .LBB14_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i8 %b seq_cst - ret i8 %1 + %res = atomicrmw sub ptr %a, i8 %b seq_cst + ret i8 %res } define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { @@ -780,35 +895,45 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: and a10, a3, a9 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a11 +; XTENSA-ATOMIC-NEXT: or a9, a10, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: and a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB15_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB15_2 +; XTENSA-ATOMIC-NEXT: .LBB15_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB15_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB15_4 +; XTENSA-ATOMIC-NEXT: .LBB15_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB15_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB15_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB15_1 +; XTENSA-ATOMIC-NEXT: .LBB15_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i8 %b monotonic - ret i8 %1 + %res = atomicrmw and ptr %a, i8 %b monotonic + ret i8 %res } define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { @@ -826,36 +951,46 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: and a10, a3, a9 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a11 +; XTENSA-ATOMIC-NEXT: or a9, a10, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: and a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB16_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB16_2 +; XTENSA-ATOMIC-NEXT: .LBB16_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB16_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB16_4 +; XTENSA-ATOMIC-NEXT: .LBB16_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB16_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB16_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB16_1 +; XTENSA-ATOMIC-NEXT: .LBB16_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i8 %b acquire - ret i8 %1 + %res = atomicrmw and ptr %a, i8 %b acquire + ret i8 %res } define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { @@ -873,36 +1008,46 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: and a10, a3, a9 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a11 +; XTENSA-ATOMIC-NEXT: or a9, a10, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: and a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB17_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB17_2 +; XTENSA-ATOMIC-NEXT: .LBB17_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB17_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB17_4 +; XTENSA-ATOMIC-NEXT: .LBB17_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB17_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB17_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB17_1 +; XTENSA-ATOMIC-NEXT: .LBB17_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i8 %b release - ret i8 %1 + %res = atomicrmw and ptr %a, i8 %b release + ret i8 %res } define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { @@ -920,37 +1065,47 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: and a10, a3, a9 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a11 +; XTENSA-ATOMIC-NEXT: or a9, a10, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: and a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB18_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB18_2 +; XTENSA-ATOMIC-NEXT: .LBB18_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB18_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB18_4 +; XTENSA-ATOMIC-NEXT: .LBB18_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB18_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB18_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB18_1 +; XTENSA-ATOMIC-NEXT: .LBB18_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i8 %b acq_rel - ret i8 %1 + %res = atomicrmw and ptr %a, i8 %b acq_rel + ret i8 %res } define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { @@ -968,37 +1123,47 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: and a10, a3, a9 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a11 +; XTENSA-ATOMIC-NEXT: or a9, a10, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: and a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB19_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB19_2 +; XTENSA-ATOMIC-NEXT: .LBB19_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB19_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB19_4 +; XTENSA-ATOMIC-NEXT: .LBB19_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB19_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB19_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB19_1 +; XTENSA-ATOMIC-NEXT: .LBB19_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i8 %b seq_cst - ret i8 %1 + %res = atomicrmw and ptr %a, i8 %b seq_cst + ret i8 %res } define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { @@ -1016,33 +1181,48 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a14, a13, a13 -; XTENSA-ATOMIC-NEXT: and a13, a14, a11 -; XTENSA-ATOMIC-NEXT: and a13, a13, a12 -; XTENSA-ATOMIC-NEXT: and a13, a13, a11 -; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 -; XTENSA-ATOMIC-NEXT: or a15, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a13, a15 -; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB20_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a13 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a12, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: l32i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: movi a15, 1 +; XTENSA-ATOMIC-NEXT: j .LBB20_2 +; XTENSA-ATOMIC-NEXT: .LBB20_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB20_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a6, a6 +; XTENSA-ATOMIC-NEXT: beqi a5, 1, .LBB20_4 +; XTENSA-ATOMIC-NEXT: .LBB20_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a6, a7, a12 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: xor a5, a5, a11 +; XTENSA-ATOMIC-NEXT: and a5, a5, a10 +; XTENSA-ATOMIC-NEXT: or a6, a6, a5 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a6, a13, 0 +; XTENSA-ATOMIC-NEXT: or a5, a15, a15 +; XTENSA-ATOMIC-NEXT: beq a6, a7, .LBB20_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB20_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a5, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB20_1 +; XTENSA-ATOMIC-NEXT: .LBB20_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a6 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw nand ptr %a, i8 %b monotonic - ret i8 %1 + %res = atomicrmw nand ptr %a, i8 %b monotonic + ret i8 %res } define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { @@ -1060,34 +1240,49 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a14, a13, a13 -; XTENSA-ATOMIC-NEXT: and a13, a14, a11 -; XTENSA-ATOMIC-NEXT: and a13, a13, a12 -; XTENSA-ATOMIC-NEXT: and a13, a13, a11 -; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 -; XTENSA-ATOMIC-NEXT: or a15, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a13, a15 -; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB21_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a13 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a12, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: l32i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: movi a15, 1 +; XTENSA-ATOMIC-NEXT: j .LBB21_2 +; XTENSA-ATOMIC-NEXT: .LBB21_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB21_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a6, a6 +; XTENSA-ATOMIC-NEXT: beqi a5, 1, .LBB21_4 +; XTENSA-ATOMIC-NEXT: .LBB21_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a6, a7, a12 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: xor a5, a5, a11 +; XTENSA-ATOMIC-NEXT: and a5, a5, a10 +; XTENSA-ATOMIC-NEXT: or a6, a6, a5 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a6, a13, 0 +; XTENSA-ATOMIC-NEXT: or a5, a15, a15 +; XTENSA-ATOMIC-NEXT: beq a6, a7, .LBB21_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB21_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a5, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB21_1 +; XTENSA-ATOMIC-NEXT: .LBB21_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a6 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw nand ptr %a, i8 %b acquire - ret i8 %1 + %res = atomicrmw nand ptr %a, i8 %b acquire + ret i8 %res } define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { @@ -1105,34 +1300,49 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a14, a13, a13 -; XTENSA-ATOMIC-NEXT: and a13, a14, a11 -; XTENSA-ATOMIC-NEXT: and a13, a13, a12 -; XTENSA-ATOMIC-NEXT: and a13, a13, a11 -; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 -; XTENSA-ATOMIC-NEXT: or a15, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a13, a15 -; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB22_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a13 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a12, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: movi a15, 1 +; XTENSA-ATOMIC-NEXT: j .LBB22_2 +; XTENSA-ATOMIC-NEXT: .LBB22_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB22_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a6, a6 +; XTENSA-ATOMIC-NEXT: beqi a5, 1, .LBB22_4 +; XTENSA-ATOMIC-NEXT: .LBB22_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a6, a7, a12 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: xor a5, a5, a11 +; XTENSA-ATOMIC-NEXT: and a5, a5, a10 +; XTENSA-ATOMIC-NEXT: or a6, a6, a5 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a6, a13, 0 +; XTENSA-ATOMIC-NEXT: or a5, a15, a15 +; XTENSA-ATOMIC-NEXT: beq a6, a7, .LBB22_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB22_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a5, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB22_1 +; XTENSA-ATOMIC-NEXT: .LBB22_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a6 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw nand ptr %a, i8 %b release - ret i8 %1 + %res = atomicrmw nand ptr %a, i8 %b release + ret i8 %res } define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { @@ -1150,35 +1360,50 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a14, a13, a13 -; XTENSA-ATOMIC-NEXT: and a13, a14, a11 -; XTENSA-ATOMIC-NEXT: and a13, a13, a12 -; XTENSA-ATOMIC-NEXT: and a13, a13, a11 -; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 -; XTENSA-ATOMIC-NEXT: or a15, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a13, a15 -; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB23_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a13 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a12, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: movi a15, 1 +; XTENSA-ATOMIC-NEXT: j .LBB23_2 +; XTENSA-ATOMIC-NEXT: .LBB23_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB23_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a6, a6 +; XTENSA-ATOMIC-NEXT: beqi a5, 1, .LBB23_4 +; XTENSA-ATOMIC-NEXT: .LBB23_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a6, a7, a12 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: xor a5, a5, a11 +; XTENSA-ATOMIC-NEXT: and a5, a5, a10 +; XTENSA-ATOMIC-NEXT: or a6, a6, a5 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a6, a13, 0 +; XTENSA-ATOMIC-NEXT: or a5, a15, a15 +; XTENSA-ATOMIC-NEXT: beq a6, a7, .LBB23_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB23_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a5, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB23_1 +; XTENSA-ATOMIC-NEXT: .LBB23_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a6 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw nand ptr %a, i8 %b acq_rel - ret i8 %1 + %res = atomicrmw nand ptr %a, i8 %b acq_rel + ret i8 %res } define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { @@ -1196,35 +1421,50 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a14, a13, a13 -; XTENSA-ATOMIC-NEXT: and a13, a14, a11 -; XTENSA-ATOMIC-NEXT: and a13, a13, a12 -; XTENSA-ATOMIC-NEXT: and a13, a13, a11 -; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 -; XTENSA-ATOMIC-NEXT: or a15, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a13, a15 -; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB24_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a13 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a10, 255 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a12, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: movi a15, 1 +; XTENSA-ATOMIC-NEXT: j .LBB24_2 +; XTENSA-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a6, a6 +; XTENSA-ATOMIC-NEXT: beqi a5, 1, .LBB24_4 +; XTENSA-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a6, a7, a12 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: xor a5, a5, a11 +; XTENSA-ATOMIC-NEXT: and a5, a5, a10 +; XTENSA-ATOMIC-NEXT: or a6, a6, a5 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a6, a13, 0 +; XTENSA-ATOMIC-NEXT: or a5, a15, a15 +; XTENSA-ATOMIC-NEXT: beq a6, a7, .LBB24_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a5, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB24_1 +; XTENSA-ATOMIC-NEXT: .LBB24_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a6 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw nand ptr %a, i8 %b seq_cst - ret i8 %1 + %res = atomicrmw nand ptr %a, i8 %b seq_cst + ret i8 %res } define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { @@ -1242,35 +1482,40 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: or a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB25_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB25_2 +; XTENSA-ATOMIC-NEXT: .LBB25_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB25_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB25_4 +; XTENSA-ATOMIC-NEXT: .LBB25_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB25_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB25_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB25_1 +; XTENSA-ATOMIC-NEXT: .LBB25_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i8 %b monotonic - ret i8 %1 + %res = atomicrmw or ptr %a, i8 %b monotonic + ret i8 %res } define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { @@ -1288,36 +1533,41 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: or a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB26_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB26_2 +; XTENSA-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB26_4 +; XTENSA-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB26_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB26_1 +; XTENSA-ATOMIC-NEXT: .LBB26_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i8 %b acquire - ret i8 %1 + %res = atomicrmw or ptr %a, i8 %b acquire + ret i8 %res } define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { @@ -1335,36 +1585,41 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: or a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB27_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB27_2 +; XTENSA-ATOMIC-NEXT: .LBB27_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB27_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB27_4 +; XTENSA-ATOMIC-NEXT: .LBB27_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB27_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB27_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB27_1 +; XTENSA-ATOMIC-NEXT: .LBB27_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i8 %b release - ret i8 %1 + %res = atomicrmw or ptr %a, i8 %b release + ret i8 %res } define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { @@ -1382,37 +1637,42 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: or a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB28_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB28_2 +; XTENSA-ATOMIC-NEXT: .LBB28_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB28_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB28_4 +; XTENSA-ATOMIC-NEXT: .LBB28_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB28_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB28_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB28_1 +; XTENSA-ATOMIC-NEXT: .LBB28_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i8 %b acq_rel - ret i8 %1 + %res = atomicrmw or ptr %a, i8 %b acq_rel + ret i8 %res } define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { @@ -1430,37 +1690,42 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: or a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB29_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB29_2 +; XTENSA-ATOMIC-NEXT: .LBB29_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB29_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB29_4 +; XTENSA-ATOMIC-NEXT: .LBB29_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB29_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB29_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB29_1 +; XTENSA-ATOMIC-NEXT: .LBB29_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i8 %b seq_cst - ret i8 %1 + %res = atomicrmw or ptr %a, i8 %b seq_cst + ret i8 %res } define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { @@ -1478,35 +1743,40 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB30_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB30_2 +; XTENSA-ATOMIC-NEXT: .LBB30_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB30_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB30_4 +; XTENSA-ATOMIC-NEXT: .LBB30_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB30_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB30_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB30_1 +; XTENSA-ATOMIC-NEXT: .LBB30_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i8 %b monotonic - ret i8 %1 + %res = atomicrmw xor ptr %a, i8 %b monotonic + ret i8 %res } define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { @@ -1524,36 +1794,41 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB31_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB31_2 +; XTENSA-ATOMIC-NEXT: .LBB31_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB31_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB31_4 +; XTENSA-ATOMIC-NEXT: .LBB31_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB31_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB31_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB31_1 +; XTENSA-ATOMIC-NEXT: .LBB31_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i8 %b acquire - ret i8 %1 + %res = atomicrmw xor ptr %a, i8 %b acquire + ret i8 %res } define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { @@ -1571,36 +1846,41 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB32_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB32_2 +; XTENSA-ATOMIC-NEXT: .LBB32_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB32_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB32_4 +; XTENSA-ATOMIC-NEXT: .LBB32_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB32_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB32_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB32_1 +; XTENSA-ATOMIC-NEXT: .LBB32_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i8 %b release - ret i8 %1 + %res = atomicrmw xor ptr %a, i8 %b release + ret i8 %res } define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { @@ -1618,37 +1898,42 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB33_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB33_2 +; XTENSA-ATOMIC-NEXT: .LBB33_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB33_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB33_4 +; XTENSA-ATOMIC-NEXT: .LBB33_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB33_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB33_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB33_1 +; XTENSA-ATOMIC-NEXT: .LBB33_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i8 %b acq_rel - ret i8 %1 + %res = atomicrmw xor ptr %a, i8 %b acq_rel + ret i8 %res } define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { @@ -1666,1180 +1951,1894 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 ; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 -; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB34_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB34_2 +; XTENSA-ATOMIC-NEXT: .LBB34_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB34_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB34_4 +; XTENSA-ATOMIC-NEXT: .LBB34_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB34_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB34_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB34_1 +; XTENSA-ATOMIC-NEXT: .LBB34_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i8 %b seq_cst - ret i8 %1 + %res = atomicrmw xor ptr %a, i8 %b seq_cst + ret i8 %res } -;define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw max ptr %a, i8 %b monotonic -; ret i8 %1 -;} - -;define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw max ptr %a, i8 %b acquire -; ret i8 %1 -;} - -;define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw max ptr %a, i8 %b release -; ret i8 %1 -;} - -;define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw max ptr %a, i8 %b acq_rel -; ret i8 %1 -;} - -;define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw max ptr %a, i8 %b seq_cst -; ret i8 %1 -;} - -;define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw min ptr %a, i8 %b monotonic -; ret i8 %1 -;} - -;define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw min ptr %a, i8 %b acquire -; ret i8 %1 -;} -; -;define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw min ptr %a, i8 %b release -; ret i8 %1 -;} -; -;define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw min ptr %a, i8 %b acq_rel -; ret i8 %1 -;} -; -;define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw min ptr %a, i8 %b seq_cst -; ret i8 %1 -;} - -;define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i8 %b monotonic -; ret i8 %1 -;} -; -;define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i8 %b acquire -; ret i8 %1 -;} -; -;define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i8 %b release -; ret i8 %1 -;} -; -;define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i8 %b acq_rel -; ret i8 %1 -;} -; -;define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i8 %b seq_cst -; ret i8 %1 -;} - -;define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i8 %b monotonic -; ret i8 %1 -;} -; -;define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i8 %b acquire -; ret i8 %1 -;} -; -;define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i8 %b release -; ret i8 %1 -;} -; -;define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i8 %b acq_rel -; ret i8 %1 -;} -; -;define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i8 %b seq_cst -; ret i8 %1 -;} - -define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xchg_i16_monotonic: +define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i8_monotonic: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 0 -; XTENSA-NEXT: l32r a8, .LCPI35_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l8ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 24 +; XTENSA-NEXT: srai a5, a8, 24 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a4, .LCPI35_0 +; XTENSA-NEXT: j .LBB35_2 +; XTENSA-NEXT: .LBB35_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB35_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l8ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB35_4 +; XTENSA-NEXT: .LBB35_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 24 +; XTENSA-NEXT: srai a8, a8, 24 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bge a5, a8, .LBB35_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB35_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB35_1 +; XTENSA-NEXT: .LBB35_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_monotonic: +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i8_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 ; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 ; XTENSA-ATOMIC-NEXT: movi a11, -1 -; XTENSA-ATOMIC-NEXT: sll a10, a10 -; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 -; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: and a14, a13, a10 -; XTENSA-ATOMIC-NEXT: .LBB35_1: # =>This Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: # Child Loop BB35_2 Depth 2 -; XTENSA-ATOMIC-NEXT: or a13, a14, a14 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: .LBB35_2: # Parent Loop BB35_1 Depth=1 -; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: slli a12, a3, 24 +; XTENSA-ATOMIC-NEXT: srai a12, a12, 24 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB35_2 +; XTENSA-ATOMIC-NEXT: .LBB35_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB35_2 Depth=1 ; XTENSA-ATOMIC-NEXT: or a15, a7, a7 -; XTENSA-ATOMIC-NEXT: or a14, a12, a15 -; XTENSA-ATOMIC-NEXT: or a7, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB35_4 -; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB35_2 Depth=2 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB35_2 -; XTENSA-ATOMIC-NEXT: .LBB35_4: # in Loop: Header=BB35_1 Depth=1 -; XTENSA-ATOMIC-NEXT: and a14, a14, a10 -; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB35_1 -; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB35_6 +; XTENSA-ATOMIC-NEXT: .LBB35_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: slli a6, a7, 24 +; XTENSA-ATOMIC-NEXT: srai a5, a6, 24 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a12, a5, .LBB35_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB35_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB35_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB35_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB35_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB35_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB35_1 +; XTENSA-ATOMIC-NEXT: .LBB35_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: sext a2, a8, 15 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i16 %b monotonic - ret i16 %1 + %res = atomicrmw max ptr %a, i8 %b monotonic + ret i8 %res } -define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xchg_i16_acquire: +define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i8_acquire: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 2 -; XTENSA-NEXT: l32r a8, .LCPI36_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l8ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 24 +; XTENSA-NEXT: srai a5, a8, 24 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a4, .LCPI36_0 +; XTENSA-NEXT: j .LBB36_2 +; XTENSA-NEXT: .LBB36_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB36_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l8ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB36_4 +; XTENSA-NEXT: .LBB36_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 24 +; XTENSA-NEXT: srai a8, a8, 24 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bge a5, a8, .LBB36_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB36_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB36_1 +; XTENSA-NEXT: .LBB36_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_acquire: +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i8_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 ; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 ; XTENSA-ATOMIC-NEXT: movi a11, -1 -; XTENSA-ATOMIC-NEXT: sll a10, a10 -; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 -; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: and a14, a13, a10 -; XTENSA-ATOMIC-NEXT: .LBB36_1: # =>This Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: # Child Loop BB36_2 Depth 2 -; XTENSA-ATOMIC-NEXT: or a13, a14, a14 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: .LBB36_2: # Parent Loop BB36_1 Depth=1 -; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: slli a12, a3, 24 +; XTENSA-ATOMIC-NEXT: srai a12, a12, 24 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB36_2 +; XTENSA-ATOMIC-NEXT: .LBB36_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB36_2 Depth=1 ; XTENSA-ATOMIC-NEXT: or a15, a7, a7 -; XTENSA-ATOMIC-NEXT: or a14, a12, a15 -; XTENSA-ATOMIC-NEXT: or a7, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB36_4 -; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB36_2 Depth=2 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB36_2 -; XTENSA-ATOMIC-NEXT: .LBB36_4: # in Loop: Header=BB36_1 Depth=1 -; XTENSA-ATOMIC-NEXT: and a14, a14, a10 -; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB36_1 -; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB36_6 +; XTENSA-ATOMIC-NEXT: .LBB36_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: slli a6, a7, 24 +; XTENSA-ATOMIC-NEXT: srai a5, a6, 24 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a12, a5, .LBB36_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB36_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB36_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB36_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB36_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB36_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB36_1 +; XTENSA-ATOMIC-NEXT: .LBB36_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: sext a2, a8, 15 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i16 %b acquire - ret i16 %1 + %res = atomicrmw max ptr %a, i8 %b acquire + ret i8 %res } -define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xchg_i16_release: +define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i8_release: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 3 -; XTENSA-NEXT: l32r a8, .LCPI37_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a9, a2, a2 +; XTENSA-NEXT: l8ui a2, a9, 0 +; XTENSA-NEXT: s32i a3, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: slli a8, a3, 24 +; XTENSA-NEXT: or a3, a9, a9 +; XTENSA-NEXT: srai a4, a8, 24 +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a5, .LCPI37_0 +; XTENSA-NEXT: j .LBB37_2 +; XTENSA-NEXT: .LBB37_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB37_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: or a10, a3, a3 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l8ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB37_4 +; XTENSA-NEXT: .LBB37_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 4 +; XTENSA-NEXT: slli a8, a2, 24 +; XTENSA-NEXT: srai a8, a8, 24 +; XTENSA-NEXT: l32i a12, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: bge a4, a8, .LBB37_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB37_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB37_1 +; XTENSA-NEXT: .LBB37_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_release: +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i8_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 ; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 ; XTENSA-ATOMIC-NEXT: movi a11, -1 -; XTENSA-ATOMIC-NEXT: sll a10, a10 -; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 -; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: and a14, a13, a10 -; XTENSA-ATOMIC-NEXT: .LBB37_1: # =>This Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: # Child Loop BB37_2 Depth 2 -; XTENSA-ATOMIC-NEXT: or a13, a14, a14 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: .LBB37_2: # Parent Loop BB37_1 Depth=1 -; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: slli a12, a3, 24 +; XTENSA-ATOMIC-NEXT: srai a12, a12, 24 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB37_2 +; XTENSA-ATOMIC-NEXT: .LBB37_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB37_2 Depth=1 ; XTENSA-ATOMIC-NEXT: or a15, a7, a7 -; XTENSA-ATOMIC-NEXT: or a14, a12, a15 -; XTENSA-ATOMIC-NEXT: or a7, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB37_4 -; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB37_2 Depth=2 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB37_2 -; XTENSA-ATOMIC-NEXT: .LBB37_4: # in Loop: Header=BB37_1 Depth=1 -; XTENSA-ATOMIC-NEXT: and a14, a14, a10 -; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB37_1 -; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB37_6 +; XTENSA-ATOMIC-NEXT: .LBB37_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: slli a6, a7, 24 +; XTENSA-ATOMIC-NEXT: srai a5, a6, 24 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a12, a5, .LBB37_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB37_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB37_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB37_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB37_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB37_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB37_1 +; XTENSA-ATOMIC-NEXT: .LBB37_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: sext a2, a8, 15 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i16 %b release - ret i16 %1 + %res = atomicrmw max ptr %a, i8 %b release + ret i8 %res } -define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xchg_i16_acq_rel: +define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i8_acq_rel: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 4 -; XTENSA-NEXT: l32r a8, .LCPI38_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a9, a2, a2 +; XTENSA-NEXT: l8ui a2, a9, 0 +; XTENSA-NEXT: s32i a3, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: slli a8, a3, 24 +; XTENSA-NEXT: or a3, a9, a9 +; XTENSA-NEXT: srai a4, a8, 24 +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a5, .LCPI38_0 +; XTENSA-NEXT: j .LBB38_2 +; XTENSA-NEXT: .LBB38_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB38_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: or a10, a3, a3 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l8ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB38_4 +; XTENSA-NEXT: .LBB38_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 4 +; XTENSA-NEXT: slli a8, a2, 24 +; XTENSA-NEXT: srai a8, a8, 24 +; XTENSA-NEXT: l32i a12, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: bge a4, a8, .LBB38_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB38_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB38_1 +; XTENSA-NEXT: .LBB38_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_acq_rel: +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i8_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 ; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 ; XTENSA-ATOMIC-NEXT: movi a11, -1 -; XTENSA-ATOMIC-NEXT: sll a10, a10 -; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 -; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: and a14, a13, a10 -; XTENSA-ATOMIC-NEXT: .LBB38_1: # =>This Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: # Child Loop BB38_2 Depth 2 -; XTENSA-ATOMIC-NEXT: or a13, a14, a14 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: .LBB38_2: # Parent Loop BB38_1 Depth=1 -; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: slli a12, a3, 24 +; XTENSA-ATOMIC-NEXT: srai a12, a12, 24 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB38_2 +; XTENSA-ATOMIC-NEXT: .LBB38_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB38_2 Depth=1 ; XTENSA-ATOMIC-NEXT: or a15, a7, a7 -; XTENSA-ATOMIC-NEXT: or a14, a12, a15 -; XTENSA-ATOMIC-NEXT: or a7, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB38_4 -; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB38_2 Depth=2 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB38_2 -; XTENSA-ATOMIC-NEXT: .LBB38_4: # in Loop: Header=BB38_1 Depth=1 -; XTENSA-ATOMIC-NEXT: and a14, a14, a10 -; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB38_1 -; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB38_6 +; XTENSA-ATOMIC-NEXT: .LBB38_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: slli a6, a7, 24 +; XTENSA-ATOMIC-NEXT: srai a5, a6, 24 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a12, a5, .LBB38_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB38_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB38_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB38_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB38_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB38_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB38_1 +; XTENSA-ATOMIC-NEXT: .LBB38_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: sext a2, a8, 15 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i16 %b acq_rel - ret i16 %1 + %res = atomicrmw max ptr %a, i8 %b acq_rel + ret i8 %res } -define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xchg_i16_seq_cst: +define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i8_seq_cst: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 5 -; XTENSA-NEXT: l32r a8, .LCPI39_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l8ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 24 +; XTENSA-NEXT: srai a5, a8, 24 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a4, .LCPI39_0 +; XTENSA-NEXT: j .LBB39_2 +; XTENSA-NEXT: .LBB39_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB39_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l8ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB39_4 +; XTENSA-NEXT: .LBB39_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 24 +; XTENSA-NEXT: srai a8, a8, 24 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bge a5, a8, .LBB39_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB39_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB39_1 +; XTENSA-NEXT: .LBB39_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_seq_cst: +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i8_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 ; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 ; XTENSA-ATOMIC-NEXT: movi a11, -1 -; XTENSA-ATOMIC-NEXT: sll a10, a10 -; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 -; XTENSA-ATOMIC-NEXT: l32i a12, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: and a14, a13, a10 -; XTENSA-ATOMIC-NEXT: .LBB39_1: # =>This Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: # Child Loop BB39_2 Depth 2 -; XTENSA-ATOMIC-NEXT: or a13, a14, a14 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: .LBB39_2: # Parent Loop BB39_1 Depth=1 -; XTENSA-ATOMIC-NEXT: # => This Inner Loop Header: Depth=2 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: slli a12, a3, 24 +; XTENSA-ATOMIC-NEXT: srai a12, a12, 24 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB39_2 +; XTENSA-ATOMIC-NEXT: .LBB39_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB39_2 Depth=1 ; XTENSA-ATOMIC-NEXT: or a15, a7, a7 -; XTENSA-ATOMIC-NEXT: or a14, a12, a15 -; XTENSA-ATOMIC-NEXT: or a7, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: beq a7, a14, .LBB39_4 -; XTENSA-ATOMIC-NEXT: # %bb.3: # in Loop: Header=BB39_2 Depth=2 -; XTENSA-ATOMIC-NEXT: and a7, a14, a11 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB39_2 -; XTENSA-ATOMIC-NEXT: .LBB39_4: # in Loop: Header=BB39_1 Depth=1 -; XTENSA-ATOMIC-NEXT: and a14, a14, a10 -; XTENSA-ATOMIC-NEXT: bne a14, a13, .LBB39_1 -; XTENSA-ATOMIC-NEXT: # %bb.5: +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB39_6 +; XTENSA-ATOMIC-NEXT: .LBB39_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: sext a2, a8, 15 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: slli a6, a7, 24 +; XTENSA-ATOMIC-NEXT: srai a5, a6, 24 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a12, a5, .LBB39_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB39_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB39_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB39_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB39_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB39_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB39_1 +; XTENSA-ATOMIC-NEXT: .LBB39_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i16 %b seq_cst - ret i16 %1 + %res = atomicrmw max ptr %a, i8 %b seq_cst + ret i8 %res } -define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_add_i16_monotonic: +define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i8_monotonic: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 0 -; XTENSA-NEXT: l32r a8, .LCPI40_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l8ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 24 +; XTENSA-NEXT: srai a5, a8, 24 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a4, .LCPI40_0 +; XTENSA-NEXT: j .LBB40_2 +; XTENSA-NEXT: .LBB40_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB40_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l8ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB40_4 +; XTENSA-NEXT: .LBB40_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 24 +; XTENSA-NEXT: srai a8, a8, 24 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: blt a5, a8, .LBB40_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB40_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB40_1 +; XTENSA-NEXT: .LBB40_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_monotonic: +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i8_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: slli a12, a3, 24 +; XTENSA-ATOMIC-NEXT: srai a12, a12, 24 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB40_2 +; XTENSA-ATOMIC-NEXT: .LBB40_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB40_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB40_6 +; XTENSA-ATOMIC-NEXT: .LBB40_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: slli a6, a7, 24 +; XTENSA-ATOMIC-NEXT: srai a5, a6, 24 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a12, a5, .LBB40_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB40_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB40_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB40_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB40_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB40_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB40_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB40_1 +; XTENSA-ATOMIC-NEXT: .LBB40_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i16 %b monotonic - ret i16 %1 + %res = atomicrmw min ptr %a, i8 %b monotonic + ret i8 %res } -define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_add_i16_acquire: +define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i8_acquire: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 2 -; XTENSA-NEXT: l32r a8, .LCPI41_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l8ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 24 +; XTENSA-NEXT: srai a5, a8, 24 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a4, .LCPI41_0 +; XTENSA-NEXT: j .LBB41_2 +; XTENSA-NEXT: .LBB41_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB41_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l8ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB41_4 +; XTENSA-NEXT: .LBB41_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 24 +; XTENSA-NEXT: srai a8, a8, 24 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: blt a5, a8, .LBB41_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB41_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB41_1 +; XTENSA-NEXT: .LBB41_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_acquire: +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i8_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: slli a12, a3, 24 +; XTENSA-ATOMIC-NEXT: srai a12, a12, 24 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB41_2 +; XTENSA-ATOMIC-NEXT: .LBB41_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB41_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB41_6 +; XTENSA-ATOMIC-NEXT: .LBB41_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: slli a6, a7, 24 +; XTENSA-ATOMIC-NEXT: srai a5, a6, 24 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a12, a5, .LBB41_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB41_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB41_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB41_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB41_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB41_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB41_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB41_1 +; XTENSA-ATOMIC-NEXT: .LBB41_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i16 %b acquire - ret i16 %1 + %res = atomicrmw min ptr %a, i8 %b acquire + ret i8 %res } -define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_add_i16_release: +define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i8_release: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 3 -; XTENSA-NEXT: l32r a8, .LCPI42_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a9, a2, a2 +; XTENSA-NEXT: l8ui a2, a9, 0 +; XTENSA-NEXT: s32i a3, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: slli a8, a3, 24 +; XTENSA-NEXT: or a3, a9, a9 +; XTENSA-NEXT: srai a4, a8, 24 +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a5, .LCPI42_0 +; XTENSA-NEXT: j .LBB42_2 +; XTENSA-NEXT: .LBB42_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB42_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: or a10, a3, a3 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l8ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB42_4 +; XTENSA-NEXT: .LBB42_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 4 +; XTENSA-NEXT: slli a8, a2, 24 +; XTENSA-NEXT: srai a8, a8, 24 +; XTENSA-NEXT: l32i a12, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: blt a4, a8, .LBB42_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB42_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB42_1 +; XTENSA-NEXT: .LBB42_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_release: +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i8_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: slli a12, a3, 24 +; XTENSA-ATOMIC-NEXT: srai a12, a12, 24 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB42_2 +; XTENSA-ATOMIC-NEXT: .LBB42_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB42_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB42_6 +; XTENSA-ATOMIC-NEXT: .LBB42_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: slli a6, a7, 24 +; XTENSA-ATOMIC-NEXT: srai a5, a6, 24 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a12, a5, .LBB42_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB42_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB42_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB42_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB42_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB42_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB42_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB42_1 +; XTENSA-ATOMIC-NEXT: .LBB42_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i16 %b release - ret i16 %1 + %res = atomicrmw min ptr %a, i8 %b release + ret i8 %res } -define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_add_i16_acq_rel: +define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i8_acq_rel: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 4 -; XTENSA-NEXT: l32r a8, .LCPI43_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a9, a2, a2 +; XTENSA-NEXT: l8ui a2, a9, 0 +; XTENSA-NEXT: s32i a3, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: slli a8, a3, 24 +; XTENSA-NEXT: or a3, a9, a9 +; XTENSA-NEXT: srai a4, a8, 24 +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a5, .LCPI43_0 +; XTENSA-NEXT: j .LBB43_2 +; XTENSA-NEXT: .LBB43_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB43_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: or a10, a3, a3 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l8ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB43_4 +; XTENSA-NEXT: .LBB43_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 4 +; XTENSA-NEXT: slli a8, a2, 24 +; XTENSA-NEXT: srai a8, a8, 24 +; XTENSA-NEXT: l32i a12, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: blt a4, a8, .LBB43_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB43_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB43_1 +; XTENSA-NEXT: .LBB43_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_acq_rel: +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i8_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: slli a12, a3, 24 +; XTENSA-ATOMIC-NEXT: srai a12, a12, 24 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB43_2 +; XTENSA-ATOMIC-NEXT: .LBB43_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB43_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB43_6 +; XTENSA-ATOMIC-NEXT: .LBB43_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: slli a6, a7, 24 +; XTENSA-ATOMIC-NEXT: srai a5, a6, 24 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a12, a5, .LBB43_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB43_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB43_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB43_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB43_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB43_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB43_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB43_1 +; XTENSA-ATOMIC-NEXT: .LBB43_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i16 %b acq_rel - ret i16 %1 + %res = atomicrmw min ptr %a, i8 %b acq_rel + ret i8 %res } -define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_add_i16_seq_cst: +define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i8_seq_cst: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 5 -; XTENSA-NEXT: l32r a8, .LCPI44_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l8ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 24 +; XTENSA-NEXT: srai a5, a8, 24 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a4, .LCPI44_0 +; XTENSA-NEXT: j .LBB44_2 +; XTENSA-NEXT: .LBB44_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB44_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l8ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB44_4 +; XTENSA-NEXT: .LBB44_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 24 +; XTENSA-NEXT: srai a8, a8, 24 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: blt a5, a8, .LBB44_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB44_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB44_1 +; XTENSA-NEXT: .LBB44_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_seq_cst: +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i8_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: slli a12, a3, 24 +; XTENSA-ATOMIC-NEXT: srai a12, a12, 24 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB44_2 +; XTENSA-ATOMIC-NEXT: .LBB44_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB44_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB44_6 +; XTENSA-ATOMIC-NEXT: .LBB44_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: slli a6, a7, 24 +; XTENSA-ATOMIC-NEXT: srai a5, a6, 24 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a12, a5, .LBB44_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB44_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB44_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB44_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB44_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB44_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB44_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB44_1 +; XTENSA-ATOMIC-NEXT: .LBB44_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i16 %b seq_cst - ret i16 %1 + %res = atomicrmw min ptr %a, i8 %b seq_cst + ret i8 %res } -define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_sub_i16_monotonic: +define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i8_monotonic: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 0 -; XTENSA-NEXT: l32r a8, .LCPI45_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a8, a3, a3 +; XTENSA-NEXT: s32i a2, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: l8ui a2, a2, 0 +; XTENSA-NEXT: movi a5, 255 +; XTENSA-NEXT: and a4, a8, a5 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a6, .LCPI45_0 +; XTENSA-NEXT: j .LBB45_2 +; XTENSA-NEXT: .LBB45_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB45_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: l32i a10, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a6 +; XTENSA-NEXT: l8ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB45_4 +; XTENSA-NEXT: .LBB45_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 4 +; XTENSA-NEXT: and a8, a2, a5 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a4, a8, .LBB45_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB45_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB45_1 +; XTENSA-NEXT: .LBB45_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_monotonic: +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i8_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: and a12, a3, a9 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB45_2 +; XTENSA-ATOMIC-NEXT: .LBB45_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB45_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB45_6 +; XTENSA-ATOMIC-NEXT: .LBB45_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a12, a5, .LBB45_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB45_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB45_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB45_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB45_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB45_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB45_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB45_1 +; XTENSA-ATOMIC-NEXT: .LBB45_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i16 %b monotonic - ret i16 %1 + %res = atomicrmw umax ptr %a, i8 %b monotonic + ret i8 %res } -define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_sub_i16_acquire: +define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i8_acquire: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 2 -; XTENSA-NEXT: l32r a8, .LCPI46_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a8, a3, a3 +; XTENSA-NEXT: s32i a2, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: l8ui a2, a2, 0 +; XTENSA-NEXT: movi a5, 255 +; XTENSA-NEXT: and a4, a8, a5 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a6, .LCPI46_0 +; XTENSA-NEXT: j .LBB46_2 +; XTENSA-NEXT: .LBB46_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB46_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: l32i a10, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a6 +; XTENSA-NEXT: l8ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB46_4 +; XTENSA-NEXT: .LBB46_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 4 +; XTENSA-NEXT: and a8, a2, a5 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a4, a8, .LBB46_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB46_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB46_1 +; XTENSA-NEXT: .LBB46_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_acquire: +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i8_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: and a12, a3, a9 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB46_2 +; XTENSA-ATOMIC-NEXT: .LBB46_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB46_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB46_6 +; XTENSA-ATOMIC-NEXT: .LBB46_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a12, a5, .LBB46_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB46_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB46_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB46_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB46_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB46_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB46_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB46_1 +; XTENSA-ATOMIC-NEXT: .LBB46_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i16 %b acquire - ret i16 %1 + %res = atomicrmw umax ptr %a, i8 %b acquire + ret i8 %res } -define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_sub_i16_release: +define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i8_release: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 3 -; XTENSA-NEXT: l32r a8, .LCPI47_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: s32i a2, a1, 4 # 4-byte Folded Spill +; XTENSA-NEXT: l8ui a2, a2, 0 +; XTENSA-NEXT: movi a4, 255 +; XTENSA-NEXT: or a5, a3, a3 +; XTENSA-NEXT: and a8, a3, a4 +; XTENSA-NEXT: s32i a8, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a3, .LCPI47_0 +; XTENSA-NEXT: j .LBB47_2 +; XTENSA-NEXT: .LBB47_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB47_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 8 +; XTENSA-NEXT: l32i a10, a1, 4 # 4-byte Folded Reload +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a3 +; XTENSA-NEXT: l8ui a2, a1, 8 +; XTENSA-NEXT: bnez a10, .LBB47_4 +; XTENSA-NEXT: .LBB47_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 8 +; XTENSA-NEXT: and a8, a2, a4 +; XTENSA-NEXT: or a12, a5, a5 +; XTENSA-NEXT: l32i a9, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: bgeu a9, a8, .LBB47_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB47_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB47_1 +; XTENSA-NEXT: .LBB47_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_release: +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i8_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: and a12, a3, a9 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB47_2 +; XTENSA-ATOMIC-NEXT: .LBB47_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB47_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB47_6 +; XTENSA-ATOMIC-NEXT: .LBB47_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a12, a5, .LBB47_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB47_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB47_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB47_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB47_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB47_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB47_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB47_1 +; XTENSA-ATOMIC-NEXT: .LBB47_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i16 %b release - ret i16 %1 + %res = atomicrmw umax ptr %a, i8 %b release + ret i8 %res } -define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_sub_i16_acq_rel: +define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i8_acq_rel: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 4 -; XTENSA-NEXT: l32r a8, .LCPI48_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: s32i a2, a1, 4 # 4-byte Folded Spill +; XTENSA-NEXT: l8ui a2, a2, 0 +; XTENSA-NEXT: movi a4, 255 +; XTENSA-NEXT: or a5, a3, a3 +; XTENSA-NEXT: and a8, a3, a4 +; XTENSA-NEXT: s32i a8, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a3, .LCPI48_0 +; XTENSA-NEXT: j .LBB48_2 +; XTENSA-NEXT: .LBB48_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB48_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 8 +; XTENSA-NEXT: l32i a10, a1, 4 # 4-byte Folded Reload +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a3 +; XTENSA-NEXT: l8ui a2, a1, 8 +; XTENSA-NEXT: bnez a10, .LBB48_4 +; XTENSA-NEXT: .LBB48_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 8 +; XTENSA-NEXT: and a8, a2, a4 +; XTENSA-NEXT: or a12, a5, a5 +; XTENSA-NEXT: l32i a9, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: bgeu a9, a8, .LBB48_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB48_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB48_1 +; XTENSA-NEXT: .LBB48_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_acq_rel: +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i8_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: and a12, a3, a9 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB48_2 +; XTENSA-ATOMIC-NEXT: .LBB48_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB48_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB48_6 +; XTENSA-ATOMIC-NEXT: .LBB48_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a12, a5, .LBB48_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB48_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB48_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB48_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB48_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB48_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB48_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB48_1 +; XTENSA-ATOMIC-NEXT: .LBB48_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i16 %b acq_rel - ret i16 %1 + %res = atomicrmw umax ptr %a, i8 %b acq_rel + ret i8 %res } -define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_sub_i16_seq_cst: +define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i8_seq_cst: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 5 -; XTENSA-NEXT: l32r a8, .LCPI49_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a8, a3, a3 +; XTENSA-NEXT: s32i a2, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: l8ui a2, a2, 0 +; XTENSA-NEXT: movi a5, 255 +; XTENSA-NEXT: and a4, a8, a5 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a6, .LCPI49_0 +; XTENSA-NEXT: j .LBB49_2 +; XTENSA-NEXT: .LBB49_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB49_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: l32i a10, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a6 +; XTENSA-NEXT: l8ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB49_4 +; XTENSA-NEXT: .LBB49_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 4 +; XTENSA-NEXT: and a8, a2, a5 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a4, a8, .LBB49_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB49_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB49_1 +; XTENSA-NEXT: .LBB49_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_seq_cst: +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i8_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: sub a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: and a12, a3, a9 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB49_2 +; XTENSA-ATOMIC-NEXT: .LBB49_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB49_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB49_6 +; XTENSA-ATOMIC-NEXT: .LBB49_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a12, a5, .LBB49_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB49_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB49_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB49_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB49_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB49_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB49_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB49_1 +; XTENSA-ATOMIC-NEXT: .LBB49_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i16 %b seq_cst - ret i16 %1 + %res = atomicrmw umax ptr %a, i8 %b seq_cst + ret i8 %res } -define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_and_i16_monotonic: +define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i8_monotonic: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 0 -; XTENSA-NEXT: l32r a8, .LCPI50_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a8, a3, a3 +; XTENSA-NEXT: s32i a2, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: l8ui a2, a2, 0 +; XTENSA-NEXT: movi a5, 255 +; XTENSA-NEXT: and a4, a8, a5 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a6, .LCPI50_0 +; XTENSA-NEXT: j .LBB50_2 +; XTENSA-NEXT: .LBB50_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB50_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: l32i a10, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a6 +; XTENSA-NEXT: l8ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB50_4 +; XTENSA-NEXT: .LBB50_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 4 +; XTENSA-NEXT: and a8, a2, a5 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a4, a8, .LBB50_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB50_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB50_1 +; XTENSA-NEXT: .LBB50_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_monotonic: +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i8_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: and a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: and a12, a3, a9 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB50_2 +; XTENSA-ATOMIC-NEXT: .LBB50_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB50_6 +; XTENSA-ATOMIC-NEXT: .LBB50_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a12, a5, .LBB50_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB50_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB50_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB50_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB50_1 +; XTENSA-ATOMIC-NEXT: .LBB50_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i16 %b monotonic - ret i16 %1 + %res = atomicrmw umin ptr %a, i8 %b monotonic + ret i8 %res } -define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_and_i16_acquire: +define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i8_acquire: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 2 -; XTENSA-NEXT: l32r a8, .LCPI51_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a8, a3, a3 +; XTENSA-NEXT: s32i a2, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: l8ui a2, a2, 0 +; XTENSA-NEXT: movi a5, 255 +; XTENSA-NEXT: and a4, a8, a5 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a6, .LCPI51_0 +; XTENSA-NEXT: j .LBB51_2 +; XTENSA-NEXT: .LBB51_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB51_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: l32i a10, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a6 +; XTENSA-NEXT: l8ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB51_4 +; XTENSA-NEXT: .LBB51_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 4 +; XTENSA-NEXT: and a8, a2, a5 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a4, a8, .LBB51_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB51_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB51_1 +; XTENSA-NEXT: .LBB51_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_acquire: +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i8_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: and a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: and a12, a3, a9 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB51_2 +; XTENSA-ATOMIC-NEXT: .LBB51_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB51_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB51_6 +; XTENSA-ATOMIC-NEXT: .LBB51_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a12, a5, .LBB51_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB51_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB51_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB51_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB51_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB51_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB51_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB51_1 +; XTENSA-ATOMIC-NEXT: .LBB51_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i16 %b acquire - ret i16 %1 + %res = atomicrmw umin ptr %a, i8 %b acquire + ret i8 %res } -define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_and_i16_release: +define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i8_release: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 3 -; XTENSA-NEXT: l32r a8, .LCPI52_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: s32i a2, a1, 4 # 4-byte Folded Spill +; XTENSA-NEXT: l8ui a2, a2, 0 +; XTENSA-NEXT: movi a4, 255 +; XTENSA-NEXT: or a5, a3, a3 +; XTENSA-NEXT: and a8, a3, a4 +; XTENSA-NEXT: s32i a8, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a3, .LCPI52_0 +; XTENSA-NEXT: j .LBB52_2 +; XTENSA-NEXT: .LBB52_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB52_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 8 +; XTENSA-NEXT: l32i a10, a1, 4 # 4-byte Folded Reload +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a3 +; XTENSA-NEXT: l8ui a2, a1, 8 +; XTENSA-NEXT: bnez a10, .LBB52_4 +; XTENSA-NEXT: .LBB52_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 8 +; XTENSA-NEXT: and a8, a2, a4 +; XTENSA-NEXT: or a12, a5, a5 +; XTENSA-NEXT: l32i a9, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: bltu a9, a8, .LBB52_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB52_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB52_1 +; XTENSA-NEXT: .LBB52_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_release: +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i8_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: and a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: and a12, a3, a9 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB52_2 +; XTENSA-ATOMIC-NEXT: .LBB52_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB52_6 +; XTENSA-ATOMIC-NEXT: .LBB52_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a12, a5, .LBB52_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB52_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB52_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB52_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB52_1 +; XTENSA-ATOMIC-NEXT: .LBB52_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i16 %b release - ret i16 %1 + %res = atomicrmw umin ptr %a, i8 %b release + ret i8 %res } -define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_and_i16_acq_rel: +define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i8_acq_rel: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 4 -; XTENSA-NEXT: l32r a8, .LCPI53_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: s32i a2, a1, 4 # 4-byte Folded Spill +; XTENSA-NEXT: l8ui a2, a2, 0 +; XTENSA-NEXT: movi a4, 255 +; XTENSA-NEXT: or a5, a3, a3 +; XTENSA-NEXT: and a8, a3, a4 +; XTENSA-NEXT: s32i a8, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a3, .LCPI53_0 +; XTENSA-NEXT: j .LBB53_2 +; XTENSA-NEXT: .LBB53_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB53_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 8 +; XTENSA-NEXT: l32i a10, a1, 4 # 4-byte Folded Reload +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a3 +; XTENSA-NEXT: l8ui a2, a1, 8 +; XTENSA-NEXT: bnez a10, .LBB53_4 +; XTENSA-NEXT: .LBB53_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 8 +; XTENSA-NEXT: and a8, a2, a4 +; XTENSA-NEXT: or a12, a5, a5 +; XTENSA-NEXT: l32i a9, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: bltu a9, a8, .LBB53_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB53_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB53_1 +; XTENSA-NEXT: .LBB53_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_acq_rel: +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i8_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: and a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: and a12, a3, a9 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB53_2 +; XTENSA-ATOMIC-NEXT: .LBB53_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB53_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB53_6 +; XTENSA-ATOMIC-NEXT: .LBB53_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a12, a5, .LBB53_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB53_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB53_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB53_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB53_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB53_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB53_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB53_1 +; XTENSA-ATOMIC-NEXT: .LBB53_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i16 %b acq_rel - ret i16 %1 + %res = atomicrmw umin ptr %a, i8 %b acq_rel + ret i8 %res } -define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_and_i16_seq_cst: +define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i8_seq_cst: ; XTENSA: # %bb.0: -; XTENSA-NEXT: entry a1, 32 -; XTENSA-NEXT: or a11, a3, a3 -; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: movi a12, 5 -; XTENSA-NEXT: l32r a8, .LCPI54_0 -; XTENSA-NEXT: callx8 a8 -; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a8, a3, a3 +; XTENSA-NEXT: s32i a2, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: l8ui a2, a2, 0 +; XTENSA-NEXT: movi a5, 255 +; XTENSA-NEXT: and a4, a8, a5 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a6, .LCPI54_0 +; XTENSA-NEXT: j .LBB54_2 +; XTENSA-NEXT: .LBB54_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB54_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: l32i a10, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a6 +; XTENSA-NEXT: l8ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB54_4 +; XTENSA-NEXT: .LBB54_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s8i a2, a1, 4 +; XTENSA-NEXT: and a8, a2, a5 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a4, a8, .LBB54_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB54_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB54_1 +; XTENSA-NEXT: .LBB54_4: # %atomicrmw.end ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_seq_cst: +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i8_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: and a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: and a12, a3, a9 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB54_2 +; XTENSA-ATOMIC-NEXT: .LBB54_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB54_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB54_6 +; XTENSA-ATOMIC-NEXT: .LBB54_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a7, a15 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: or a6, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a12, a5, .LBB54_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB54_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a7, a7 +; XTENSA-ATOMIC-NEXT: .LBB54_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB54_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a6, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a7, a7 +; XTENSA-ATOMIC-NEXT: and a6, a15, a10 +; XTENSA-ATOMIC-NEXT: or a7, a6, a7 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB54_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a11, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB54_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB54_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB54_1 +; XTENSA-ATOMIC-NEXT: .LBB54_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i16 %b seq_cst - ret i16 %1 + %res = atomicrmw umin ptr %a, i8 %b seq_cst + ret i8 %res } -define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_nand_i16_monotonic: +define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i16_monotonic: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -2850,42 +3849,52 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_monotonic: +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI55_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 ; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a14, a13, a13 -; XTENSA-ATOMIC-NEXT: and a13, a14, a11 -; XTENSA-ATOMIC-NEXT: and a13, a13, a12 -; XTENSA-ATOMIC-NEXT: and a13, a13, a11 -; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 -; XTENSA-ATOMIC-NEXT: or a15, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a15, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a13, a15 -; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB55_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB55_2 +; XTENSA-ATOMIC-NEXT: .LBB55_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB55_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB55_4 +; XTENSA-ATOMIC-NEXT: .LBB55_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a15, a10 +; XTENSA-ATOMIC-NEXT: or a14, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a11, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB55_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB55_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB55_1 +; XTENSA-ATOMIC-NEXT: .LBB55_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a13 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a14 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw nand ptr %a, i16 %b monotonic - ret i16 %1 + %res = atomicrmw xchg ptr %a, i16 %b monotonic + ret i16 %res } -define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_nand_i16_acquire: +define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i16_acquire: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -2896,43 +3905,53 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_acquire: +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI56_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 ; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a14, a13, a13 -; XTENSA-ATOMIC-NEXT: and a13, a14, a11 -; XTENSA-ATOMIC-NEXT: and a13, a13, a12 -; XTENSA-ATOMIC-NEXT: and a13, a13, a11 -; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 -; XTENSA-ATOMIC-NEXT: or a15, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a15, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a13, a15 -; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB56_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB56_2 +; XTENSA-ATOMIC-NEXT: .LBB56_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB56_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB56_4 +; XTENSA-ATOMIC-NEXT: .LBB56_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a15, a10 +; XTENSA-ATOMIC-NEXT: or a14, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a11, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB56_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB56_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB56_1 +; XTENSA-ATOMIC-NEXT: .LBB56_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a13 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a14 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw nand ptr %a, i16 %b acquire - ret i16 %1 + %res = atomicrmw xchg ptr %a, i16 %b acquire + ret i16 %res } -define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_nand_i16_release: +define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i16_release: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -2943,43 +3962,53 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_release: +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI57_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 ; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a14, a13, a13 -; XTENSA-ATOMIC-NEXT: and a13, a14, a11 -; XTENSA-ATOMIC-NEXT: and a13, a13, a12 -; XTENSA-ATOMIC-NEXT: and a13, a13, a11 -; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 -; XTENSA-ATOMIC-NEXT: or a15, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a15, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a13, a15 -; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB57_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB57_2 +; XTENSA-ATOMIC-NEXT: .LBB57_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB57_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB57_4 +; XTENSA-ATOMIC-NEXT: .LBB57_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a15, a10 +; XTENSA-ATOMIC-NEXT: or a14, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a11, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB57_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB57_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB57_1 +; XTENSA-ATOMIC-NEXT: .LBB57_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a13 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a14 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw nand ptr %a, i16 %b release - ret i16 %1 + %res = atomicrmw xchg ptr %a, i16 %b release + ret i16 %res } -define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_nand_i16_acq_rel: +define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i16_acq_rel: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -2990,44 +4019,54 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_acq_rel: +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI58_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 ; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a14, a13, a13 -; XTENSA-ATOMIC-NEXT: and a13, a14, a11 -; XTENSA-ATOMIC-NEXT: and a13, a13, a12 -; XTENSA-ATOMIC-NEXT: and a13, a13, a11 -; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 -; XTENSA-ATOMIC-NEXT: or a15, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a15, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a13, a15 -; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB58_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB58_2 +; XTENSA-ATOMIC-NEXT: .LBB58_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB58_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB58_4 +; XTENSA-ATOMIC-NEXT: .LBB58_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a15, a10 +; XTENSA-ATOMIC-NEXT: or a14, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a11, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB58_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB58_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB58_1 +; XTENSA-ATOMIC-NEXT: .LBB58_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a13 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a14 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw nand ptr %a, i16 %b acq_rel - ret i16 %1 + %res = atomicrmw xchg ptr %a, i16 %b acq_rel + ret i16 %res } -define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_nand_i16_seq_cst: +define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i16_seq_cst: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3038,44 +4077,54 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_seq_cst: +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI59_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 ; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: l32i a13, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a12, a3 -; XTENSA-ATOMIC-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a14, a13, a13 -; XTENSA-ATOMIC-NEXT: and a13, a14, a11 -; XTENSA-ATOMIC-NEXT: and a13, a13, a12 -; XTENSA-ATOMIC-NEXT: and a13, a13, a11 -; XTENSA-ATOMIC-NEXT: xor a15, a14, a11 -; XTENSA-ATOMIC-NEXT: or a15, a13, a15 -; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a15, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a13, a15 -; XTENSA-ATOMIC-NEXT: bne a15, a14, .LBB59_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a10, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a11, -4 +; XTENSA-ATOMIC-NEXT: and a11, a2, a11 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB59_2 +; XTENSA-ATOMIC-NEXT: .LBB59_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB59_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB59_4 +; XTENSA-ATOMIC-NEXT: .LBB59_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a15, a10 +; XTENSA-ATOMIC-NEXT: or a14, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a11, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a14, a15, .LBB59_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB59_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB59_1 +; XTENSA-ATOMIC-NEXT: .LBB59_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a13 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a14 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw nand ptr %a, i16 %b seq_cst - ret i16 %1 + %res = atomicrmw xchg ptr %a, i16 %b seq_cst + ret i16 %res } -define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_or_i16_monotonic: +define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i16_monotonic: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3086,44 +4135,54 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_monotonic: +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: or a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI60_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB60_2 +; XTENSA-ATOMIC-NEXT: .LBB60_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB60_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB60_4 +; XTENSA-ATOMIC-NEXT: .LBB60_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: add a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB60_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB60_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB60_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB60_1 +; XTENSA-ATOMIC-NEXT: .LBB60_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i16 %b monotonic - ret i16 %1 + %res = atomicrmw add ptr %a, i16 %b monotonic + ret i16 %res } -define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_or_i16_acquire: +define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i16_acquire: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3134,45 +4193,55 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_acquire: +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: or a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI61_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB61_2 +; XTENSA-ATOMIC-NEXT: .LBB61_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB61_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB61_4 +; XTENSA-ATOMIC-NEXT: .LBB61_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: add a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB61_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB61_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB61_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB61_1 +; XTENSA-ATOMIC-NEXT: .LBB61_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i16 %b acquire - ret i16 %1 + %res = atomicrmw add ptr %a, i16 %b acquire + ret i16 %res } -define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_or_i16_release: +define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i16_release: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3183,45 +4252,55 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_release: +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: or a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI62_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB62_2 +; XTENSA-ATOMIC-NEXT: .LBB62_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB62_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB62_4 +; XTENSA-ATOMIC-NEXT: .LBB62_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: add a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB62_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB62_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB62_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB62_1 +; XTENSA-ATOMIC-NEXT: .LBB62_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i16 %b release - ret i16 %1 + %res = atomicrmw add ptr %a, i16 %b release + ret i16 %res } -define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_or_i16_acq_rel: +define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i16_acq_rel: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3232,46 +4311,56 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_acq_rel: +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: or a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI63_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB63_2 +; XTENSA-ATOMIC-NEXT: .LBB63_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB63_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB63_4 +; XTENSA-ATOMIC-NEXT: .LBB63_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: add a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB63_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB63_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB63_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB63_1 +; XTENSA-ATOMIC-NEXT: .LBB63_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i16 %b acq_rel - ret i16 %1 + %res = atomicrmw add ptr %a, i16 %b acq_rel + ret i16 %res } -define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_or_i16_seq_cst: +define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i16_seq_cst: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3282,46 +4371,56 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_seq_cst: +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: or a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI64_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB64_2 +; XTENSA-ATOMIC-NEXT: .LBB64_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB64_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB64_4 +; XTENSA-ATOMIC-NEXT: .LBB64_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: add a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB64_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB64_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB64_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB64_1 +; XTENSA-ATOMIC-NEXT: .LBB64_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i16 %b seq_cst - ret i16 %1 + %res = atomicrmw add ptr %a, i16 %b seq_cst + ret i16 %res } -define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xor_i16_monotonic: +define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i16_monotonic: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3332,44 +4431,54 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_monotonic: +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI65_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB65_2 +; XTENSA-ATOMIC-NEXT: .LBB65_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB65_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB65_4 +; XTENSA-ATOMIC-NEXT: .LBB65_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB65_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB65_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB65_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB65_1 +; XTENSA-ATOMIC-NEXT: .LBB65_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i16 %b monotonic - ret i16 %1 + %res = atomicrmw sub ptr %a, i16 %b monotonic + ret i16 %res } -define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xor_i16_acquire: +define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i16_acquire: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3380,45 +4489,55 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_acquire: +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI66_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB66_2 +; XTENSA-ATOMIC-NEXT: .LBB66_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB66_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB66_4 +; XTENSA-ATOMIC-NEXT: .LBB66_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB66_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB66_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB66_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB66_1 +; XTENSA-ATOMIC-NEXT: .LBB66_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i16 %b acquire - ret i16 %1 + %res = atomicrmw sub ptr %a, i16 %b acquire + ret i16 %res } -define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xor_i16_release: +define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i16_release: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3429,45 +4548,55 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_release: +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI67_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB67_2 +; XTENSA-ATOMIC-NEXT: .LBB67_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB67_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB67_4 +; XTENSA-ATOMIC-NEXT: .LBB67_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB67_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB67_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB67_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB67_1 +; XTENSA-ATOMIC-NEXT: .LBB67_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i16 %b release - ret i16 %1 + %res = atomicrmw sub ptr %a, i16 %b release + ret i16 %res } -define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xor_i16_acq_rel: +define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i16_acq_rel: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3478,46 +4607,56 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_acq_rel: +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI68_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB68_2 +; XTENSA-ATOMIC-NEXT: .LBB68_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB68_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB68_4 +; XTENSA-ATOMIC-NEXT: .LBB68_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB68_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB68_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB68_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB68_1 +; XTENSA-ATOMIC-NEXT: .LBB68_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i16 %b acq_rel - ret i16 %1 + %res = atomicrmw sub ptr %a, i16 %b acq_rel + ret i16 %res } -define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xor_i16_seq_cst: +define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i16_seq_cst: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3528,146 +4667,56 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_seq_cst: +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a9, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a10, 1 -; XTENSA-ATOMIC-NEXT: slli a10, a10, 16 -; XTENSA-ATOMIC-NEXT: addi a10, a10, -1 -; XTENSA-ATOMIC-NEXT: ssl a8 -; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a10 -; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a9, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a3 -; XTENSA-ATOMIC-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: xor a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 -; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI69_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a11, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a12, -4 +; XTENSA-ATOMIC-NEXT: and a12, a2, a12 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 1 +; XTENSA-ATOMIC-NEXT: j .LBB69_2 +; XTENSA-ATOMIC-NEXT: .LBB69_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB69_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB69_4 +; XTENSA-ATOMIC-NEXT: .LBB69_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a7, a15, a11 +; XTENSA-ATOMIC-NEXT: sub a6, a15, a9 +; XTENSA-ATOMIC-NEXT: and a6, a6, a10 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a9, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB69_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a12, 0 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB69_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB69_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a13, a13 +; XTENSA-ATOMIC-NEXT: j .LBB69_1 +; XTENSA-ATOMIC-NEXT: .LBB69_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a10 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i16 %b seq_cst - ret i16 %1 + %res = atomicrmw sub ptr %a, i16 %b seq_cst + ret i16 %res } -;define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw max ptr %a, i16 %b monotonic -; ret i16 %1 -;} -; -;define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw max ptr %a, i16 %b acquire -; ret i16 %1 -;} -; -;define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw max ptr %a, i16 %b release -; ret i16 %1 -;} -; -;define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw max ptr %a, i16 %b acq_rel -; ret i16 %1 -;} -; -;define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw max ptr %a, i16 %b seq_cst -; ret i16 %1 -;} - -;define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw min ptr %a, i16 %b monotonic -; ret i16 %1 -;} -; -;define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw min ptr %a, i16 %b acquire -; ret i16 %1 -;} -; -;define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw min ptr %a, i16 %b release -; ret i16 %1 -;} -; -;define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw min ptr %a, i16 %b acq_rel -; ret i16 %1 -;} -; -;define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw min ptr %a, i16 %b seq_cst -; ret i16 %1 -;} - -;define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i16 %b monotonic -; ret i16 %1 -;} -; -;define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i16 %b acquire -; ret i16 %1 -;} -; -;define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i16 %b release -; ret i16 %1 -;} -; -;define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i16 %b acq_rel -; ret i16 %1 -;} -; -;define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i16 %b seq_cst -; ret i16 %1 -;} - -;define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i16 %b monotonic -; ret i16 %1 -;} -; -;define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i16 %b acquire -; ret i16 %1 -;} -; -;define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i16 %b release -; ret i16 %1 -;} -; -;define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i16 %b acq_rel -; ret i16 %1 -;} -; -;define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i16 %b seq_cst -; ret i16 %1 -;} - -define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xchg_i32_monotonic: +define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i16_monotonic: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3678,26 +4727,52 @@ define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_monotonic: +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB70_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a8, a9, a9 -; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 -; XTENSA-ATOMIC-NEXT: or a9, a3, a3 -; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: bne a9, a8, .LBB70_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI70_0 +; XTENSA-ATOMIC-NEXT: and a10, a3, a9 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a11 +; XTENSA-ATOMIC-NEXT: or a9, a10, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB70_2 +; XTENSA-ATOMIC-NEXT: .LBB70_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB70_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB70_4 +; XTENSA-ATOMIC-NEXT: .LBB70_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB70_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB70_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB70_1 +; XTENSA-ATOMIC-NEXT: .LBB70_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i32 %b monotonic - ret i32 %1 + %res = atomicrmw and ptr %a, i16 %b monotonic + ret i16 %res } -define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xchg_i32_acquire: +define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i16_acquire: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3708,27 +4783,53 @@ define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_acquire: +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB71_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a8, a9, a9 -; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 -; XTENSA-ATOMIC-NEXT: or a9, a3, a3 -; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: bne a9, a8, .LBB71_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: or a2, a8, a8 -; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i32 %b acquire - ret i32 %1 -} - -define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xchg_i32_release: +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI71_0 +; XTENSA-ATOMIC-NEXT: and a10, a3, a9 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a11 +; XTENSA-ATOMIC-NEXT: or a9, a10, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB71_2 +; XTENSA-ATOMIC-NEXT: .LBB71_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB71_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB71_4 +; XTENSA-ATOMIC-NEXT: .LBB71_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB71_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB71_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB71_1 +; XTENSA-ATOMIC-NEXT: .LBB71_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw and ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i16_release: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3739,27 +4840,53 @@ define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_release: +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI72_0 +; XTENSA-ATOMIC-NEXT: and a10, a3, a9 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a11 +; XTENSA-ATOMIC-NEXT: or a9, a10, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB72_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a8, a9, a9 -; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 -; XTENSA-ATOMIC-NEXT: or a9, a3, a3 -; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: bne a9, a8, .LBB72_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB72_2 +; XTENSA-ATOMIC-NEXT: .LBB72_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB72_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB72_4 +; XTENSA-ATOMIC-NEXT: .LBB72_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB72_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB72_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB72_1 +; XTENSA-ATOMIC-NEXT: .LBB72_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i32 %b release - ret i32 %1 + %res = atomicrmw and ptr %a, i16 %b release + ret i16 %res } -define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xchg_i32_acq_rel: +define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i16_acq_rel: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3770,28 +4897,54 @@ define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_acq_rel: +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI73_0 +; XTENSA-ATOMIC-NEXT: and a10, a3, a9 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a11 +; XTENSA-ATOMIC-NEXT: or a9, a10, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB73_2 +; XTENSA-ATOMIC-NEXT: .LBB73_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB73_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB73_4 +; XTENSA-ATOMIC-NEXT: .LBB73_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB73_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB73_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB73_1 +; XTENSA-ATOMIC-NEXT: .LBB73_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB73_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a8, a9, a9 -; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 -; XTENSA-ATOMIC-NEXT: or a9, a3, a3 -; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: bne a9, a8, .LBB73_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i32 %b acq_rel - ret i32 %1 + %res = atomicrmw and ptr %a, i16 %b acq_rel + ret i16 %res } -define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_xchg_i32_seq_cst: +define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i16_seq_cst: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3802,28 +4955,54 @@ define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_seq_cst: +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI74_0 +; XTENSA-ATOMIC-NEXT: and a10, a3, a9 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a11 +; XTENSA-ATOMIC-NEXT: or a9, a10, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB74_2 +; XTENSA-ATOMIC-NEXT: .LBB74_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB74_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB74_4 +; XTENSA-ATOMIC-NEXT: .LBB74_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB74_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB74_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB74_1 +; XTENSA-ATOMIC-NEXT: .LBB74_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB74_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a8, a9, a9 -; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 -; XTENSA-ATOMIC-NEXT: or a9, a3, a3 -; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: bne a9, a8, .LBB74_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xchg ptr %a, i32 %b seq_cst - ret i32 %1 + %res = atomicrmw and ptr %a, i16 %b seq_cst + ret i16 %res } -define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_add_i32_monotonic: +define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i16_monotonic: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3834,26 +5013,55 @@ define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_monotonic: +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: add a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB75_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI75_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a12, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: l32i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: movi a15, 1 +; XTENSA-ATOMIC-NEXT: j .LBB75_2 +; XTENSA-ATOMIC-NEXT: .LBB75_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB75_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a6, a6 +; XTENSA-ATOMIC-NEXT: beqi a5, 1, .LBB75_4 +; XTENSA-ATOMIC-NEXT: .LBB75_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a6, a7, a12 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: xor a5, a5, a11 +; XTENSA-ATOMIC-NEXT: and a5, a5, a10 +; XTENSA-ATOMIC-NEXT: or a6, a6, a5 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a6, a13, 0 +; XTENSA-ATOMIC-NEXT: or a5, a15, a15 +; XTENSA-ATOMIC-NEXT: beq a6, a7, .LBB75_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB75_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a5, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB75_1 +; XTENSA-ATOMIC-NEXT: .LBB75_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a6 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i32 %b monotonic - ret i32 %1 + %res = atomicrmw nand ptr %a, i16 %b monotonic + ret i16 %res } -define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_add_i32_acquire: +define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i16_acquire: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3864,27 +5072,56 @@ define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_acquire: +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: add a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB76_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI76_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a12, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: l32i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: movi a15, 1 +; XTENSA-ATOMIC-NEXT: j .LBB76_2 +; XTENSA-ATOMIC-NEXT: .LBB76_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB76_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a6, a6 +; XTENSA-ATOMIC-NEXT: beqi a5, 1, .LBB76_4 +; XTENSA-ATOMIC-NEXT: .LBB76_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a6, a7, a12 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: xor a5, a5, a11 +; XTENSA-ATOMIC-NEXT: and a5, a5, a10 +; XTENSA-ATOMIC-NEXT: or a6, a6, a5 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a6, a13, 0 +; XTENSA-ATOMIC-NEXT: or a5, a15, a15 +; XTENSA-ATOMIC-NEXT: beq a6, a7, .LBB76_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB76_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a5, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB76_1 +; XTENSA-ATOMIC-NEXT: .LBB76_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a6 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i32 %b acquire - ret i32 %1 + %res = atomicrmw nand ptr %a, i16 %b acquire + ret i16 %res } -define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_add_i32_release: +define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i16_release: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3895,27 +5132,56 @@ define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_release: +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: add a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB77_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI77_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a12, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: movi a15, 1 +; XTENSA-ATOMIC-NEXT: j .LBB77_2 +; XTENSA-ATOMIC-NEXT: .LBB77_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB77_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a6, a6 +; XTENSA-ATOMIC-NEXT: beqi a5, 1, .LBB77_4 +; XTENSA-ATOMIC-NEXT: .LBB77_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a6, a7, a12 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: xor a5, a5, a11 +; XTENSA-ATOMIC-NEXT: and a5, a5, a10 +; XTENSA-ATOMIC-NEXT: or a6, a6, a5 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a6, a13, 0 +; XTENSA-ATOMIC-NEXT: or a5, a15, a15 +; XTENSA-ATOMIC-NEXT: beq a6, a7, .LBB77_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB77_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a5, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB77_1 +; XTENSA-ATOMIC-NEXT: .LBB77_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a6 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i32 %b release - ret i32 %1 + %res = atomicrmw nand ptr %a, i16 %b release + ret i16 %res } -define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_add_i32_acq_rel: +define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i16_acq_rel: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3926,28 +5192,57 @@ define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_acq_rel: +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: add a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB78_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI78_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a12, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: movi a15, 1 +; XTENSA-ATOMIC-NEXT: j .LBB78_2 +; XTENSA-ATOMIC-NEXT: .LBB78_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB78_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a6, a6 +; XTENSA-ATOMIC-NEXT: beqi a5, 1, .LBB78_4 +; XTENSA-ATOMIC-NEXT: .LBB78_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a6, a7, a12 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: xor a5, a5, a11 +; XTENSA-ATOMIC-NEXT: and a5, a5, a10 +; XTENSA-ATOMIC-NEXT: or a6, a6, a5 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a6, a13, 0 +; XTENSA-ATOMIC-NEXT: or a5, a15, a15 +; XTENSA-ATOMIC-NEXT: beq a6, a7, .LBB78_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB78_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a5, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB78_1 +; XTENSA-ATOMIC-NEXT: .LBB78_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a6 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i32 %b acq_rel - ret i32 %1 + %res = atomicrmw nand ptr %a, i16 %b acq_rel + ret i16 %res } -define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_add_i32_seq_cst: +define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_nand_i16_seq_cst: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3958,28 +5253,57 @@ define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_seq_cst: +; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: add a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB79_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32r a10, .LCPI79_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a10 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a11, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a11 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a10 +; XTENSA-ATOMIC-NEXT: movi a11, -1 +; XTENSA-ATOMIC-NEXT: xor a12, a10, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: movi a15, 1 +; XTENSA-ATOMIC-NEXT: j .LBB79_2 +; XTENSA-ATOMIC-NEXT: .LBB79_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB79_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a6, a6 +; XTENSA-ATOMIC-NEXT: beqi a5, 1, .LBB79_4 +; XTENSA-ATOMIC-NEXT: .LBB79_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a6, a7, a12 +; XTENSA-ATOMIC-NEXT: and a5, a7, a9 +; XTENSA-ATOMIC-NEXT: xor a5, a5, a11 +; XTENSA-ATOMIC-NEXT: and a5, a5, a10 +; XTENSA-ATOMIC-NEXT: or a6, a6, a5 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a6, a13, 0 +; XTENSA-ATOMIC-NEXT: or a5, a15, a15 +; XTENSA-ATOMIC-NEXT: beq a6, a7, .LBB79_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB79_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a5, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB79_1 +; XTENSA-ATOMIC-NEXT: .LBB79_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a6 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw add ptr %a, i32 %b seq_cst - ret i32 %1 + %res = atomicrmw nand ptr %a, i16 %b seq_cst + ret i16 %res } -define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_sub_i32_monotonic: +define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i16_monotonic: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -3990,26 +5314,47 @@ define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_monotonic: +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: sub a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB80_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32r a8, .LCPI80_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB80_2 +; XTENSA-ATOMIC-NEXT: .LBB80_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB80_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB80_4 +; XTENSA-ATOMIC-NEXT: .LBB80_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB80_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB80_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB80_1 +; XTENSA-ATOMIC-NEXT: .LBB80_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i32 %b monotonic - ret i32 %1 + %res = atomicrmw or ptr %a, i16 %b monotonic + ret i16 %res } -define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_sub_i32_acquire: +define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i16_acquire: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -4020,27 +5365,48 @@ define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_acquire: +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: sub a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB81_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32r a8, .LCPI81_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB81_2 +; XTENSA-ATOMIC-NEXT: .LBB81_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB81_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB81_4 +; XTENSA-ATOMIC-NEXT: .LBB81_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB81_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB81_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB81_1 +; XTENSA-ATOMIC-NEXT: .LBB81_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i32 %b acquire - ret i32 %1 + %res = atomicrmw or ptr %a, i16 %b acquire + ret i16 %res } -define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_sub_i32_release: +define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i16_release: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -4051,27 +5417,48 @@ define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_release: +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32r a8, .LCPI82_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: sub a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB82_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB82_2 +; XTENSA-ATOMIC-NEXT: .LBB82_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB82_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB82_4 +; XTENSA-ATOMIC-NEXT: .LBB82_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB82_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB82_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB82_1 +; XTENSA-ATOMIC-NEXT: .LBB82_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i32 %b release - ret i32 %1 + %res = atomicrmw or ptr %a, i16 %b release + ret i16 %res } -define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_sub_i32_acq_rel: +define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i16_acq_rel: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -4082,28 +5469,49 @@ define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_acq_rel: +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32r a8, .LCPI83_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: sub a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB83_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB83_2 +; XTENSA-ATOMIC-NEXT: .LBB83_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB83_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB83_4 +; XTENSA-ATOMIC-NEXT: .LBB83_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB83_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB83_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB83_1 +; XTENSA-ATOMIC-NEXT: .LBB83_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i32 %b acq_rel - ret i32 %1 + %res = atomicrmw or ptr %a, i16 %b acq_rel + ret i16 %res } -define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_sub_i32_seq_cst: +define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_or_i16_seq_cst: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -4114,28 +5522,49 @@ define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_seq_cst: +; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32r a8, .LCPI84_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: sub a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB84_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB84_2 +; XTENSA-ATOMIC-NEXT: .LBB84_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB84_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB84_4 +; XTENSA-ATOMIC-NEXT: .LBB84_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB84_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB84_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB84_1 +; XTENSA-ATOMIC-NEXT: .LBB84_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw sub ptr %a, i32 %b seq_cst - ret i32 %1 + %res = atomicrmw or ptr %a, i16 %b seq_cst + ret i16 %res } -define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_and_i32_monotonic: +define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i16_monotonic: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -4146,26 +5575,47 @@ define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_monotonic: +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: and a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB85_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32r a8, .LCPI85_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB85_2 +; XTENSA-ATOMIC-NEXT: .LBB85_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB85_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB85_4 +; XTENSA-ATOMIC-NEXT: .LBB85_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB85_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB85_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB85_1 +; XTENSA-ATOMIC-NEXT: .LBB85_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i32 %b monotonic - ret i32 %1 + %res = atomicrmw xor ptr %a, i16 %b monotonic + ret i16 %res } -define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_and_i32_acquire: +define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i16_acquire: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -4176,27 +5626,48 @@ define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_acquire: +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: and a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB86_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32r a8, .LCPI86_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB86_2 +; XTENSA-ATOMIC-NEXT: .LBB86_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB86_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB86_4 +; XTENSA-ATOMIC-NEXT: .LBB86_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB86_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB86_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB86_1 +; XTENSA-ATOMIC-NEXT: .LBB86_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i32 %b acquire - ret i32 %1 + %res = atomicrmw xor ptr %a, i16 %b acquire + ret i16 %res } -define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_and_i32_release: +define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i16_release: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -4207,27 +5678,48 @@ define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_release: +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_release: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32r a8, .LCPI87_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: and a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB87_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB87_2 +; XTENSA-ATOMIC-NEXT: .LBB87_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB87_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB87_4 +; XTENSA-ATOMIC-NEXT: .LBB87_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB87_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB87_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB87_1 +; XTENSA-ATOMIC-NEXT: .LBB87_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i32 %b release - ret i32 %1 + %res = atomicrmw xor ptr %a, i16 %b release + ret i16 %res } -define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_and_i32_acq_rel: +define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i16_acq_rel: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -4238,28 +5730,49 @@ define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_acq_rel: +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_acq_rel: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32r a8, .LCPI88_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: and a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB88_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB88_2 +; XTENSA-ATOMIC-NEXT: .LBB88_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB88_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB88_4 +; XTENSA-ATOMIC-NEXT: .LBB88_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB88_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB88_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB88_1 +; XTENSA-ATOMIC-NEXT: .LBB88_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i32 %b acq_rel - ret i32 %1 + %res = atomicrmw xor ptr %a, i16 %b acq_rel + ret i16 %res } -define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind { -; XTENSA-LABEL: atomicrmw_and_i32_seq_cst: +define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xor_i16_seq_cst: ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 32 ; XTENSA-NEXT: or a11, a3, a3 @@ -4270,49 +5783,2764 @@ define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw ; -; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_seq_cst: +; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_seq_cst: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32r a8, .LCPI89_0 +; XTENSA-ATOMIC-NEXT: and a9, a3, a8 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a10, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a10 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: and a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB89_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB89_2 +; XTENSA-ATOMIC-NEXT: .LBB89_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB89_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a13, a13 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB89_4 +; XTENSA-ATOMIC-NEXT: .LBB89_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a13, a14, a9 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a13, a14, .LBB89_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB89_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB89_1 +; XTENSA-ATOMIC-NEXT: .LBB89_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a13 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw and ptr %a, i32 %b seq_cst - ret i32 %1 + %res = atomicrmw xor ptr %a, i16 %b seq_cst + ret i16 %res } -;define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw nand ptr %a, i32 %b monotonic -; ret i32 %1 -;} -; -;define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw nand ptr %a, i32 %b acquire -; ret i32 %1 -;} +define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 16 +; XTENSA-NEXT: srai a5, a8, 16 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a4, .LCPI90_0 +; XTENSA-NEXT: j .LBB90_2 +; XTENSA-NEXT: .LBB90_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB90_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB90_4 +; XTENSA-NEXT: .LBB90_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 16 +; XTENSA-NEXT: srai a8, a8, 16 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bge a5, a8, .LBB90_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB90_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB90_1 +; XTENSA-NEXT: .LBB90_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw nand ptr %a, i32 %b release -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI90_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: slli a11, a3, 16 +; XTENSA-ATOMIC-NEXT: srai a11, a11, 16 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB90_2 +; XTENSA-ATOMIC-NEXT: .LBB90_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB90_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a15, a15 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB90_6 +; XTENSA-ATOMIC-NEXT: .LBB90_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a14 +; XTENSA-ATOMIC-NEXT: slli a7, a15, 16 +; XTENSA-ATOMIC-NEXT: srai a6, a7, 16 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a11, a6, .LBB90_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB90_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB90_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB90_2 Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a15, .LCPI90_0 +; XTENSA-ATOMIC-NEXT: and a15, a7, a15 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a15, a15 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: or a15, a7, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a15, a14, .LBB90_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB90_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB90_1 +; XTENSA-ATOMIC-NEXT: .LBB90_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a15 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw max ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 16 +; XTENSA-NEXT: srai a5, a8, 16 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a4, .LCPI91_0 +; XTENSA-NEXT: j .LBB91_2 +; XTENSA-NEXT: .LBB91_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB91_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB91_4 +; XTENSA-NEXT: .LBB91_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 16 +; XTENSA-NEXT: srai a8, a8, 16 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bge a5, a8, .LBB91_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB91_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB91_1 +; XTENSA-NEXT: .LBB91_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI91_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: slli a11, a3, 16 +; XTENSA-ATOMIC-NEXT: srai a11, a11, 16 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB91_2 +; XTENSA-ATOMIC-NEXT: .LBB91_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB91_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a15, a15 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB91_6 +; XTENSA-ATOMIC-NEXT: .LBB91_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a14 +; XTENSA-ATOMIC-NEXT: slli a7, a15, 16 +; XTENSA-ATOMIC-NEXT: srai a6, a7, 16 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a11, a6, .LBB91_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB91_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB91_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB91_2 Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a15, .LCPI91_0 +; XTENSA-ATOMIC-NEXT: and a15, a7, a15 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a15, a15 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: or a15, a7, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a15, a14, .LBB91_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB91_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB91_1 +; XTENSA-ATOMIC-NEXT: .LBB91_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a15 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw max ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a9, a2, a2 +; XTENSA-NEXT: l16ui a2, a9, 0 +; XTENSA-NEXT: s32i a3, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: slli a8, a3, 16 +; XTENSA-NEXT: or a3, a9, a9 +; XTENSA-NEXT: srai a4, a8, 16 +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a5, .LCPI92_0 +; XTENSA-NEXT: j .LBB92_2 +; XTENSA-NEXT: .LBB92_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB92_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: or a10, a3, a3 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l16ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB92_4 +; XTENSA-NEXT: .LBB92_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s16i a2, a1, 4 +; XTENSA-NEXT: slli a8, a2, 16 +; XTENSA-NEXT: srai a8, a8, 16 +; XTENSA-NEXT: l32i a12, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: bge a4, a8, .LBB92_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB92_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB92_1 +; XTENSA-NEXT: .LBB92_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI92_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: slli a11, a3, 16 +; XTENSA-ATOMIC-NEXT: srai a11, a11, 16 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB92_2 +; XTENSA-ATOMIC-NEXT: .LBB92_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB92_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a15, a15 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB92_6 +; XTENSA-ATOMIC-NEXT: .LBB92_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a14 +; XTENSA-ATOMIC-NEXT: slli a7, a15, 16 +; XTENSA-ATOMIC-NEXT: srai a6, a7, 16 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a11, a6, .LBB92_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB92_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB92_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB92_2 Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a15, .LCPI92_0 +; XTENSA-ATOMIC-NEXT: and a15, a7, a15 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a15, a15 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: or a15, a7, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a15, a14, .LBB92_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB92_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB92_1 +; XTENSA-ATOMIC-NEXT: .LBB92_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a15 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw max ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i16_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a9, a2, a2 +; XTENSA-NEXT: l16ui a2, a9, 0 +; XTENSA-NEXT: s32i a3, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: slli a8, a3, 16 +; XTENSA-NEXT: or a3, a9, a9 +; XTENSA-NEXT: srai a4, a8, 16 +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a5, .LCPI93_0 +; XTENSA-NEXT: j .LBB93_2 +; XTENSA-NEXT: .LBB93_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB93_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: or a10, a3, a3 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l16ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB93_4 +; XTENSA-NEXT: .LBB93_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s16i a2, a1, 4 +; XTENSA-NEXT: slli a8, a2, 16 +; XTENSA-NEXT: srai a8, a8, 16 +; XTENSA-NEXT: l32i a12, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: bge a4, a8, .LBB93_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB93_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB93_1 +; XTENSA-NEXT: .LBB93_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i16_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI93_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: slli a11, a3, 16 +; XTENSA-ATOMIC-NEXT: srai a11, a11, 16 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB93_2 +; XTENSA-ATOMIC-NEXT: .LBB93_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB93_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a15, a15 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB93_6 +; XTENSA-ATOMIC-NEXT: .LBB93_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a14 +; XTENSA-ATOMIC-NEXT: slli a7, a15, 16 +; XTENSA-ATOMIC-NEXT: srai a6, a7, 16 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a11, a6, .LBB93_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB93_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB93_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB93_2 Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a15, .LCPI93_0 +; XTENSA-ATOMIC-NEXT: and a15, a7, a15 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a15, a15 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: or a15, a7, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a15, a14, .LBB93_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB93_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB93_1 +; XTENSA-ATOMIC-NEXT: .LBB93_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a15 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw max ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 16 +; XTENSA-NEXT: srai a5, a8, 16 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a4, .LCPI94_0 +; XTENSA-NEXT: j .LBB94_2 +; XTENSA-NEXT: .LBB94_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB94_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB94_4 +; XTENSA-NEXT: .LBB94_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 16 +; XTENSA-NEXT: srai a8, a8, 16 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bge a5, a8, .LBB94_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB94_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB94_1 +; XTENSA-NEXT: .LBB94_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI94_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: slli a11, a3, 16 +; XTENSA-ATOMIC-NEXT: srai a11, a11, 16 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB94_2 +; XTENSA-ATOMIC-NEXT: .LBB94_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB94_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a15, a15 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB94_6 +; XTENSA-ATOMIC-NEXT: .LBB94_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a14 +; XTENSA-ATOMIC-NEXT: slli a7, a15, 16 +; XTENSA-ATOMIC-NEXT: srai a6, a7, 16 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a11, a6, .LBB94_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB94_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB94_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB94_2 Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a15, .LCPI94_0 +; XTENSA-ATOMIC-NEXT: and a15, a7, a15 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a15, a15 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: or a15, a7, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a15, a14, .LBB94_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB94_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB94_1 +; XTENSA-ATOMIC-NEXT: .LBB94_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a15 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw max ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 16 +; XTENSA-NEXT: srai a5, a8, 16 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a4, .LCPI95_0 +; XTENSA-NEXT: j .LBB95_2 +; XTENSA-NEXT: .LBB95_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB95_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB95_4 +; XTENSA-NEXT: .LBB95_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 16 +; XTENSA-NEXT: srai a8, a8, 16 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: blt a5, a8, .LBB95_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB95_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB95_1 +; XTENSA-NEXT: .LBB95_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI95_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: slli a11, a3, 16 +; XTENSA-ATOMIC-NEXT: srai a11, a11, 16 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB95_2 +; XTENSA-ATOMIC-NEXT: .LBB95_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB95_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a15, a15 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB95_6 +; XTENSA-ATOMIC-NEXT: .LBB95_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a14 +; XTENSA-ATOMIC-NEXT: slli a7, a15, 16 +; XTENSA-ATOMIC-NEXT: srai a6, a7, 16 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a11, a6, .LBB95_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB95_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB95_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB95_2 Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a15, .LCPI95_0 +; XTENSA-ATOMIC-NEXT: and a15, a7, a15 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a15, a15 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: or a15, a7, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a15, a14, .LBB95_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB95_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB95_1 +; XTENSA-ATOMIC-NEXT: .LBB95_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a15 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw min ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 16 +; XTENSA-NEXT: srai a5, a8, 16 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a4, .LCPI96_0 +; XTENSA-NEXT: j .LBB96_2 +; XTENSA-NEXT: .LBB96_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB96_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB96_4 +; XTENSA-NEXT: .LBB96_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 16 +; XTENSA-NEXT: srai a8, a8, 16 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: blt a5, a8, .LBB96_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB96_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB96_1 +; XTENSA-NEXT: .LBB96_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI96_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: slli a11, a3, 16 +; XTENSA-ATOMIC-NEXT: srai a11, a11, 16 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB96_2 +; XTENSA-ATOMIC-NEXT: .LBB96_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB96_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a15, a15 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB96_6 +; XTENSA-ATOMIC-NEXT: .LBB96_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a14 +; XTENSA-ATOMIC-NEXT: slli a7, a15, 16 +; XTENSA-ATOMIC-NEXT: srai a6, a7, 16 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a11, a6, .LBB96_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB96_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB96_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB96_2 Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a15, .LCPI96_0 +; XTENSA-ATOMIC-NEXT: and a15, a7, a15 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a15, a15 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: or a15, a7, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a15, a14, .LBB96_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB96_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB96_1 +; XTENSA-ATOMIC-NEXT: .LBB96_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a15 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw min ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a9, a2, a2 +; XTENSA-NEXT: l16ui a2, a9, 0 +; XTENSA-NEXT: s32i a3, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: slli a8, a3, 16 +; XTENSA-NEXT: or a3, a9, a9 +; XTENSA-NEXT: srai a4, a8, 16 +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a5, .LCPI97_0 +; XTENSA-NEXT: j .LBB97_2 +; XTENSA-NEXT: .LBB97_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB97_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: or a10, a3, a3 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l16ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB97_4 +; XTENSA-NEXT: .LBB97_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s16i a2, a1, 4 +; XTENSA-NEXT: slli a8, a2, 16 +; XTENSA-NEXT: srai a8, a8, 16 +; XTENSA-NEXT: l32i a12, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: blt a4, a8, .LBB97_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB97_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB97_1 +; XTENSA-NEXT: .LBB97_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI97_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: slli a11, a3, 16 +; XTENSA-ATOMIC-NEXT: srai a11, a11, 16 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB97_2 +; XTENSA-ATOMIC-NEXT: .LBB97_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB97_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a15, a15 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB97_6 +; XTENSA-ATOMIC-NEXT: .LBB97_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a14 +; XTENSA-ATOMIC-NEXT: slli a7, a15, 16 +; XTENSA-ATOMIC-NEXT: srai a6, a7, 16 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a11, a6, .LBB97_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB97_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB97_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB97_2 Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a15, .LCPI97_0 +; XTENSA-ATOMIC-NEXT: and a15, a7, a15 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a15, a15 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: or a15, a7, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a15, a14, .LBB97_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB97_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB97_1 +; XTENSA-ATOMIC-NEXT: .LBB97_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a15 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw min ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i16_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a9, a2, a2 +; XTENSA-NEXT: l16ui a2, a9, 0 +; XTENSA-NEXT: s32i a3, a1, 0 # 4-byte Folded Spill +; XTENSA-NEXT: slli a8, a3, 16 +; XTENSA-NEXT: or a3, a9, a9 +; XTENSA-NEXT: srai a4, a8, 16 +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a5, .LCPI98_0 +; XTENSA-NEXT: j .LBB98_2 +; XTENSA-NEXT: .LBB98_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB98_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 4 +; XTENSA-NEXT: or a10, a3, a3 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l16ui a2, a1, 4 +; XTENSA-NEXT: bnez a10, .LBB98_4 +; XTENSA-NEXT: .LBB98_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s16i a2, a1, 4 +; XTENSA-NEXT: slli a8, a2, 16 +; XTENSA-NEXT: srai a8, a8, 16 +; XTENSA-NEXT: l32i a12, a1, 0 # 4-byte Folded Reload +; XTENSA-NEXT: blt a4, a8, .LBB98_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB98_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB98_1 +; XTENSA-NEXT: .LBB98_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i16_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI98_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: slli a11, a3, 16 +; XTENSA-ATOMIC-NEXT: srai a11, a11, 16 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB98_2 +; XTENSA-ATOMIC-NEXT: .LBB98_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB98_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a15, a15 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB98_6 +; XTENSA-ATOMIC-NEXT: .LBB98_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a14 +; XTENSA-ATOMIC-NEXT: slli a7, a15, 16 +; XTENSA-ATOMIC-NEXT: srai a6, a7, 16 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a11, a6, .LBB98_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB98_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB98_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB98_2 Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a15, .LCPI98_0 +; XTENSA-ATOMIC-NEXT: and a15, a7, a15 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a15, a15 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: or a15, a7, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a15, a14, .LBB98_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB98_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB98_1 +; XTENSA-ATOMIC-NEXT: .LBB98_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a15 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw min ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: slli a8, a3, 16 +; XTENSA-NEXT: srai a5, a8, 16 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a4, .LCPI99_0 +; XTENSA-NEXT: j .LBB99_2 +; XTENSA-NEXT: .LBB99_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB99_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB99_4 +; XTENSA-NEXT: .LBB99_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: slli a8, a2, 16 +; XTENSA-NEXT: srai a8, a8, 16 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: blt a5, a8, .LBB99_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB99_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB99_1 +; XTENSA-NEXT: .LBB99_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI99_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: slli a11, a3, 16 +; XTENSA-ATOMIC-NEXT: srai a11, a11, 16 +; XTENSA-ATOMIC-NEXT: movi a12, 0 +; XTENSA-ATOMIC-NEXT: movi a13, 1 +; XTENSA-ATOMIC-NEXT: j .LBB99_2 +; XTENSA-ATOMIC-NEXT: .LBB99_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB99_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a15, a15 +; XTENSA-ATOMIC-NEXT: beqi a7, 1, .LBB99_6 +; XTENSA-ATOMIC-NEXT: .LBB99_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a14 +; XTENSA-ATOMIC-NEXT: slli a7, a15, 16 +; XTENSA-ATOMIC-NEXT: srai a6, a7, 16 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a11, a6, .LBB99_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB99_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB99_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB99_2 Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a15, .LCPI99_0 +; XTENSA-ATOMIC-NEXT: and a15, a7, a15 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a15, a15 +; XTENSA-ATOMIC-NEXT: and a7, a14, a9 +; XTENSA-ATOMIC-NEXT: or a15, a7, a15 +; XTENSA-ATOMIC-NEXT: wsr a14, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a15, a10, 0 +; XTENSA-ATOMIC-NEXT: or a7, a13, a13 +; XTENSA-ATOMIC-NEXT: beq a15, a14, .LBB99_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB99_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB99_1 +; XTENSA-ATOMIC-NEXT: .LBB99_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a15 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw min ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a5, .LCPI100_1 +; XTENSA-NEXT: j .LBB100_2 +; XTENSA-NEXT: .LBB100_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB100_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB100_4 +; XTENSA-NEXT: .LBB100_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: l32r a8, .LCPI100_0 +; XTENSA-NEXT: and a9, a3, a8 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: and a8, a2, a8 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a9, a8, .LBB100_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB100_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB100_1 +; XTENSA-NEXT: .LBB100_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI100_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB100_2 +; XTENSA-ATOMIC-NEXT: .LBB100_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB100_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB100_6 +; XTENSA-ATOMIC-NEXT: .LBB100_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a14, .LCPI100_0 +; XTENSA-ATOMIC-NEXT: and a6, a3, a14 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a13 +; XTENSA-ATOMIC-NEXT: and a5, a15, a14 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a6, a5, .LBB100_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB100_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB100_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB100_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a7, a14 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a14, a14 +; XTENSA-ATOMIC-NEXT: and a15, a13, a9 +; XTENSA-ATOMIC-NEXT: or a14, a15, a14 +; XTENSA-ATOMIC-NEXT: wsr a13, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a14, a13, .LBB100_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB100_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB100_1 +; XTENSA-ATOMIC-NEXT: .LBB100_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umax ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a5, .LCPI101_1 +; XTENSA-NEXT: j .LBB101_2 +; XTENSA-NEXT: .LBB101_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB101_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB101_4 +; XTENSA-NEXT: .LBB101_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: l32r a8, .LCPI101_0 +; XTENSA-NEXT: and a9, a3, a8 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: and a8, a2, a8 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a9, a8, .LBB101_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB101_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB101_1 +; XTENSA-NEXT: .LBB101_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI101_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB101_2 +; XTENSA-ATOMIC-NEXT: .LBB101_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB101_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB101_6 +; XTENSA-ATOMIC-NEXT: .LBB101_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a14, .LCPI101_0 +; XTENSA-ATOMIC-NEXT: and a6, a3, a14 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a13 +; XTENSA-ATOMIC-NEXT: and a5, a15, a14 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a6, a5, .LBB101_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB101_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB101_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB101_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a7, a14 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a14, a14 +; XTENSA-ATOMIC-NEXT: and a15, a13, a9 +; XTENSA-ATOMIC-NEXT: or a14, a15, a14 +; XTENSA-ATOMIC-NEXT: wsr a13, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a14, a13, .LBB101_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB101_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB101_1 +; XTENSA-ATOMIC-NEXT: .LBB101_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umax ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l16ui a2, a5, 0 +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a4, .LCPI102_1 +; XTENSA-NEXT: j .LBB102_2 +; XTENSA-NEXT: .LBB102_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB102_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB102_4 +; XTENSA-NEXT: .LBB102_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: l32r a8, .LCPI102_0 +; XTENSA-NEXT: and a9, a3, a8 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: and a8, a2, a8 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a9, a8, .LBB102_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB102_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB102_1 +; XTENSA-NEXT: .LBB102_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI102_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB102_2 +; XTENSA-ATOMIC-NEXT: .LBB102_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB102_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB102_6 +; XTENSA-ATOMIC-NEXT: .LBB102_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a14, .LCPI102_0 +; XTENSA-ATOMIC-NEXT: and a6, a3, a14 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a13 +; XTENSA-ATOMIC-NEXT: and a5, a15, a14 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a6, a5, .LBB102_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB102_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB102_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB102_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a7, a14 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a14, a14 +; XTENSA-ATOMIC-NEXT: and a15, a13, a9 +; XTENSA-ATOMIC-NEXT: or a14, a15, a14 +; XTENSA-ATOMIC-NEXT: wsr a13, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a14, a13, .LBB102_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB102_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB102_1 +; XTENSA-ATOMIC-NEXT: .LBB102_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umax ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i16_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l16ui a2, a5, 0 +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a4, .LCPI103_1 +; XTENSA-NEXT: j .LBB103_2 +; XTENSA-NEXT: .LBB103_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB103_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB103_4 +; XTENSA-NEXT: .LBB103_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: l32r a8, .LCPI103_0 +; XTENSA-NEXT: and a9, a3, a8 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: and a8, a2, a8 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a9, a8, .LBB103_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB103_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB103_1 +; XTENSA-NEXT: .LBB103_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i16_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI103_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB103_2 +; XTENSA-ATOMIC-NEXT: .LBB103_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB103_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB103_6 +; XTENSA-ATOMIC-NEXT: .LBB103_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a14, .LCPI103_0 +; XTENSA-ATOMIC-NEXT: and a6, a3, a14 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a13 +; XTENSA-ATOMIC-NEXT: and a5, a15, a14 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a6, a5, .LBB103_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB103_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB103_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB103_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a7, a14 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a14, a14 +; XTENSA-ATOMIC-NEXT: and a15, a13, a9 +; XTENSA-ATOMIC-NEXT: or a14, a15, a14 +; XTENSA-ATOMIC-NEXT: wsr a13, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a14, a13, .LBB103_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB103_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB103_1 +; XTENSA-ATOMIC-NEXT: .LBB103_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umax ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a5, .LCPI104_1 +; XTENSA-NEXT: j .LBB104_2 +; XTENSA-NEXT: .LBB104_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB104_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB104_4 +; XTENSA-NEXT: .LBB104_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: l32r a8, .LCPI104_0 +; XTENSA-NEXT: and a9, a3, a8 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: and a8, a2, a8 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a9, a8, .LBB104_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB104_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB104_1 +; XTENSA-NEXT: .LBB104_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI104_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB104_2 +; XTENSA-ATOMIC-NEXT: .LBB104_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB104_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB104_6 +; XTENSA-ATOMIC-NEXT: .LBB104_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a14, .LCPI104_0 +; XTENSA-ATOMIC-NEXT: and a6, a3, a14 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a13 +; XTENSA-ATOMIC-NEXT: and a5, a15, a14 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a6, a5, .LBB104_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB104_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB104_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB104_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a7, a14 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a14, a14 +; XTENSA-ATOMIC-NEXT: and a15, a13, a9 +; XTENSA-ATOMIC-NEXT: or a14, a15, a14 +; XTENSA-ATOMIC-NEXT: wsr a13, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a14, a13, .LBB104_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB104_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB104_1 +; XTENSA-ATOMIC-NEXT: .LBB104_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umax ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i16_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a5, .LCPI105_1 +; XTENSA-NEXT: j .LBB105_2 +; XTENSA-NEXT: .LBB105_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB105_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB105_4 +; XTENSA-NEXT: .LBB105_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: l32r a8, .LCPI105_0 +; XTENSA-NEXT: and a9, a3, a8 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: and a8, a2, a8 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a9, a8, .LBB105_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB105_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB105_1 +; XTENSA-NEXT: .LBB105_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i16_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI105_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB105_2 +; XTENSA-ATOMIC-NEXT: .LBB105_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB105_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB105_6 +; XTENSA-ATOMIC-NEXT: .LBB105_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a14, .LCPI105_0 +; XTENSA-ATOMIC-NEXT: and a6, a3, a14 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a13 +; XTENSA-ATOMIC-NEXT: and a5, a15, a14 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a6, a5, .LBB105_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB105_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB105_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB105_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a7, a14 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a14, a14 +; XTENSA-ATOMIC-NEXT: and a15, a13, a9 +; XTENSA-ATOMIC-NEXT: or a14, a15, a14 +; XTENSA-ATOMIC-NEXT: wsr a13, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a14, a13, .LBB105_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB105_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB105_1 +; XTENSA-ATOMIC-NEXT: .LBB105_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umin ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i16_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a5, .LCPI106_1 +; XTENSA-NEXT: j .LBB106_2 +; XTENSA-NEXT: .LBB106_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB106_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB106_4 +; XTENSA-NEXT: .LBB106_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: l32r a8, .LCPI106_0 +; XTENSA-NEXT: and a9, a3, a8 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: and a8, a2, a8 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a9, a8, .LBB106_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB106_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB106_1 +; XTENSA-NEXT: .LBB106_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i16_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI106_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB106_2 +; XTENSA-ATOMIC-NEXT: .LBB106_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB106_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB106_6 +; XTENSA-ATOMIC-NEXT: .LBB106_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a14, .LCPI106_0 +; XTENSA-ATOMIC-NEXT: and a6, a3, a14 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a13 +; XTENSA-ATOMIC-NEXT: and a5, a15, a14 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a6, a5, .LBB106_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB106_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB106_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB106_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a7, a14 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a14, a14 +; XTENSA-ATOMIC-NEXT: and a15, a13, a9 +; XTENSA-ATOMIC-NEXT: or a14, a15, a14 +; XTENSA-ATOMIC-NEXT: wsr a13, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a14, a13, .LBB106_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB106_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB106_1 +; XTENSA-ATOMIC-NEXT: .LBB106_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umin ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i16_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l16ui a2, a5, 0 +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a4, .LCPI107_1 +; XTENSA-NEXT: j .LBB107_2 +; XTENSA-NEXT: .LBB107_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB107_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB107_4 +; XTENSA-NEXT: .LBB107_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: l32r a8, .LCPI107_0 +; XTENSA-NEXT: and a9, a3, a8 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: and a8, a2, a8 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a9, a8, .LBB107_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB107_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB107_1 +; XTENSA-NEXT: .LBB107_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i16_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI107_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB107_2 +; XTENSA-ATOMIC-NEXT: .LBB107_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB107_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB107_6 +; XTENSA-ATOMIC-NEXT: .LBB107_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a14, .LCPI107_0 +; XTENSA-ATOMIC-NEXT: and a6, a3, a14 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a13 +; XTENSA-ATOMIC-NEXT: and a5, a15, a14 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a6, a5, .LBB107_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB107_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB107_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB107_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a7, a14 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a14, a14 +; XTENSA-ATOMIC-NEXT: and a15, a13, a9 +; XTENSA-ATOMIC-NEXT: or a14, a15, a14 +; XTENSA-ATOMIC-NEXT: wsr a13, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a14, a13, .LBB107_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB107_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB107_1 +; XTENSA-ATOMIC-NEXT: .LBB107_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umin ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i16_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l16ui a2, a5, 0 +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a4, .LCPI108_1 +; XTENSA-NEXT: j .LBB108_2 +; XTENSA-NEXT: .LBB108_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB108_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB108_4 +; XTENSA-NEXT: .LBB108_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: l32r a8, .LCPI108_0 +; XTENSA-NEXT: and a9, a3, a8 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: and a8, a2, a8 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a9, a8, .LBB108_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB108_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB108_1 +; XTENSA-NEXT: .LBB108_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i16_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI108_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB108_2 +; XTENSA-ATOMIC-NEXT: .LBB108_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB108_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB108_6 +; XTENSA-ATOMIC-NEXT: .LBB108_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a14, .LCPI108_0 +; XTENSA-ATOMIC-NEXT: and a6, a3, a14 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a13 +; XTENSA-ATOMIC-NEXT: and a5, a15, a14 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a6, a5, .LBB108_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB108_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB108_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB108_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a7, a14 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a14, a14 +; XTENSA-ATOMIC-NEXT: and a15, a13, a9 +; XTENSA-ATOMIC-NEXT: or a14, a15, a14 +; XTENSA-ATOMIC-NEXT: wsr a13, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a14, a13, .LBB108_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB108_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB108_1 +; XTENSA-ATOMIC-NEXT: .LBB108_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umin ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i16_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l16ui a2, a6, 0 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a5, .LCPI109_1 +; XTENSA-NEXT: j .LBB109_2 +; XTENSA-NEXT: .LBB109_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB109_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l16ui a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB109_4 +; XTENSA-NEXT: .LBB109_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: l32r a8, .LCPI109_0 +; XTENSA-NEXT: and a9, a3, a8 +; XTENSA-NEXT: s16i a2, a1, 0 +; XTENSA-NEXT: and a8, a2, a8 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a9, a8, .LBB109_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB109_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB109_1 +; XTENSA-NEXT: .LBB109_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i16_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: l32r a9, .LCPI109_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a9, a9 +; XTENSA-ATOMIC-NEXT: movi a10, -1 +; XTENSA-ATOMIC-NEXT: xor a9, a9, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -4 +; XTENSA-ATOMIC-NEXT: and a10, a2, a10 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a13, a10, 0 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB109_2 +; XTENSA-ATOMIC-NEXT: .LBB109_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB109_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a14, a14 +; XTENSA-ATOMIC-NEXT: beqi a15, 1, .LBB109_6 +; XTENSA-ATOMIC-NEXT: .LBB109_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: l32r a14, .LCPI109_0 +; XTENSA-ATOMIC-NEXT: and a6, a3, a14 +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a15, a13 +; XTENSA-ATOMIC-NEXT: and a5, a15, a14 +; XTENSA-ATOMIC-NEXT: or a7, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a6, a5, .LBB109_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB109_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a7, a15, a15 +; XTENSA-ATOMIC-NEXT: .LBB109_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB109_2 Depth=1 +; XTENSA-ATOMIC-NEXT: and a14, a7, a14 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a14, a14 +; XTENSA-ATOMIC-NEXT: and a15, a13, a9 +; XTENSA-ATOMIC-NEXT: or a14, a15, a14 +; XTENSA-ATOMIC-NEXT: wsr a13, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a14, a10, 0 +; XTENSA-ATOMIC-NEXT: or a15, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a14, a13, .LBB109_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB109_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB109_1 +; XTENSA-ATOMIC-NEXT: .LBB109_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a14 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umin ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI110_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB110_2 +; XTENSA-ATOMIC-NEXT: .LBB110_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB110_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB110_4 +; XTENSA-ATOMIC-NEXT: .LBB110_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB110_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB110_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB110_1 +; XTENSA-ATOMIC-NEXT: .LBB110_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw xchg ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI111_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB111_2 +; XTENSA-ATOMIC-NEXT: .LBB111_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB111_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB111_4 +; XTENSA-ATOMIC-NEXT: .LBB111_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB111_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB111_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB111_1 +; XTENSA-ATOMIC-NEXT: .LBB111_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw xchg ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI112_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB112_2 +; XTENSA-ATOMIC-NEXT: .LBB112_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB112_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB112_4 +; XTENSA-ATOMIC-NEXT: .LBB112_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB112_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB112_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB112_1 +; XTENSA-ATOMIC-NEXT: .LBB112_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw xchg ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI113_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB113_2 +; XTENSA-ATOMIC-NEXT: .LBB113_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB113_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB113_4 +; XTENSA-ATOMIC-NEXT: .LBB113_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB113_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB113_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB113_1 +; XTENSA-ATOMIC-NEXT: .LBB113_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw xchg ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_xchg_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI114_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB114_2 +; XTENSA-ATOMIC-NEXT: .LBB114_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB114_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB114_4 +; XTENSA-ATOMIC-NEXT: .LBB114_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB114_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB114_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB114_1 +; XTENSA-ATOMIC-NEXT: .LBB114_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw xchg ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI115_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB115_2 +; XTENSA-ATOMIC-NEXT: .LBB115_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB115_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB115_4 +; XTENSA-ATOMIC-NEXT: .LBB115_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: add a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB115_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB115_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB115_1 +; XTENSA-ATOMIC-NEXT: .LBB115_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw add ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI116_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB116_2 +; XTENSA-ATOMIC-NEXT: .LBB116_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB116_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB116_4 +; XTENSA-ATOMIC-NEXT: .LBB116_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: add a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB116_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB116_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB116_1 +; XTENSA-ATOMIC-NEXT: .LBB116_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw add ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI117_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB117_2 +; XTENSA-ATOMIC-NEXT: .LBB117_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB117_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB117_4 +; XTENSA-ATOMIC-NEXT: .LBB117_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: add a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB117_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB117_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB117_1 +; XTENSA-ATOMIC-NEXT: .LBB117_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw add ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI118_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB118_2 +; XTENSA-ATOMIC-NEXT: .LBB118_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB118_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB118_4 +; XTENSA-ATOMIC-NEXT: .LBB118_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: add a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB118_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB118_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB118_1 +; XTENSA-ATOMIC-NEXT: .LBB118_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw add ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_add_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI119_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB119_2 +; XTENSA-ATOMIC-NEXT: .LBB119_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB119_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB119_4 +; XTENSA-ATOMIC-NEXT: .LBB119_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: add a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB119_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB119_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB119_1 +; XTENSA-ATOMIC-NEXT: .LBB119_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw add ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI120_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB120_2 +; XTENSA-ATOMIC-NEXT: .LBB120_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB120_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB120_4 +; XTENSA-ATOMIC-NEXT: .LBB120_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: sub a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB120_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB120_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB120_1 +; XTENSA-ATOMIC-NEXT: .LBB120_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw sub ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI121_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB121_2 +; XTENSA-ATOMIC-NEXT: .LBB121_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB121_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB121_4 +; XTENSA-ATOMIC-NEXT: .LBB121_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: sub a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB121_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB121_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB121_1 +; XTENSA-ATOMIC-NEXT: .LBB121_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw sub ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI122_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB122_2 +; XTENSA-ATOMIC-NEXT: .LBB122_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB122_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB122_4 +; XTENSA-ATOMIC-NEXT: .LBB122_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: sub a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB122_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB122_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB122_1 +; XTENSA-ATOMIC-NEXT: .LBB122_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw sub ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI123_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB123_2 +; XTENSA-ATOMIC-NEXT: .LBB123_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB123_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB123_4 +; XTENSA-ATOMIC-NEXT: .LBB123_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: sub a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB123_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB123_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB123_1 +; XTENSA-ATOMIC-NEXT: .LBB123_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw sub ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_sub_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI124_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB124_2 +; XTENSA-ATOMIC-NEXT: .LBB124_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB124_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB124_4 +; XTENSA-ATOMIC-NEXT: .LBB124_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: sub a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB124_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB124_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB124_1 +; XTENSA-ATOMIC-NEXT: .LBB124_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw sub ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 0 +; XTENSA-NEXT: l32r a8, .LCPI125_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB125_2 +; XTENSA-ATOMIC-NEXT: .LBB125_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB125_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB125_4 +; XTENSA-ATOMIC-NEXT: .LBB125_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB125_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB125_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB125_1 +; XTENSA-ATOMIC-NEXT: .LBB125_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw and ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 2 +; XTENSA-NEXT: l32r a8, .LCPI126_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB126_2 +; XTENSA-ATOMIC-NEXT: .LBB126_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB126_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB126_4 +; XTENSA-ATOMIC-NEXT: .LBB126_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB126_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB126_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB126_1 +; XTENSA-ATOMIC-NEXT: .LBB126_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw and ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 3 +; XTENSA-NEXT: l32r a8, .LCPI127_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB127_2 +; XTENSA-ATOMIC-NEXT: .LBB127_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB127_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB127_4 +; XTENSA-ATOMIC-NEXT: .LBB127_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB127_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB127_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB127_1 +; XTENSA-ATOMIC-NEXT: .LBB127_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw and ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 4 +; XTENSA-NEXT: l32r a8, .LCPI128_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB128_2 +; XTENSA-ATOMIC-NEXT: .LBB128_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB128_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB128_4 +; XTENSA-ATOMIC-NEXT: .LBB128_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB128_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB128_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB128_1 +; XTENSA-ATOMIC-NEXT: .LBB128_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw and ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_and_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: or a11, a3, a3 +; XTENSA-NEXT: or a10, a2, a2 +; XTENSA-NEXT: movi a12, 5 +; XTENSA-NEXT: l32r a8, .LCPI129_0 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: or a2, a10, a10 +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB129_2 +; XTENSA-ATOMIC-NEXT: .LBB129_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB129_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB129_4 +; XTENSA-ATOMIC-NEXT: .LBB129_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB129_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB129_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB129_1 +; XTENSA-ATOMIC-NEXT: .LBB129_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw and ptr %a, i32 %b seq_cst + ret i32 %res +} + +;define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { +; %res = atomicrmw nand ptr %a, i32 %b monotonic +; ret i32 %res +;} +; +;define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { +; %res = atomicrmw nand ptr %a, i32 %b acquire +; ret i32 %res +;} +; +;define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { +; %res = atomicrmw nand ptr %a, i32 %b release +; ret i32 %res +;} ; ;define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw nand ptr %a, i32 %b acq_rel -; ret i32 %1 +; %res = atomicrmw nand ptr %a, i32 %b acq_rel +; ret i32 %res ;} ; ;define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw nand ptr %a, i32 %b seq_cst -; ret i32 %1 +; %res = atomicrmw nand ptr %a, i32 %b seq_cst +; ret i32 %res ;} define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { @@ -4322,7 +8550,7 @@ define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a11, a3, a3 ; XTENSA-NEXT: or a10, a2, a2 ; XTENSA-NEXT: movi a12, 0 -; XTENSA-NEXT: l32r a8, .LCPI90_0 +; XTENSA-NEXT: l32r a8, .LCPI130_0 ; XTENSA-NEXT: callx8 a8 ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw @@ -4330,19 +8558,30 @@ define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: or a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB130_2 +; XTENSA-ATOMIC-NEXT: .LBB130_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB130_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB130_4 +; XTENSA-ATOMIC-NEXT: .LBB130_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB90_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB130_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB130_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB130_1 +; XTENSA-ATOMIC-NEXT: .LBB130_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i32 %b monotonic - ret i32 %1 + %res = atomicrmw or ptr %a, i32 %b monotonic + ret i32 %res } define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind { @@ -4352,7 +8591,7 @@ define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a11, a3, a3 ; XTENSA-NEXT: or a10, a2, a2 ; XTENSA-NEXT: movi a12, 2 -; XTENSA-NEXT: l32r a8, .LCPI91_0 +; XTENSA-NEXT: l32r a8, .LCPI131_0 ; XTENSA-NEXT: callx8 a8 ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw @@ -4360,20 +8599,31 @@ define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: or a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB131_2 +; XTENSA-ATOMIC-NEXT: .LBB131_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB131_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB131_4 +; XTENSA-ATOMIC-NEXT: .LBB131_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB91_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB131_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB131_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB131_1 +; XTENSA-ATOMIC-NEXT: .LBB131_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i32 %b acquire - ret i32 %1 + %res = atomicrmw or ptr %a, i32 %b acquire + ret i32 %res } define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind { @@ -4383,7 +8633,7 @@ define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a11, a3, a3 ; XTENSA-NEXT: or a10, a2, a2 ; XTENSA-NEXT: movi a12, 3 -; XTENSA-NEXT: l32r a8, .LCPI92_0 +; XTENSA-NEXT: l32r a8, .LCPI132_0 ; XTENSA-NEXT: callx8 a8 ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw @@ -4392,19 +8642,30 @@ define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: or a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB132_2 +; XTENSA-ATOMIC-NEXT: .LBB132_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB132_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB132_4 +; XTENSA-ATOMIC-NEXT: .LBB132_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB92_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB132_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB132_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB132_1 +; XTENSA-ATOMIC-NEXT: .LBB132_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i32 %b release - ret i32 %1 + %res = atomicrmw or ptr %a, i32 %b release + ret i32 %res } define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind { @@ -4414,7 +8675,7 @@ define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a11, a3, a3 ; XTENSA-NEXT: or a10, a2, a2 ; XTENSA-NEXT: movi a12, 4 -; XTENSA-NEXT: l32r a8, .LCPI93_0 +; XTENSA-NEXT: l32r a8, .LCPI133_0 ; XTENSA-NEXT: callx8 a8 ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw @@ -4423,20 +8684,31 @@ define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: or a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB133_2 +; XTENSA-ATOMIC-NEXT: .LBB133_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB133_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB133_4 +; XTENSA-ATOMIC-NEXT: .LBB133_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB93_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB133_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB133_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB133_1 +; XTENSA-ATOMIC-NEXT: .LBB133_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i32 %b acq_rel - ret i32 %1 + %res = atomicrmw or ptr %a, i32 %b acq_rel + ret i32 %res } define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind { @@ -4446,7 +8718,7 @@ define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a11, a3, a3 ; XTENSA-NEXT: or a10, a2, a2 ; XTENSA-NEXT: movi a12, 5 -; XTENSA-NEXT: l32r a8, .LCPI94_0 +; XTENSA-NEXT: l32r a8, .LCPI134_0 ; XTENSA-NEXT: callx8 a8 ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw @@ -4455,20 +8727,31 @@ define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: or a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB134_2 +; XTENSA-ATOMIC-NEXT: .LBB134_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB134_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB134_4 +; XTENSA-ATOMIC-NEXT: .LBB134_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB94_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB134_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB134_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB134_1 +; XTENSA-ATOMIC-NEXT: .LBB134_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw or ptr %a, i32 %b seq_cst - ret i32 %1 + %res = atomicrmw or ptr %a, i32 %b seq_cst + ret i32 %res } define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { @@ -4478,7 +8761,7 @@ define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a11, a3, a3 ; XTENSA-NEXT: or a10, a2, a2 ; XTENSA-NEXT: movi a12, 0 -; XTENSA-NEXT: l32r a8, .LCPI95_0 +; XTENSA-NEXT: l32r a8, .LCPI135_0 ; XTENSA-NEXT: callx8 a8 ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw @@ -4486,19 +8769,30 @@ define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: xor a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB135_2 +; XTENSA-ATOMIC-NEXT: .LBB135_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB135_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB135_4 +; XTENSA-ATOMIC-NEXT: .LBB135_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB95_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB135_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB135_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB135_1 +; XTENSA-ATOMIC-NEXT: .LBB135_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i32 %b monotonic - ret i32 %1 + %res = atomicrmw xor ptr %a, i32 %b monotonic + ret i32 %res } define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind { @@ -4508,7 +8802,7 @@ define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a11, a3, a3 ; XTENSA-NEXT: or a10, a2, a2 ; XTENSA-NEXT: movi a12, 2 -; XTENSA-NEXT: l32r a8, .LCPI96_0 +; XTENSA-NEXT: l32r a8, .LCPI136_0 ; XTENSA-NEXT: callx8 a8 ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw @@ -4516,20 +8810,31 @@ define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind { ; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_acquire: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: xor a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB136_2 +; XTENSA-ATOMIC-NEXT: .LBB136_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB136_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB136_4 +; XTENSA-ATOMIC-NEXT: .LBB136_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB96_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB136_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB136_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB136_1 +; XTENSA-ATOMIC-NEXT: .LBB136_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i32 %b acquire - ret i32 %1 + %res = atomicrmw xor ptr %a, i32 %b acquire + ret i32 %res } define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind { @@ -4539,7 +8844,7 @@ define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a11, a3, a3 ; XTENSA-NEXT: or a10, a2, a2 ; XTENSA-NEXT: movi a12, 3 -; XTENSA-NEXT: l32r a8, .LCPI97_0 +; XTENSA-NEXT: l32r a8, .LCPI137_0 ; XTENSA-NEXT: callx8 a8 ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw @@ -4548,19 +8853,30 @@ define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: xor a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB137_2 +; XTENSA-ATOMIC-NEXT: .LBB137_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB137_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB137_4 +; XTENSA-ATOMIC-NEXT: .LBB137_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB97_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB137_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB137_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB137_1 +; XTENSA-ATOMIC-NEXT: .LBB137_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i32 %b release - ret i32 %1 + %res = atomicrmw xor ptr %a, i32 %b release + ret i32 %res } define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { @@ -4570,7 +8886,7 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a11, a3, a3 ; XTENSA-NEXT: or a10, a2, a2 ; XTENSA-NEXT: movi a12, 4 -; XTENSA-NEXT: l32r a8, .LCPI98_0 +; XTENSA-NEXT: l32r a8, .LCPI138_0 ; XTENSA-NEXT: callx8 a8 ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw @@ -4579,20 +8895,31 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: xor a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB138_2 +; XTENSA-ATOMIC-NEXT: .LBB138_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB138_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB138_4 +; XTENSA-ATOMIC-NEXT: .LBB138_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB98_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB138_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB138_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB138_1 +; XTENSA-ATOMIC-NEXT: .LBB138_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i32 %b acq_rel - ret i32 %1 + %res = atomicrmw xor ptr %a, i32 %b acq_rel + ret i32 %res } define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind { @@ -4602,7 +8929,7 @@ define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind { ; XTENSA-NEXT: or a11, a3, a3 ; XTENSA-NEXT: or a10, a2, a2 ; XTENSA-NEXT: movi a12, 5 -; XTENSA-NEXT: l32r a8, .LCPI99_0 +; XTENSA-NEXT: l32r a8, .LCPI139_0 ; XTENSA-NEXT: callx8 a8 ; XTENSA-NEXT: or a2, a10, a10 ; XTENSA-NEXT: retw @@ -4611,118 +8938,1361 @@ define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: xor a8, a10, a3 -; XTENSA-ATOMIC-NEXT: wsr a10, scompare1 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB139_2 +; XTENSA-ATOMIC-NEXT: .LBB139_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB139_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB139_4 +; XTENSA-ATOMIC-NEXT: .LBB139_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a8, a11, a3 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a9, a8 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB99_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a8 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB139_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB139_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB139_1 +; XTENSA-ATOMIC-NEXT: .LBB139_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw - %1 = atomicrmw xor ptr %a, i32 %b seq_cst - ret i32 %1 + %res = atomicrmw xor ptr %a, i32 %b seq_cst + ret i32 %res } -;define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw max ptr %a, i32 %b monotonic -; ret i32 %1 -;} +define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a5, .LCPI140_0 +; XTENSA-NEXT: j .LBB140_2 +; XTENSA-NEXT: .LBB140_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB140_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB140_4 +; XTENSA-NEXT: .LBB140_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bge a3, a2, .LBB140_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB140_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB140_1 +; XTENSA-NEXT: .LBB140_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw max ptr %a, i32 %b acquire -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB140_2 +; XTENSA-ATOMIC-NEXT: .LBB140_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB140_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB140_6 +; XTENSA-ATOMIC-NEXT: .LBB140_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a3, a11, .LBB140_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB140_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB140_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB140_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB140_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB140_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB140_1 +; XTENSA-ATOMIC-NEXT: .LBB140_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw max ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a5, .LCPI141_0 +; XTENSA-NEXT: j .LBB141_2 +; XTENSA-NEXT: .LBB141_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB141_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB141_4 +; XTENSA-NEXT: .LBB141_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bge a3, a2, .LBB141_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB141_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB141_1 +; XTENSA-NEXT: .LBB141_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw max ptr %a, i32 %b release -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB141_2 +; XTENSA-ATOMIC-NEXT: .LBB141_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB141_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB141_6 +; XTENSA-ATOMIC-NEXT: .LBB141_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a3, a11, .LBB141_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB141_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB141_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB141_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB141_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB141_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB141_1 +; XTENSA-ATOMIC-NEXT: .LBB141_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw max ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l32i a2, a5, 0 +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a4, .LCPI142_0 +; XTENSA-NEXT: j .LBB142_2 +; XTENSA-NEXT: .LBB142_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB142_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB142_4 +; XTENSA-NEXT: .LBB142_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bge a3, a2, .LBB142_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB142_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB142_1 +; XTENSA-NEXT: .LBB142_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw max ptr %a, i32 %b acq_rel -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB142_2 +; XTENSA-ATOMIC-NEXT: .LBB142_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB142_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB142_6 +; XTENSA-ATOMIC-NEXT: .LBB142_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a3, a11, .LBB142_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB142_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB142_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB142_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB142_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB142_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB142_1 +; XTENSA-ATOMIC-NEXT: .LBB142_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw max ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l32i a2, a5, 0 +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a4, .LCPI143_0 +; XTENSA-NEXT: j .LBB143_2 +; XTENSA-NEXT: .LBB143_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB143_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB143_4 +; XTENSA-NEXT: .LBB143_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bge a3, a2, .LBB143_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB143_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB143_1 +; XTENSA-NEXT: .LBB143_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw max ptr %a, i32 %b seq_cst -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB143_2 +; XTENSA-ATOMIC-NEXT: .LBB143_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB143_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB143_6 +; XTENSA-ATOMIC-NEXT: .LBB143_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a3, a11, .LBB143_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB143_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB143_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB143_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB143_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB143_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB143_1 +; XTENSA-ATOMIC-NEXT: .LBB143_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw max ptr %a, i32 %b acq_rel + ret i32 %res +} -;define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw min ptr %a, i32 %b monotonic -; ret i32 %1 -;} +define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_max_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a5, .LCPI144_0 +; XTENSA-NEXT: j .LBB144_2 +; XTENSA-NEXT: .LBB144_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB144_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB144_4 +; XTENSA-NEXT: .LBB144_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bge a3, a2, .LBB144_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB144_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB144_1 +; XTENSA-NEXT: .LBB144_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw min ptr %a, i32 %b acquire -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_max_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB144_2 +; XTENSA-ATOMIC-NEXT: .LBB144_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB144_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB144_6 +; XTENSA-ATOMIC-NEXT: .LBB144_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bge a3, a11, .LBB144_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB144_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB144_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB144_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB144_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB144_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB144_1 +; XTENSA-ATOMIC-NEXT: .LBB144_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw max ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a5, .LCPI145_0 +; XTENSA-NEXT: j .LBB145_2 +; XTENSA-NEXT: .LBB145_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB145_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB145_4 +; XTENSA-NEXT: .LBB145_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: blt a3, a2, .LBB145_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB145_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB145_1 +; XTENSA-NEXT: .LBB145_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw min ptr %a, i32 %b release -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB145_2 +; XTENSA-ATOMIC-NEXT: .LBB145_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB145_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB145_6 +; XTENSA-ATOMIC-NEXT: .LBB145_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a3, a11, .LBB145_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB145_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB145_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB145_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB145_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB145_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB145_1 +; XTENSA-ATOMIC-NEXT: .LBB145_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw min ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a5, .LCPI146_0 +; XTENSA-NEXT: j .LBB146_2 +; XTENSA-NEXT: .LBB146_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB146_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB146_4 +; XTENSA-NEXT: .LBB146_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: blt a3, a2, .LBB146_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB146_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB146_1 +; XTENSA-NEXT: .LBB146_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw min ptr %a, i32 %b acq_rel -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB146_2 +; XTENSA-ATOMIC-NEXT: .LBB146_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB146_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB146_6 +; XTENSA-ATOMIC-NEXT: .LBB146_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a3, a11, .LBB146_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB146_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB146_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB146_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB146_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB146_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB146_1 +; XTENSA-ATOMIC-NEXT: .LBB146_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw min ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l32i a2, a5, 0 +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a4, .LCPI147_0 +; XTENSA-NEXT: j .LBB147_2 +; XTENSA-NEXT: .LBB147_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB147_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB147_4 +; XTENSA-NEXT: .LBB147_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: blt a3, a2, .LBB147_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB147_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB147_1 +; XTENSA-NEXT: .LBB147_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw min ptr %a, i32 %b seq_cst -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB147_2 +; XTENSA-ATOMIC-NEXT: .LBB147_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB147_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB147_6 +; XTENSA-ATOMIC-NEXT: .LBB147_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a3, a11, .LBB147_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB147_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB147_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB147_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB147_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB147_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB147_1 +; XTENSA-ATOMIC-NEXT: .LBB147_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw min ptr %a, i32 %b release + ret i32 %res +} -;define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i32 %b monotonic -; ret i32 %1 -;} +define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l32i a2, a5, 0 +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a4, .LCPI148_0 +; XTENSA-NEXT: j .LBB148_2 +; XTENSA-NEXT: .LBB148_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB148_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB148_4 +; XTENSA-NEXT: .LBB148_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: blt a3, a2, .LBB148_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB148_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB148_1 +; XTENSA-NEXT: .LBB148_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i32 %b acquire -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB148_2 +; XTENSA-ATOMIC-NEXT: .LBB148_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB148_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB148_6 +; XTENSA-ATOMIC-NEXT: .LBB148_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a3, a11, .LBB148_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB148_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB148_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB148_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB148_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB148_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB148_1 +; XTENSA-ATOMIC-NEXT: .LBB148_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw min ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_min_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a5, .LCPI149_0 +; XTENSA-NEXT: j .LBB149_2 +; XTENSA-NEXT: .LBB149_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB149_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB149_4 +; XTENSA-NEXT: .LBB149_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: blt a3, a2, .LBB149_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB149_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB149_1 +; XTENSA-NEXT: .LBB149_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i32 %b release -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_min_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB149_2 +; XTENSA-ATOMIC-NEXT: .LBB149_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB149_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB149_6 +; XTENSA-ATOMIC-NEXT: .LBB149_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: blt a3, a11, .LBB149_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB149_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB149_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB149_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB149_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB149_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB149_1 +; XTENSA-ATOMIC-NEXT: .LBB149_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw min ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a5, .LCPI150_0 +; XTENSA-NEXT: j .LBB150_2 +; XTENSA-NEXT: .LBB150_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB150_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB150_4 +; XTENSA-NEXT: .LBB150_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a3, a2, .LBB150_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB150_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB150_1 +; XTENSA-NEXT: .LBB150_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i32 %b acq_rel -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB150_2 +; XTENSA-ATOMIC-NEXT: .LBB150_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB150_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB150_6 +; XTENSA-ATOMIC-NEXT: .LBB150_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a3, a11, .LBB150_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB150_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB150_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB150_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB150_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB150_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB150_1 +; XTENSA-ATOMIC-NEXT: .LBB150_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umax ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a5, .LCPI151_0 +; XTENSA-NEXT: j .LBB151_2 +; XTENSA-NEXT: .LBB151_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB151_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB151_4 +; XTENSA-NEXT: .LBB151_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a3, a2, .LBB151_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB151_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB151_1 +; XTENSA-NEXT: .LBB151_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw umax ptr %a, i32 %b seq_cst -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB151_2 +; XTENSA-ATOMIC-NEXT: .LBB151_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB151_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB151_6 +; XTENSA-ATOMIC-NEXT: .LBB151_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a3, a11, .LBB151_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB151_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB151_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB151_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB151_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB151_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB151_1 +; XTENSA-ATOMIC-NEXT: .LBB151_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umax ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l32i a2, a5, 0 +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a4, .LCPI152_0 +; XTENSA-NEXT: j .LBB152_2 +; XTENSA-NEXT: .LBB152_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB152_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB152_4 +; XTENSA-NEXT: .LBB152_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a3, a2, .LBB152_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB152_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB152_1 +; XTENSA-NEXT: .LBB152_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i32 %b monotonic -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB152_2 +; XTENSA-ATOMIC-NEXT: .LBB152_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB152_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB152_6 +; XTENSA-ATOMIC-NEXT: .LBB152_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a3, a11, .LBB152_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB152_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB152_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB152_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB152_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB152_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB152_1 +; XTENSA-ATOMIC-NEXT: .LBB152_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umax ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l32i a2, a5, 0 +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a4, .LCPI153_0 +; XTENSA-NEXT: j .LBB153_2 +; XTENSA-NEXT: .LBB153_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB153_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB153_4 +; XTENSA-NEXT: .LBB153_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a3, a2, .LBB153_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB153_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB153_1 +; XTENSA-NEXT: .LBB153_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i32 %b acquire -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB153_2 +; XTENSA-ATOMIC-NEXT: .LBB153_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB153_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB153_6 +; XTENSA-ATOMIC-NEXT: .LBB153_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a3, a11, .LBB153_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB153_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB153_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB153_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB153_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB153_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB153_1 +; XTENSA-ATOMIC-NEXT: .LBB153_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umax ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umax_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a5, .LCPI154_0 +; XTENSA-NEXT: j .LBB154_2 +; XTENSA-NEXT: .LBB154_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB154_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB154_4 +; XTENSA-NEXT: .LBB154_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bgeu a3, a2, .LBB154_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB154_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB154_1 +; XTENSA-NEXT: .LBB154_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i32 %b release -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_umax_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB154_2 +; XTENSA-ATOMIC-NEXT: .LBB154_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB154_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB154_6 +; XTENSA-ATOMIC-NEXT: .LBB154_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bgeu a3, a11, .LBB154_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB154_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB154_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB154_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB154_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB154_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB154_1 +; XTENSA-ATOMIC-NEXT: .LBB154_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umax ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i32_monotonic: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 0 +; XTENSA-NEXT: l32r a5, .LCPI155_0 +; XTENSA-NEXT: j .LBB155_2 +; XTENSA-NEXT: .LBB155_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB155_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB155_4 +; XTENSA-NEXT: .LBB155_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a3, a2, .LBB155_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB155_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB155_1 +; XTENSA-NEXT: .LBB155_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i32 %b acq_rel -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i32_monotonic: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB155_2 +; XTENSA-ATOMIC-NEXT: .LBB155_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB155_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB155_6 +; XTENSA-ATOMIC-NEXT: .LBB155_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a3, a11, .LBB155_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB155_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB155_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB155_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB155_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB155_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB155_1 +; XTENSA-ATOMIC-NEXT: .LBB155_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umin ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i32_acquire: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 2 +; XTENSA-NEXT: l32r a5, .LCPI156_0 +; XTENSA-NEXT: j .LBB156_2 +; XTENSA-NEXT: .LBB156_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB156_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB156_4 +; XTENSA-NEXT: .LBB156_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a3, a2, .LBB156_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB156_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB156_1 +; XTENSA-NEXT: .LBB156_4: # %atomicrmw.end +; XTENSA-NEXT: retw ; -;define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind { -; %1 = atomicrmw umin ptr %a, i32 %b seq_cst -; ret i32 %1 -;} +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i32_acquire: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB156_2 +; XTENSA-ATOMIC-NEXT: .LBB156_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB156_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB156_6 +; XTENSA-ATOMIC-NEXT: .LBB156_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a3, a11, .LBB156_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB156_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB156_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB156_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB156_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB156_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB156_1 +; XTENSA-ATOMIC-NEXT: .LBB156_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umin ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i32_release: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l32i a2, a5, 0 +; XTENSA-NEXT: movi a7, 3 +; XTENSA-NEXT: movi a6, 0 +; XTENSA-NEXT: l32r a4, .LCPI157_0 +; XTENSA-NEXT: j .LBB157_2 +; XTENSA-NEXT: .LBB157_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB157_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB157_4 +; XTENSA-NEXT: .LBB157_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a3, a2, .LBB157_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB157_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB157_1 +; XTENSA-NEXT: .LBB157_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i32_release: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB157_2 +; XTENSA-ATOMIC-NEXT: .LBB157_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB157_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB157_6 +; XTENSA-ATOMIC-NEXT: .LBB157_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a3, a11, .LBB157_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB157_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB157_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB157_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB157_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB157_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB157_1 +; XTENSA-ATOMIC-NEXT: .LBB157_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umin ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i32_acq_rel: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a5, a2, a2 +; XTENSA-NEXT: l32i a2, a5, 0 +; XTENSA-NEXT: movi a7, 4 +; XTENSA-NEXT: movi a6, 2 +; XTENSA-NEXT: l32r a4, .LCPI158_0 +; XTENSA-NEXT: j .LBB158_2 +; XTENSA-NEXT: .LBB158_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB158_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a5, a5 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a6, a6 +; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB158_4 +; XTENSA-NEXT: .LBB158_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a3, a2, .LBB158_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB158_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB158_1 +; XTENSA-NEXT: .LBB158_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i32_acq_rel: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB158_2 +; XTENSA-ATOMIC-NEXT: .LBB158_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB158_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB158_6 +; XTENSA-ATOMIC-NEXT: .LBB158_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a3, a11, .LBB158_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB158_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB158_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB158_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB158_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB158_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB158_1 +; XTENSA-ATOMIC-NEXT: .LBB158_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umin ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind { +; XTENSA-LABEL: atomicrmw_umin_i32_seq_cst: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 48 +; XTENSA-NEXT: or a6, a2, a2 +; XTENSA-NEXT: l32i a2, a6, 0 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a5, .LCPI159_0 +; XTENSA-NEXT: j .LBB159_2 +; XTENSA-NEXT: .LBB159_1: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB159_2 Depth=1 +; XTENSA-NEXT: addi a11, a1, 0 +; XTENSA-NEXT: or a10, a6, a6 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32i a2, a1, 0 +; XTENSA-NEXT: bnez a10, .LBB159_4 +; XTENSA-NEXT: .LBB159_2: # %atomicrmw.start +; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-NEXT: s32i a2, a1, 0 +; XTENSA-NEXT: or a12, a3, a3 +; XTENSA-NEXT: bltu a3, a2, .LBB159_1 +; XTENSA-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-NEXT: # in Loop: Header=BB159_2 Depth=1 +; XTENSA-NEXT: or a12, a2, a2 +; XTENSA-NEXT: j .LBB159_1 +; XTENSA-NEXT: .LBB159_4: # %atomicrmw.end +; XTENSA-NEXT: retw +; +; XTENSA-ATOMIC-LABEL: atomicrmw_umin_i32_seq_cst: +; XTENSA-ATOMIC: # %bb.0: +; XTENSA-ATOMIC-NEXT: entry a1, 32 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB159_2 +; XTENSA-ATOMIC-NEXT: .LBB159_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB159_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB159_6 +; XTENSA-ATOMIC-NEXT: .LBB159_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a3, a3 +; XTENSA-ATOMIC-NEXT: bltu a3, a11, .LBB159_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB159_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB159_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB159_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB159_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB159_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB159_1 +; XTENSA-ATOMIC-NEXT: .LBB159_6: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 +; XTENSA-ATOMIC-NEXT: retw + %res = atomicrmw umin ptr %a, i32 %b seq_cst + ret i32 %res +} diff --git a/llvm/test/CodeGen/Xtensa/forced-atomics.ll b/llvm/test/CodeGen/Xtensa/forced-atomics.ll index f803f90d23073..41a1fbcf50586 100644 --- a/llvm/test/CodeGen/Xtensa/forced-atomics.ll +++ b/llvm/test/CodeGen/Xtensa/forced-atomics.ll @@ -61,34 +61,44 @@ define i8 @rmw8(ptr %p) nounwind { ; XTENSA-ATOMIC-LABEL: rmw8: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a13, 1 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a9, a8, 3 -; XTENSA-ATOMIC-NEXT: movi a8, 255 -; XTENSA-ATOMIC-NEXT: ssl a9 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 1 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: movi a11, 255 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a11, a11 ; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a8 ; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a13 -; XTENSA-ATOMIC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: j .LBB2_2 +; XTENSA-ATOMIC-NEXT: .LBB2_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB2_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB2_4 +; XTENSA-ATOMIC-NEXT: .LBB2_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: add a6, a15, a10 +; XTENSA-ATOMIC-NEXT: and a6, a6, a11 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB2_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: ssr a9 -; XTENSA-ATOMIC-NEXT: srl a9, a14 -; XTENSA-ATOMIC-NEXT: and a2, a9, a8 +; XTENSA-ATOMIC-NEXT: s32c1i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: or a6, a9, a9 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB2_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB2_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB2_1 +; XTENSA-ATOMIC-NEXT: .LBB2_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: ssr a8 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw add ptr %p, i8 1 seq_cst, align 1 @@ -218,35 +228,44 @@ define i16 @rmw16(ptr %p) nounwind { ; XTENSA-ATOMIC-LABEL: rmw16: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a13, 1 -; XTENSA-ATOMIC-NEXT: movi a8, 3 -; XTENSA-ATOMIC-NEXT: and a8, a8, a2 -; XTENSA-ATOMIC-NEXT: sub a10, a2, a8 -; XTENSA-ATOMIC-NEXT: slli a8, a8, 3 -; XTENSA-ATOMIC-NEXT: slli a9, a13, 16 -; XTENSA-ATOMIC-NEXT: addi a9, a9, -1 +; XTENSA-ATOMIC-NEXT: slli a8, a2, 3 +; XTENSA-ATOMIC-NEXT: movi a9, 24 +; XTENSA-ATOMIC-NEXT: and a8, a8, a9 +; XTENSA-ATOMIC-NEXT: movi a9, 1 ; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a10, a9 +; XTENSA-ATOMIC-NEXT: l32r a11, .LCPI6_0 +; XTENSA-ATOMIC-NEXT: ssl a8 +; XTENSA-ATOMIC-NEXT: sll a11, a11 ; XTENSA-ATOMIC-NEXT: movi a12, -1 -; XTENSA-ATOMIC-NEXT: sll a11, a9 ; XTENSA-ATOMIC-NEXT: xor a12, a11, a12 -; XTENSA-ATOMIC-NEXT: l32i a14, a10, 0 -; XTENSA-ATOMIC-NEXT: sll a13, a13 -; XTENSA-ATOMIC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a15, a14, a14 -; XTENSA-ATOMIC-NEXT: and a14, a15, a11 -; XTENSA-ATOMIC-NEXT: add a14, a14, a13 -; XTENSA-ATOMIC-NEXT: and a14, a14, a11 +; XTENSA-ATOMIC-NEXT: movi a13, -4 +; XTENSA-ATOMIC-NEXT: and a13, a2, a13 +; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a15, a13, 0 +; XTENSA-ATOMIC-NEXT: movi a14, 0 +; XTENSA-ATOMIC-NEXT: j .LBB6_2 +; XTENSA-ATOMIC-NEXT: .LBB6_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB6_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a15, a7, a7 +; XTENSA-ATOMIC-NEXT: beqi a6, 1, .LBB6_4 +; XTENSA-ATOMIC-NEXT: .LBB6_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; XTENSA-ATOMIC-NEXT: and a7, a15, a12 -; XTENSA-ATOMIC-NEXT: or a7, a14, a7 +; XTENSA-ATOMIC-NEXT: add a6, a15, a10 +; XTENSA-ATOMIC-NEXT: and a6, a6, a11 +; XTENSA-ATOMIC-NEXT: or a7, a7, a6 ; XTENSA-ATOMIC-NEXT: wsr a15, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a7, a10, 0 -; XTENSA-ATOMIC-NEXT: mov.n a14, a7 -; XTENSA-ATOMIC-NEXT: bne a7, a15, .LBB6_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: s32c1i a7, a13, 0 +; XTENSA-ATOMIC-NEXT: or a6, a9, a9 +; XTENSA-ATOMIC-NEXT: beq a7, a15, .LBB6_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB6_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a6, a14, a14 +; XTENSA-ATOMIC-NEXT: j .LBB6_1 +; XTENSA-ATOMIC-NEXT: .LBB6_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: ssr a8 -; XTENSA-ATOMIC-NEXT: srl a8, a14 -; XTENSA-ATOMIC-NEXT: and a2, a8, a9 +; XTENSA-ATOMIC-NEXT: srl a2, a7 ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw add ptr %p, i16 1 seq_cst, align 2 @@ -501,17 +520,27 @@ define i32 @rmw32_add_monotonic(ptr %p) nounwind { ; XTENSA-ATOMIC-LABEL: rmw32_add_monotonic: ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 -; XTENSA-ATOMIC-NEXT: movi a8, 1 -; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a11, a10, a10 -; XTENSA-ATOMIC-NEXT: add a9, a11, a8 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB16_2 +; XTENSA-ATOMIC-NEXT: .LBB16_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB16_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB16_4 +; XTENSA-ATOMIC-NEXT: .LBB16_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: addi a8, a11, 1 ; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a10, a9 -; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB16_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB16_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB16_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB16_1 +; XTENSA-ATOMIC-NEXT: .LBB16_4: # %atomicrmw.end +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw add ptr %p, i32 1 monotonic, align 4 ret i32 %v @@ -533,18 +562,28 @@ define i32 @rmw32_add_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 1 -; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a11, a10, a10 -; XTENSA-ATOMIC-NEXT: add a9, a11, a8 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB17_2 +; XTENSA-ATOMIC-NEXT: .LBB17_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB17_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB17_4 +; XTENSA-ATOMIC-NEXT: .LBB17_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: addi a8, a11, 1 ; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a10, a9 -; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB17_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB17_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB17_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB17_1 +; XTENSA-ATOMIC-NEXT: .LBB17_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw add ptr %p, i32 1 seq_cst, align 4 ret i32 %v @@ -566,18 +605,28 @@ define i32 @rmw32_sub_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 1 -; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a11, a10, a10 -; XTENSA-ATOMIC-NEXT: sub a9, a11, a8 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 0 +; XTENSA-ATOMIC-NEXT: movi a10, 1 +; XTENSA-ATOMIC-NEXT: j .LBB18_2 +; XTENSA-ATOMIC-NEXT: .LBB18_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB18_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB18_4 +; XTENSA-ATOMIC-NEXT: .LBB18_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: addi a8, a11, -1 ; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a10, a9 -; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB18_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB18_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB18_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: j .LBB18_1 +; XTENSA-ATOMIC-NEXT: .LBB18_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw sub ptr %p, i32 1 seq_cst, align 4 ret i32 %v @@ -599,18 +648,28 @@ define i32 @rmw32_and_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 1 -; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a11, a10, a10 -; XTENSA-ATOMIC-NEXT: and a9, a11, a8 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 1 +; XTENSA-ATOMIC-NEXT: movi a10, 0 +; XTENSA-ATOMIC-NEXT: j .LBB19_2 +; XTENSA-ATOMIC-NEXT: .LBB19_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB19_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB19_4 +; XTENSA-ATOMIC-NEXT: .LBB19_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: and a8, a11, a9 ; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a10, a9 -; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB19_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB19_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB19_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: j .LBB19_1 +; XTENSA-ATOMIC-NEXT: .LBB19_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw and ptr %p, i32 1 seq_cst, align 4 ret i32 %v @@ -632,20 +691,31 @@ define i32 @rmw32_nand_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 1 -; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: l32i a13, a2, 0 ; XTENSA-ATOMIC-NEXT: movi a9, -1 -; XTENSA-ATOMIC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a12, a11, a11 -; XTENSA-ATOMIC-NEXT: and a10, a12, a8 -; XTENSA-ATOMIC-NEXT: xor a10, a10, a9 -; XTENSA-ATOMIC-NEXT: wsr a12, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a11, a10 -; XTENSA-ATOMIC-NEXT: bne a12, a10, .LBB20_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a10 +; XTENSA-ATOMIC-NEXT: movi a10, -2 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: movi a12, 1 +; XTENSA-ATOMIC-NEXT: j .LBB20_2 +; XTENSA-ATOMIC-NEXT: .LBB20_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB20_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a14, 1, .LBB20_4 +; XTENSA-ATOMIC-NEXT: .LBB20_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a8, a13, a9 +; XTENSA-ATOMIC-NEXT: or a8, a8, a10 +; XTENSA-ATOMIC-NEXT: wsr a13, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a14, a12, a12 +; XTENSA-ATOMIC-NEXT: beq a8, a13, .LBB20_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB20_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a14, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB20_1 +; XTENSA-ATOMIC-NEXT: .LBB20_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw nand ptr %p, i32 1 seq_cst, align 4 ret i32 %v @@ -667,18 +737,28 @@ define i32 @rmw32_or_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 1 -; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a11, a10, a10 -; XTENSA-ATOMIC-NEXT: or a9, a11, a8 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 1 +; XTENSA-ATOMIC-NEXT: movi a10, 0 +; XTENSA-ATOMIC-NEXT: j .LBB21_2 +; XTENSA-ATOMIC-NEXT: .LBB21_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB21_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB21_4 +; XTENSA-ATOMIC-NEXT: .LBB21_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a9 ; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a10, a9 -; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB21_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB21_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB21_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: j .LBB21_1 +; XTENSA-ATOMIC-NEXT: .LBB21_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw or ptr %p, i32 1 seq_cst, align 4 ret i32 %v @@ -700,18 +780,28 @@ define i32 @rmw32_xor_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 1 -; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a11, a10, a10 -; XTENSA-ATOMIC-NEXT: xor a9, a11, a8 +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 1 +; XTENSA-ATOMIC-NEXT: movi a10, 0 +; XTENSA-ATOMIC-NEXT: j .LBB22_2 +; XTENSA-ATOMIC-NEXT: .LBB22_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB22_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB22_4 +; XTENSA-ATOMIC-NEXT: .LBB22_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: xor a8, a11, a9 ; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a9, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a10, a9 -; XTENSA-ATOMIC-NEXT: bne a11, a9, .LBB22_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: -; XTENSA-ATOMIC-NEXT: mov.n a2, a9 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB22_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB22_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: j .LBB22_1 +; XTENSA-ATOMIC-NEXT: .LBB22_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw xor ptr %p, i32 1 seq_cst, align 4 ret i32 %v @@ -752,23 +842,34 @@ define i32 @rmw32_max_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 1 ; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a9, a11, a11 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: blt a9, a8, .LBB23_3 -; XTENSA-ATOMIC-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1 -; XTENSA-ATOMIC-NEXT: mov.n a10, a8 -; XTENSA-ATOMIC-NEXT: .LBB23_3: # in Loop: Header=BB23_1 Depth=1 -; XTENSA-ATOMIC-NEXT: mov.n a10, a10 -; XTENSA-ATOMIC-NEXT: wsr a9, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a11, a10 -; XTENSA-ATOMIC-NEXT: bne a9, a10, .LBB23_1 -; XTENSA-ATOMIC-NEXT: # %bb.4: -; XTENSA-ATOMIC-NEXT: mov.n a2, a10 +; XTENSA-ATOMIC-NEXT: movi a9, 1 +; XTENSA-ATOMIC-NEXT: movi a10, 0 +; XTENSA-ATOMIC-NEXT: j .LBB23_2 +; XTENSA-ATOMIC-NEXT: .LBB23_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB23_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB23_6 +; XTENSA-ATOMIC-NEXT: .LBB23_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a9, a9 +; XTENSA-ATOMIC-NEXT: bge a9, a11, .LBB23_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB23_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB23_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB23_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB23_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB23_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: j .LBB23_1 +; XTENSA-ATOMIC-NEXT: .LBB23_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw max ptr %p, i32 1 seq_cst, align 4 ret i32 %v @@ -809,23 +910,35 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 1 -; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a9, a11, a11 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: bge a9, a8, .LBB24_3 -; XTENSA-ATOMIC-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1 -; XTENSA-ATOMIC-NEXT: mov.n a10, a8 -; XTENSA-ATOMIC-NEXT: .LBB24_3: # in Loop: Header=BB24_1 Depth=1 -; XTENSA-ATOMIC-NEXT: mov.n a10, a10 -; XTENSA-ATOMIC-NEXT: wsr a9, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a11, a10 -; XTENSA-ATOMIC-NEXT: bne a9, a10, .LBB24_1 -; XTENSA-ATOMIC-NEXT: # %bb.4: -; XTENSA-ATOMIC-NEXT: mov.n a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a12, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 1 +; XTENSA-ATOMIC-NEXT: movi a10, 2 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: or a8, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB24_2 +; XTENSA-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a13, 1, .LBB24_6 +; XTENSA-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: blt a12, a10, .LBB24_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a9, a9 +; XTENSA-ATOMIC-NEXT: .LBB24_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a12, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a13, a9, a9 +; XTENSA-ATOMIC-NEXT: beq a8, a12, .LBB24_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB24_1 +; XTENSA-ATOMIC-NEXT: .LBB24_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw min ptr %p, i32 1 seq_cst, align 4 ret i32 %v @@ -866,23 +979,34 @@ define i32 @rmw32_umax_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 1 ; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a9, a11, a11 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: bltu a9, a8, .LBB25_3 -; XTENSA-ATOMIC-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1 -; XTENSA-ATOMIC-NEXT: mov.n a10, a8 -; XTENSA-ATOMIC-NEXT: .LBB25_3: # in Loop: Header=BB25_1 Depth=1 -; XTENSA-ATOMIC-NEXT: mov.n a10, a10 -; XTENSA-ATOMIC-NEXT: wsr a9, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a11, a10 -; XTENSA-ATOMIC-NEXT: bne a9, a10, .LBB25_1 -; XTENSA-ATOMIC-NEXT: # %bb.4: -; XTENSA-ATOMIC-NEXT: mov.n a2, a10 +; XTENSA-ATOMIC-NEXT: movi a9, 1 +; XTENSA-ATOMIC-NEXT: movi a10, 0 +; XTENSA-ATOMIC-NEXT: j .LBB25_2 +; XTENSA-ATOMIC-NEXT: .LBB25_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB25_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB25_6 +; XTENSA-ATOMIC-NEXT: .LBB25_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a9, a9 +; XTENSA-ATOMIC-NEXT: bgeu a9, a11, .LBB25_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB25_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a11, a11 +; XTENSA-ATOMIC-NEXT: .LBB25_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB25_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB25_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB25_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: j .LBB25_1 +; XTENSA-ATOMIC-NEXT: .LBB25_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw umax ptr %p, i32 1 seq_cst, align 4 ret i32 %v @@ -923,23 +1047,35 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: movi a8, 1 -; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a9, a11, a11 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: bgeu a9, a8, .LBB26_3 -; XTENSA-ATOMIC-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1 -; XTENSA-ATOMIC-NEXT: mov.n a10, a8 -; XTENSA-ATOMIC-NEXT: .LBB26_3: # in Loop: Header=BB26_1 Depth=1 -; XTENSA-ATOMIC-NEXT: mov.n a10, a10 -; XTENSA-ATOMIC-NEXT: wsr a9, scompare1 -; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: mov.n a11, a10 -; XTENSA-ATOMIC-NEXT: bne a9, a10, .LBB26_1 -; XTENSA-ATOMIC-NEXT: # %bb.4: -; XTENSA-ATOMIC-NEXT: mov.n a2, a10 +; XTENSA-ATOMIC-NEXT: l32i a12, a2, 0 +; XTENSA-ATOMIC-NEXT: movi a9, 1 +; XTENSA-ATOMIC-NEXT: movi a10, 2 +; XTENSA-ATOMIC-NEXT: movi a11, 0 +; XTENSA-ATOMIC-NEXT: or a8, a12, a12 +; XTENSA-ATOMIC-NEXT: j .LBB26_2 +; XTENSA-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a13, 1, .LBB26_6 +; XTENSA-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: bltu a12, a10, .LBB26_4 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a8, a9, a9 +; XTENSA-ATOMIC-NEXT: .LBB26_4: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a12, scompare1 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a13, a9, a9 +; XTENSA-ATOMIC-NEXT: beq a8, a12, .LBB26_1 +; XTENSA-ATOMIC-NEXT: # %bb.5: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a13, a11, a11 +; XTENSA-ATOMIC-NEXT: j .LBB26_1 +; XTENSA-ATOMIC-NEXT: .LBB26_6: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw %v = atomicrmw umin ptr %p, i32 1 seq_cst, align 4 ret i32 %v @@ -961,16 +1097,26 @@ define i32 @rmw32_xchg_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw +; XTENSA-ATOMIC-NEXT: l32i a11, a2, 0 ; XTENSA-ATOMIC-NEXT: movi a9, 1 -; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a8, a10, a10 -; XTENSA-ATOMIC-NEXT: wsr a8, scompare1 -; XTENSA-ATOMIC-NEXT: or a10, a9, a9 -; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: bne a10, a8, .LBB27_1 -; XTENSA-ATOMIC-NEXT: # %bb.2: +; XTENSA-ATOMIC-NEXT: movi a10, 0 +; XTENSA-ATOMIC-NEXT: j .LBB27_2 +; XTENSA-ATOMIC-NEXT: .LBB27_1: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB27_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a11, a8, a8 +; XTENSA-ATOMIC-NEXT: beqi a12, 1, .LBB27_4 +; XTENSA-ATOMIC-NEXT: .LBB27_2: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; XTENSA-ATOMIC-NEXT: wsr a11, scompare1 +; XTENSA-ATOMIC-NEXT: or a8, a9, a9 +; XTENSA-ATOMIC-NEXT: s32c1i a8, a2, 0 +; XTENSA-ATOMIC-NEXT: or a12, a9, a9 +; XTENSA-ATOMIC-NEXT: beq a8, a11, .LBB27_1 +; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start +; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB27_2 Depth=1 +; XTENSA-ATOMIC-NEXT: or a12, a10, a10 +; XTENSA-ATOMIC-NEXT: j .LBB27_1 +; XTENSA-ATOMIC-NEXT: .LBB27_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw ; XTENSA-ATOMIC-NEXT: or a2, a8, a8 ; XTENSA-ATOMIC-NEXT: retw @@ -983,21 +1129,20 @@ define float @rmw32_fadd_seq_cst(ptr %p) nounwind { ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 48 ; XTENSA-NEXT: l32i a10, a2, 0 -; XTENSA-NEXT: l32r a7, .LCPI28_0 -; XTENSA-NEXT: l32r a5, .LCPI28_1 -; XTENSA-NEXT: movi a6, 5 -; XTENSA-NEXT: l32r a4, .LCPI28_2 +; XTENSA-NEXT: l32r a6, .LCPI28_1 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a5, .LCPI28_2 ; XTENSA-NEXT: .LBB28_1: # %atomicrmw.start ; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 ; XTENSA-NEXT: s32i a10, a1, 0 -; XTENSA-NEXT: or a11, a7, a7 -; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32r a11, .LCPI28_0 +; XTENSA-NEXT: callx8 a6 ; XTENSA-NEXT: or a12, a10, a10 ; XTENSA-NEXT: addi a11, a1, 0 ; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: or a13, a6, a6 -; XTENSA-NEXT: or a14, a6, a6 -; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 ; XTENSA-NEXT: or a8, a10, a10 ; XTENSA-NEXT: l32i a10, a1, 0 ; XTENSA-NEXT: beqz a8, .LBB28_1 @@ -1009,28 +1154,27 @@ define float @rmw32_fadd_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a6, a2, 0 -; XTENSA-ATOMIC-NEXT: l32r a7, .LCPI28_0 -; XTENSA-ATOMIC-NEXT: l32r a5, .LCPI28_1 -; XTENSA-ATOMIC-NEXT: movi a4, 0 -; XTENSA-ATOMIC-NEXT: movi a3, 1 +; XTENSA-ATOMIC-NEXT: l32i a7, a2, 0 +; XTENSA-ATOMIC-NEXT: l32r a6, .LCPI28_1 +; XTENSA-ATOMIC-NEXT: movi a5, 0 +; XTENSA-ATOMIC-NEXT: movi a4, 1 ; XTENSA-ATOMIC-NEXT: j .LBB28_2 ; XTENSA-ATOMIC-NEXT: .LBB28_1: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB28_2 Depth=1 -; XTENSA-ATOMIC-NEXT: or a6, a10, a10 +; XTENSA-ATOMIC-NEXT: or a7, a10, a10 ; XTENSA-ATOMIC-NEXT: beqi a8, 1, .LBB28_4 ; XTENSA-ATOMIC-NEXT: .LBB28_2: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a6, a6 -; XTENSA-ATOMIC-NEXT: or a11, a7, a7 -; XTENSA-ATOMIC-NEXT: callx8 a5 -; XTENSA-ATOMIC-NEXT: wsr a6, scompare1 +; XTENSA-ATOMIC-NEXT: l32r a11, .LCPI28_0 +; XTENSA-ATOMIC-NEXT: or a10, a7, a7 +; XTENSA-ATOMIC-NEXT: callx8 a6 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: or a8, a3, a3 -; XTENSA-ATOMIC-NEXT: beq a10, a6, .LBB28_1 +; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: beq a10, a7, .LBB28_1 ; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB28_2 Depth=1 -; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: or a8, a5, a5 ; XTENSA-ATOMIC-NEXT: j .LBB28_1 ; XTENSA-ATOMIC-NEXT: .LBB28_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw @@ -1045,21 +1189,20 @@ define float @rmw32_fsub_seq_cst(ptr %p) nounwind { ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 48 ; XTENSA-NEXT: l32i a10, a2, 0 -; XTENSA-NEXT: l32r a7, .LCPI29_0 -; XTENSA-NEXT: l32r a5, .LCPI29_1 -; XTENSA-NEXT: movi a6, 5 -; XTENSA-NEXT: l32r a4, .LCPI29_2 +; XTENSA-NEXT: l32r a6, .LCPI29_1 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a5, .LCPI29_2 ; XTENSA-NEXT: .LBB29_1: # %atomicrmw.start ; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 ; XTENSA-NEXT: s32i a10, a1, 0 -; XTENSA-NEXT: or a11, a7, a7 -; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32r a11, .LCPI29_0 +; XTENSA-NEXT: callx8 a6 ; XTENSA-NEXT: or a12, a10, a10 ; XTENSA-NEXT: addi a11, a1, 0 ; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: or a13, a6, a6 -; XTENSA-NEXT: or a14, a6, a6 -; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 ; XTENSA-NEXT: or a8, a10, a10 ; XTENSA-NEXT: l32i a10, a1, 0 ; XTENSA-NEXT: beqz a8, .LBB29_1 @@ -1071,28 +1214,27 @@ define float @rmw32_fsub_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a6, a2, 0 -; XTENSA-ATOMIC-NEXT: l32r a7, .LCPI29_0 -; XTENSA-ATOMIC-NEXT: l32r a5, .LCPI29_1 -; XTENSA-ATOMIC-NEXT: movi a4, 0 -; XTENSA-ATOMIC-NEXT: movi a3, 1 +; XTENSA-ATOMIC-NEXT: l32i a7, a2, 0 +; XTENSA-ATOMIC-NEXT: l32r a6, .LCPI29_1 +; XTENSA-ATOMIC-NEXT: movi a5, 0 +; XTENSA-ATOMIC-NEXT: movi a4, 1 ; XTENSA-ATOMIC-NEXT: j .LBB29_2 ; XTENSA-ATOMIC-NEXT: .LBB29_1: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB29_2 Depth=1 -; XTENSA-ATOMIC-NEXT: or a6, a10, a10 +; XTENSA-ATOMIC-NEXT: or a7, a10, a10 ; XTENSA-ATOMIC-NEXT: beqi a8, 1, .LBB29_4 ; XTENSA-ATOMIC-NEXT: .LBB29_2: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a6, a6 -; XTENSA-ATOMIC-NEXT: or a11, a7, a7 -; XTENSA-ATOMIC-NEXT: callx8 a5 -; XTENSA-ATOMIC-NEXT: wsr a6, scompare1 +; XTENSA-ATOMIC-NEXT: l32r a11, .LCPI29_0 +; XTENSA-ATOMIC-NEXT: or a10, a7, a7 +; XTENSA-ATOMIC-NEXT: callx8 a6 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: or a8, a3, a3 -; XTENSA-ATOMIC-NEXT: beq a10, a6, .LBB29_1 +; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: beq a10, a7, .LBB29_1 ; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB29_2 Depth=1 -; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: or a8, a5, a5 ; XTENSA-ATOMIC-NEXT: j .LBB29_1 ; XTENSA-ATOMIC-NEXT: .LBB29_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw @@ -1107,21 +1249,20 @@ define float @rmw32_fmin_seq_cst(ptr %p) nounwind { ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 48 ; XTENSA-NEXT: l32i a10, a2, 0 -; XTENSA-NEXT: l32r a7, .LCPI30_0 -; XTENSA-NEXT: l32r a5, .LCPI30_1 -; XTENSA-NEXT: movi a6, 5 -; XTENSA-NEXT: l32r a4, .LCPI30_2 +; XTENSA-NEXT: l32r a6, .LCPI30_1 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a5, .LCPI30_2 ; XTENSA-NEXT: .LBB30_1: # %atomicrmw.start ; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 ; XTENSA-NEXT: s32i a10, a1, 0 -; XTENSA-NEXT: or a11, a7, a7 -; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32r a11, .LCPI30_0 +; XTENSA-NEXT: callx8 a6 ; XTENSA-NEXT: or a12, a10, a10 ; XTENSA-NEXT: addi a11, a1, 0 ; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: or a13, a6, a6 -; XTENSA-NEXT: or a14, a6, a6 -; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 ; XTENSA-NEXT: or a8, a10, a10 ; XTENSA-NEXT: l32i a10, a1, 0 ; XTENSA-NEXT: beqz a8, .LBB30_1 @@ -1133,28 +1274,27 @@ define float @rmw32_fmin_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a6, a2, 0 -; XTENSA-ATOMIC-NEXT: l32r a7, .LCPI30_0 -; XTENSA-ATOMIC-NEXT: l32r a5, .LCPI30_1 -; XTENSA-ATOMIC-NEXT: movi a4, 0 -; XTENSA-ATOMIC-NEXT: movi a3, 1 +; XTENSA-ATOMIC-NEXT: l32i a7, a2, 0 +; XTENSA-ATOMIC-NEXT: l32r a6, .LCPI30_1 +; XTENSA-ATOMIC-NEXT: movi a5, 0 +; XTENSA-ATOMIC-NEXT: movi a4, 1 ; XTENSA-ATOMIC-NEXT: j .LBB30_2 ; XTENSA-ATOMIC-NEXT: .LBB30_1: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB30_2 Depth=1 -; XTENSA-ATOMIC-NEXT: or a6, a10, a10 +; XTENSA-ATOMIC-NEXT: or a7, a10, a10 ; XTENSA-ATOMIC-NEXT: beqi a8, 1, .LBB30_4 ; XTENSA-ATOMIC-NEXT: .LBB30_2: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a6, a6 -; XTENSA-ATOMIC-NEXT: or a11, a7, a7 -; XTENSA-ATOMIC-NEXT: callx8 a5 -; XTENSA-ATOMIC-NEXT: wsr a6, scompare1 +; XTENSA-ATOMIC-NEXT: l32r a11, .LCPI30_0 +; XTENSA-ATOMIC-NEXT: or a10, a7, a7 +; XTENSA-ATOMIC-NEXT: callx8 a6 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: or a8, a3, a3 -; XTENSA-ATOMIC-NEXT: beq a10, a6, .LBB30_1 +; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: beq a10, a7, .LBB30_1 ; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB30_2 Depth=1 -; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: or a8, a5, a5 ; XTENSA-ATOMIC-NEXT: j .LBB30_1 ; XTENSA-ATOMIC-NEXT: .LBB30_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw @@ -1169,21 +1309,20 @@ define float @rmw32_fmax_seq_cst(ptr %p) nounwind { ; XTENSA: # %bb.0: ; XTENSA-NEXT: entry a1, 48 ; XTENSA-NEXT: l32i a10, a2, 0 -; XTENSA-NEXT: l32r a7, .LCPI31_0 -; XTENSA-NEXT: l32r a5, .LCPI31_1 -; XTENSA-NEXT: movi a6, 5 -; XTENSA-NEXT: l32r a4, .LCPI31_2 +; XTENSA-NEXT: l32r a6, .LCPI31_1 +; XTENSA-NEXT: movi a7, 5 +; XTENSA-NEXT: l32r a5, .LCPI31_2 ; XTENSA-NEXT: .LBB31_1: # %atomicrmw.start ; XTENSA-NEXT: # =>This Inner Loop Header: Depth=1 ; XTENSA-NEXT: s32i a10, a1, 0 -; XTENSA-NEXT: or a11, a7, a7 -; XTENSA-NEXT: callx8 a5 +; XTENSA-NEXT: l32r a11, .LCPI31_0 +; XTENSA-NEXT: callx8 a6 ; XTENSA-NEXT: or a12, a10, a10 ; XTENSA-NEXT: addi a11, a1, 0 ; XTENSA-NEXT: or a10, a2, a2 -; XTENSA-NEXT: or a13, a6, a6 -; XTENSA-NEXT: or a14, a6, a6 -; XTENSA-NEXT: callx8 a4 +; XTENSA-NEXT: or a13, a7, a7 +; XTENSA-NEXT: or a14, a7, a7 +; XTENSA-NEXT: callx8 a5 ; XTENSA-NEXT: or a8, a10, a10 ; XTENSA-NEXT: l32i a10, a1, 0 ; XTENSA-NEXT: beqz a8, .LBB31_1 @@ -1195,28 +1334,27 @@ define float @rmw32_fmax_seq_cst(ptr %p) nounwind { ; XTENSA-ATOMIC: # %bb.0: ; XTENSA-ATOMIC-NEXT: entry a1, 32 ; XTENSA-ATOMIC-NEXT: memw -; XTENSA-ATOMIC-NEXT: l32i a6, a2, 0 -; XTENSA-ATOMIC-NEXT: l32r a7, .LCPI31_0 -; XTENSA-ATOMIC-NEXT: l32r a5, .LCPI31_1 -; XTENSA-ATOMIC-NEXT: movi a4, 0 -; XTENSA-ATOMIC-NEXT: movi a3, 1 +; XTENSA-ATOMIC-NEXT: l32i a7, a2, 0 +; XTENSA-ATOMIC-NEXT: l32r a6, .LCPI31_1 +; XTENSA-ATOMIC-NEXT: movi a5, 0 +; XTENSA-ATOMIC-NEXT: movi a4, 1 ; XTENSA-ATOMIC-NEXT: j .LBB31_2 ; XTENSA-ATOMIC-NEXT: .LBB31_1: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB31_2 Depth=1 -; XTENSA-ATOMIC-NEXT: or a6, a10, a10 +; XTENSA-ATOMIC-NEXT: or a7, a10, a10 ; XTENSA-ATOMIC-NEXT: beqi a8, 1, .LBB31_4 ; XTENSA-ATOMIC-NEXT: .LBB31_2: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 -; XTENSA-ATOMIC-NEXT: or a10, a6, a6 -; XTENSA-ATOMIC-NEXT: or a11, a7, a7 -; XTENSA-ATOMIC-NEXT: callx8 a5 -; XTENSA-ATOMIC-NEXT: wsr a6, scompare1 +; XTENSA-ATOMIC-NEXT: l32r a11, .LCPI31_0 +; XTENSA-ATOMIC-NEXT: or a10, a7, a7 +; XTENSA-ATOMIC-NEXT: callx8 a6 +; XTENSA-ATOMIC-NEXT: wsr a7, scompare1 ; XTENSA-ATOMIC-NEXT: s32c1i a10, a2, 0 -; XTENSA-ATOMIC-NEXT: or a8, a3, a3 -; XTENSA-ATOMIC-NEXT: beq a10, a6, .LBB31_1 +; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: beq a10, a7, .LBB31_1 ; XTENSA-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; XTENSA-ATOMIC-NEXT: # in Loop: Header=BB31_2 Depth=1 -; XTENSA-ATOMIC-NEXT: or a8, a4, a4 +; XTENSA-ATOMIC-NEXT: or a8, a5, a5 ; XTENSA-ATOMIC-NEXT: j .LBB31_1 ; XTENSA-ATOMIC-NEXT: .LBB31_4: # %atomicrmw.end ; XTENSA-ATOMIC-NEXT: memw From afc1654c5394b96da444a84351be3566b9d36d63 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 6 Aug 2025 00:54:36 +0300 Subject: [PATCH 3/4] [Xtensa] Add AtomicExpand pass test. --- .../AtomicExpand/Xtensa/atomicrmw-expand.ll | 2643 +++++++++++++++++ .../AtomicExpand/Xtensa/lit.local.cfg | 5 + 2 files changed, 2648 insertions(+) create mode 100644 llvm/test/Transforms/AtomicExpand/Xtensa/atomicrmw-expand.ll create mode 100644 llvm/test/Transforms/AtomicExpand/Xtensa/lit.local.cfg diff --git a/llvm/test/Transforms/AtomicExpand/Xtensa/atomicrmw-expand.ll b/llvm/test/Transforms/AtomicExpand/Xtensa/atomicrmw-expand.ll new file mode 100644 index 0000000000000..59916cc9e8e91 --- /dev/null +++ b/llvm/test/Transforms/AtomicExpand/Xtensa/atomicrmw-expand.ll @@ -0,0 +1,2643 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -S -mtriple=xtensa-- -passes=atomic-expand %s | FileCheck %s + +define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_xchg_i8_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_exchange_1(ptr [[A]], i8 [[B]], i32 0) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i8 %b monotonic + ret i8 %res +} + +define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_xchg_i8_acquire( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_exchange_1(ptr [[A]], i8 [[B]], i32 2) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i8 %b acquire + ret i8 %res +} + +define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_xchg_i8_release( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_exchange_1(ptr [[A]], i8 [[B]], i32 3) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i8 %b release + ret i8 %res +} + +define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_xchg_i8_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_exchange_1(ptr [[A]], i8 [[B]], i32 4) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i8 %b acq_rel + ret i8 %res +} + +define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_xchg_i8_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_exchange_1(ptr [[A]], i8 [[B]], i32 5) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i8 %b seq_cst + ret i8 %res +} + +define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_add_i8_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_add_1(ptr [[A]], i8 [[B]], i32 0) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw add ptr %a, i8 %b monotonic + ret i8 %res +} + +define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_add_i8_acquire( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_add_1(ptr [[A]], i8 [[B]], i32 2) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw add ptr %a, i8 %b acquire + ret i8 %res +} + +define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_add_i8_release( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_add_1(ptr [[A]], i8 [[B]], i32 3) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw add ptr %a, i8 %b release + ret i8 %res +} + +define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_add_i8_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_add_1(ptr [[A]], i8 [[B]], i32 4) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw add ptr %a, i8 %b acq_rel + ret i8 %res +} + +define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_add_i8_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_add_1(ptr [[A]], i8 [[B]], i32 5) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw add ptr %a, i8 %b seq_cst + ret i8 %res +} + +define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_sub_i8_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_sub_1(ptr [[A]], i8 [[B]], i32 0) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i8 %b monotonic + ret i8 %res +} + +define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_sub_i8_acquire( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_sub_1(ptr [[A]], i8 [[B]], i32 2) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i8 %b acquire + ret i8 %res +} + +define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_sub_i8_release( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_sub_1(ptr [[A]], i8 [[B]], i32 3) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i8 %b release + ret i8 %res +} + +define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_sub_i8_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_sub_1(ptr [[A]], i8 [[B]], i32 4) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i8 %b acq_rel + ret i8 %res +} + +define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_sub_i8_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_sub_1(ptr [[A]], i8 [[B]], i32 5) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i8 %b seq_cst + ret i8 %res +} + +define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_and_i8_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_and_1(ptr [[A]], i8 [[B]], i32 0) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw and ptr %a, i8 %b monotonic + ret i8 %res +} + +define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_and_i8_acquire( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_and_1(ptr [[A]], i8 [[B]], i32 2) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw and ptr %a, i8 %b acquire + ret i8 %res +} + +define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_and_i8_release( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_and_1(ptr [[A]], i8 [[B]], i32 3) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw and ptr %a, i8 %b release + ret i8 %res +} + +define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_and_i8_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_and_1(ptr [[A]], i8 [[B]], i32 4) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw and ptr %a, i8 %b acq_rel + ret i8 %res +} + +define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_and_i8_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_and_1(ptr [[A]], i8 [[B]], i32 5) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw and ptr %a, i8 %b seq_cst + ret i8 %res +} + +define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_nand_i8_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_nand_1(ptr [[A]], i8 [[B]], i32 0) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw nand ptr %a, i8 %b monotonic + ret i8 %res +} + +define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_nand_i8_acquire( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_nand_1(ptr [[A]], i8 [[B]], i32 2) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw nand ptr %a, i8 %b acquire + ret i8 %res +} + +define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_nand_i8_release( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_nand_1(ptr [[A]], i8 [[B]], i32 3) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw nand ptr %a, i8 %b release + ret i8 %res +} + +define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_nand_i8_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_nand_1(ptr [[A]], i8 [[B]], i32 4) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw nand ptr %a, i8 %b acq_rel + ret i8 %res +} + +define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_nand_i8_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_nand_1(ptr [[A]], i8 [[B]], i32 5) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw nand ptr %a, i8 %b seq_cst + ret i8 %res +} + +define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_or_i8_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_or_1(ptr [[A]], i8 [[B]], i32 0) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw or ptr %a, i8 %b monotonic + ret i8 %res +} + +define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_or_i8_acquire( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_or_1(ptr [[A]], i8 [[B]], i32 2) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw or ptr %a, i8 %b acquire + ret i8 %res +} + +define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_or_i8_release( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_or_1(ptr [[A]], i8 [[B]], i32 3) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw or ptr %a, i8 %b release + ret i8 %res +} + +define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_or_i8_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_or_1(ptr [[A]], i8 [[B]], i32 4) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw or ptr %a, i8 %b acq_rel + ret i8 %res +} + +define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_or_i8_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_or_1(ptr [[A]], i8 [[B]], i32 5) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw or ptr %a, i8 %b seq_cst + ret i8 %res +} + +define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_xor_i8_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_xor_1(ptr [[A]], i8 [[B]], i32 0) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i8 %b monotonic + ret i8 %res +} + +define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_xor_i8_acquire( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_xor_1(ptr [[A]], i8 [[B]], i32 2) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i8 %b acquire + ret i8 %res +} + +define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_xor_i8_release( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_xor_1(ptr [[A]], i8 [[B]], i32 3) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i8 %b release + ret i8 %res +} + +define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_xor_i8_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_xor_1(ptr [[A]], i8 [[B]], i32 4) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i8 %b acq_rel + ret i8 %res +} + +define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_xor_i8_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @__atomic_fetch_xor_1(ptr [[A]], i8 [[B]], i32 5) +; CHECK-NEXT: ret i8 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i8 %b seq_cst + ret i8 %res +} + +define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_max_i8_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i8 %b monotonic + ret i8 %res +} + +define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_max_i8_acquire( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i8 %b acquire + ret i8 %res +} + +define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_max_i8_release( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i8 %b release + ret i8 %res +} + +define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_max_i8_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i8 %b acq_rel + ret i8 %res +} + +define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_max_i8_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i8 %b seq_cst + ret i8 %res +} + +define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_min_i8_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i8 %b monotonic + ret i8 %res +} + +define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_min_i8_acquire( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i8 %b acquire + ret i8 %res +} + +define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_min_i8_release( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i8 %b release + ret i8 %res +} + +define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_min_i8_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i8 %b acq_rel + ret i8 %res +} + +define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_min_i8_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i8 %b seq_cst + ret i8 %res +} + +define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_umax_i8_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i8 %b monotonic + ret i8 %res +} + +define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_umax_i8_acquire( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i8 %b acquire + ret i8 %res +} + +define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_umax_i8_release( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i8 %b release + ret i8 %res +} + +define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_umax_i8_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i8 %b acq_rel + ret i8 %res +} + +define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_umax_i8_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i8 %b seq_cst + ret i8 %res +} + +define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_umin_i8_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i8 %b monotonic + ret i8 %res +} + +define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_umin_i8_acquire( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i8 %b acquire + ret i8 %res +} + +define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_umin_i8_release( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i8 %b release + ret i8 %res +} + +define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_umin_i8_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i8 %b acq_rel + ret i8 %res +} + +define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { +; CHECK-LABEL: define i8 @atomicrmw_umin_i8_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i8 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i8 [[LOADED]], i8 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: store i8 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_1(ptr [[A]], ptr [[TMP1]], i8 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8, i1 } poison, i8 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i8 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i8 %b seq_cst + ret i8 %res +} + +define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_xchg_i16_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_exchange_2(ptr [[A]], i16 [[B]], i32 0) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_xchg_i16_acquire( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_exchange_2(ptr [[A]], i16 [[B]], i32 2) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_xchg_i16_release( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_exchange_2(ptr [[A]], i16 [[B]], i32 3) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_xchg_i16_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_exchange_2(ptr [[A]], i16 [[B]], i32 4) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_xchg_i16_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_exchange_2(ptr [[A]], i16 [[B]], i32 5) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_add_i16_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_add_2(ptr [[A]], i16 [[B]], i32 0) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw add ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_add_i16_acquire( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_add_2(ptr [[A]], i16 [[B]], i32 2) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw add ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_add_i16_release( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_add_2(ptr [[A]], i16 [[B]], i32 3) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw add ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_add_i16_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_add_2(ptr [[A]], i16 [[B]], i32 4) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw add ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_add_i16_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_add_2(ptr [[A]], i16 [[B]], i32 5) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw add ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_sub_i16_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_sub_2(ptr [[A]], i16 [[B]], i32 0) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_sub_i16_acquire( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_sub_2(ptr [[A]], i16 [[B]], i32 2) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_sub_i16_release( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_sub_2(ptr [[A]], i16 [[B]], i32 3) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_sub_i16_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_sub_2(ptr [[A]], i16 [[B]], i32 4) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_sub_i16_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_sub_2(ptr [[A]], i16 [[B]], i32 5) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_and_i16_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_and_2(ptr [[A]], i16 [[B]], i32 0) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw and ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_and_i16_acquire( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_and_2(ptr [[A]], i16 [[B]], i32 2) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw and ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_and_i16_release( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_and_2(ptr [[A]], i16 [[B]], i32 3) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw and ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_and_i16_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_and_2(ptr [[A]], i16 [[B]], i32 4) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw and ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_and_i16_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_and_2(ptr [[A]], i16 [[B]], i32 5) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw and ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_nand_i16_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_nand_2(ptr [[A]], i16 [[B]], i32 0) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw nand ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_nand_i16_acquire( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_nand_2(ptr [[A]], i16 [[B]], i32 2) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw nand ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_nand_i16_release( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_nand_2(ptr [[A]], i16 [[B]], i32 3) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw nand ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_nand_i16_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_nand_2(ptr [[A]], i16 [[B]], i32 4) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw nand ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_nand_i16_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_nand_2(ptr [[A]], i16 [[B]], i32 5) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw nand ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_or_i16_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_or_2(ptr [[A]], i16 [[B]], i32 0) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw or ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_or_i16_acquire( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_or_2(ptr [[A]], i16 [[B]], i32 2) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw or ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_or_i16_release( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_or_2(ptr [[A]], i16 [[B]], i32 3) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw or ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_or_i16_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_or_2(ptr [[A]], i16 [[B]], i32 4) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw or ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_or_i16_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_or_2(ptr [[A]], i16 [[B]], i32 5) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw or ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_xor_i16_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_xor_2(ptr [[A]], i16 [[B]], i32 0) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_xor_i16_acquire( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_xor_2(ptr [[A]], i16 [[B]], i32 2) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_xor_i16_release( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_xor_2(ptr [[A]], i16 [[B]], i32 3) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_xor_i16_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_xor_2(ptr [[A]], i16 [[B]], i32 4) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_xor_i16_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i16 @__atomic_fetch_xor_2(ptr [[A]], i16 [[B]], i32 5) +; CHECK-NEXT: ret i16 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_max_i16_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_max_i16_acquire( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_max_i16_release( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_max_i16_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_max_i16_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_min_i16_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_min_i16_acquire( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_min_i16_release( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_min_i16_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_min_i16_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_umax_i16_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_umax_i16_acquire( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_umax_i16_release( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_umax_i16_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_umax_i16_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_umin_i16_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i16 %b monotonic + ret i16 %res +} + +define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_umin_i16_acquire( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i16 %b acquire + ret i16 %res +} + +define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_umin_i16_release( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i16 %b release + ret i16 %res +} + +define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_umin_i16_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i16 %b acq_rel + ret i16 %res +} + +define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { +; CHECK-LABEL: define i16 @atomicrmw_umin_i16_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i16 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i16 [[LOADED]], i16 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: store i16 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_2(ptr [[A]], ptr [[TMP1]], i16 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 2, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i16, i1 } poison, i16 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i16, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i16 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i16 %b seq_cst + ret i16 %res +} + +define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_xchg_i32_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_exchange_4(ptr [[A]], i32 [[B]], i32 0) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_xchg_i32_acquire( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_exchange_4(ptr [[A]], i32 [[B]], i32 2) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_xchg_i32_release( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_exchange_4(ptr [[A]], i32 [[B]], i32 3) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_xchg_i32_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_exchange_4(ptr [[A]], i32 [[B]], i32 4) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_xchg_i32_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_exchange_4(ptr [[A]], i32 [[B]], i32 5) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw xchg ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_add_i32_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_add_4(ptr [[A]], i32 [[B]], i32 0) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw add ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_add_i32_acquire( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_add_4(ptr [[A]], i32 [[B]], i32 2) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw add ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_add_i32_release( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_add_4(ptr [[A]], i32 [[B]], i32 3) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw add ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_add_i32_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_add_4(ptr [[A]], i32 [[B]], i32 4) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw add ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_add_i32_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_add_4(ptr [[A]], i32 [[B]], i32 5) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw add ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_sub_i32_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_sub_4(ptr [[A]], i32 [[B]], i32 0) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_sub_i32_acquire( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_sub_4(ptr [[A]], i32 [[B]], i32 2) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_sub_i32_release( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_sub_4(ptr [[A]], i32 [[B]], i32 3) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_sub_i32_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_sub_4(ptr [[A]], i32 [[B]], i32 4) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_sub_i32_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_sub_4(ptr [[A]], i32 [[B]], i32 5) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw sub ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_and_i32_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_and_4(ptr [[A]], i32 [[B]], i32 0) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw and ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_and_i32_acquire( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_and_4(ptr [[A]], i32 [[B]], i32 2) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw and ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_and_i32_release( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_and_4(ptr [[A]], i32 [[B]], i32 3) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw and ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_and_i32_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_and_4(ptr [[A]], i32 [[B]], i32 4) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw and ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_and_i32_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_and_4(ptr [[A]], i32 [[B]], i32 5) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw and ptr %a, i32 %b seq_cst + ret i32 %res +} + +;define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { +; %res = atomicrmw nand ptr %a, i32 %b monotonic +; ret i32 %res +;} +;define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { +; %res = atomicrmw nand ptr %a, i32 %b acquire +; ret i32 %res +;} +;define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { +; %res = atomicrmw nand ptr %a, i32 %b release +; ret i32 %res +;} +;define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind { +; %res = atomicrmw nand ptr %a, i32 %b acq_rel +; ret i32 %res +;} +;define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind { +; %res = atomicrmw nand ptr %a, i32 %b seq_cst +; ret i32 %res +;} + +define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_or_i32_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_or_4(ptr [[A]], i32 [[B]], i32 0) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw or ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_or_i32_acquire( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_or_4(ptr [[A]], i32 [[B]], i32 2) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw or ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_or_i32_release( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_or_4(ptr [[A]], i32 [[B]], i32 3) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw or ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_or_i32_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_or_4(ptr [[A]], i32 [[B]], i32 4) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw or ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_or_i32_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_or_4(ptr [[A]], i32 [[B]], i32 5) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw or ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_xor_i32_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_xor_4(ptr [[A]], i32 [[B]], i32 0) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_xor_i32_acquire( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_xor_4(ptr [[A]], i32 [[B]], i32 2) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_xor_i32_release( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_xor_4(ptr [[A]], i32 [[B]], i32 3) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_xor_i32_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_xor_4(ptr [[A]], i32 [[B]], i32 4) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_xor_i32_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__atomic_fetch_xor_4(ptr [[A]], i32 [[B]], i32 5) +; CHECK-NEXT: ret i32 [[TMP1]] +; + %res = atomicrmw xor ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_max_i32_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_max_i32_acquire( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_max_i32_release( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_max_i32_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_max_i32_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw max ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_min_i32_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_min_i32_acquire( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_min_i32_release( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_min_i32_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_min_i32_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp sle i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw min ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_umax_i32_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_umax_i32_acquire( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_umax_i32_release( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_umax_i32_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_umax_i32_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw umax ptr %a, i32 %b seq_cst + ret i32 %res +} + +define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_umin_i32_monotonic( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i32 %b monotonic + ret i32 %res +} + +define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_umin_i32_acquire( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 2, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i32 %b acquire + ret i32 %res +} + +define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_umin_i32_release( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 3, i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i32 %b release + ret i32 %res +} + +define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_umin_i32_acq_rel( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 4, i32 2) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i32 %b acq_rel + ret i32 %res +} + +define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: define i32 @atomicrmw_umin_i32_seq_cst( +; CHECK-SAME: ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: br label %[[ATOMICRMW_START:.*]] +; CHECK: [[ATOMICRMW_START]]: +; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], %[[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i32 [[LOADED]], [[B]] +; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 [[LOADED]], i32 [[B]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store i32 [[LOADED]], ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[A]], ptr [[TMP1]], i32 [[NEW]], i32 5, i32 5) +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP5]], 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i32, i1 } [[TMP6]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[ATOMICRMW_END:.*]], label %[[ATOMICRMW_START]] +; CHECK: [[ATOMICRMW_END]]: +; CHECK-NEXT: ret i32 [[NEWLOADED]] +; + %res = atomicrmw umin ptr %a, i32 %b seq_cst + ret i32 %res +} diff --git a/llvm/test/Transforms/AtomicExpand/Xtensa/lit.local.cfg b/llvm/test/Transforms/AtomicExpand/Xtensa/lit.local.cfg new file mode 100644 index 0000000000000..b4b9570cddfe1 --- /dev/null +++ b/llvm/test/Transforms/AtomicExpand/Xtensa/lit.local.cfg @@ -0,0 +1,5 @@ +config.suffixes = [".ll"] + +targets = set(config.root.targets_to_build.split()) +if not "Xtensa" in targets: + config.unsupported = True From dccdeff753d858576437f167e9809f8a83fcfa18 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 6 Aug 2025 14:05:43 +0300 Subject: [PATCH 4/4] [Xtensa] Minor fixes in tests. --- llvm/test/CodeGen/Xtensa/atomic-load-store.ll | 4 ++-- llvm/test/CodeGen/Xtensa/atomic-rmw.ll | 4 ++-- llvm/test/CodeGen/Xtensa/forced-atomics.ll | 4 ++-- llvm/test/Transforms/AtomicExpand/Xtensa/lit.local.cfg | 5 +---- 4 files changed, 7 insertions(+), 10 deletions(-) diff --git a/llvm/test/CodeGen/Xtensa/atomic-load-store.ll b/llvm/test/CodeGen/Xtensa/atomic-load-store.ll index 4f7266195db28..bd843a353da2a 100644 --- a/llvm/test/CodeGen/Xtensa/atomic-load-store.ll +++ b/llvm/test/CodeGen/Xtensa/atomic-load-store.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=xtensa -mattr=+windowed -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA -; RUN: llc -mtriple=xtensa -mattr=+windowed,s32c1i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC +; RUN: llc -mtriple=xtensa -mattr=+windowed < %s | FileCheck %s --check-prefixes=XTENSA +; RUN: llc -mtriple=xtensa -mattr=+windowed,s32c1i < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC define i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; XTENSA-LABEL: atomic_load_i8_unordered: diff --git a/llvm/test/CodeGen/Xtensa/atomic-rmw.ll b/llvm/test/CodeGen/Xtensa/atomic-rmw.ll index c2b0092f226b5..81cb2dd5e8184 100644 --- a/llvm/test/CodeGen/Xtensa/atomic-rmw.ll +++ b/llvm/test/CodeGen/Xtensa/atomic-rmw.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -mtriple=xtensa -mattr=+windowed -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA -; RUN: llc -mtriple=xtensa -mattr=+windowed,s32c1i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC +; RUN: llc -mtriple=xtensa -mattr=+windowed < %s | FileCheck %s --check-prefixes=XTENSA +; RUN: llc -mtriple=xtensa -mattr=+windowed,s32c1i < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; XTENSA-LABEL: atomicrmw_xchg_i8_monotonic: diff --git a/llvm/test/CodeGen/Xtensa/forced-atomics.ll b/llvm/test/CodeGen/Xtensa/forced-atomics.ll index 41a1fbcf50586..eeec87b7ab132 100644 --- a/llvm/test/CodeGen/Xtensa/forced-atomics.ll +++ b/llvm/test/CodeGen/Xtensa/forced-atomics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -mtriple=xtensa -mattr=+windowed -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA -; RUN: llc -mtriple=xtensa -mattr=+windowed,s32c1i -mattr=+forced-atomics -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC +; RUN: llc -mtriple=xtensa -mattr=+windowed < %s | FileCheck %s --check-prefixes=XTENSA +; RUN: llc -mtriple=xtensa -mattr=+windowed,s32c1i -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC define i8 @load8(ptr %p) nounwind { ; XTENSA-LABEL: load8: diff --git a/llvm/test/Transforms/AtomicExpand/Xtensa/lit.local.cfg b/llvm/test/Transforms/AtomicExpand/Xtensa/lit.local.cfg index b4b9570cddfe1..e81bfa773f36a 100644 --- a/llvm/test/Transforms/AtomicExpand/Xtensa/lit.local.cfg +++ b/llvm/test/Transforms/AtomicExpand/Xtensa/lit.local.cfg @@ -1,5 +1,2 @@ -config.suffixes = [".ll"] - -targets = set(config.root.targets_to_build.split()) -if not "Xtensa" in targets: +if not "Xtensa" in config.root.targets: config.unsupported = True