diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
index 11c17c21e189d..63009bdc2643f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
@@ -58,7 +58,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -141,7 +141,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inreg
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -224,7 +224,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -307,7 +307,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inr
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -390,7 +390,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -473,7 +473,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inreg
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -556,7 +556,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -639,7 +639,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inr
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -722,7 +722,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -805,7 +805,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inreg
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -888,7 +888,7 @@ define amdgpu_ps void @struct_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, d
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -971,7 +971,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inr
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
index bba0e08ee6341..d66f50bf04770 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
@@ -735,7 +735,7 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
   %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
   %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
 
@@ -839,7 +839,7 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
   %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
   %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
 
@@ -921,7 +921,7 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
   %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
   %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
 
@@ -995,6 +995,6 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
   %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
   %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
index d59c5a6a2609c..328849a9cea20 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
@@ -11,7 +11,7 @@ declare <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i3
 define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
-  store float %ret, ptr undef
+  store float %ret, ptr poison
   ret void
 }
 
@@ -20,6 +20,6 @@ main_body:
 define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
 main_body:
   %ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
-  store <2 x half> %ret, ptr undef
+  store <2 x half> %ret, ptr poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
index 798a3ee1d75fd..b46a82759f6c5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
@@ -11,7 +11,7 @@ declare <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half>, ptr
 define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
-  store float %ret, ptr undef
+  store float %ret, ptr poison
   ret void
 }
 
@@ -20,6 +20,6 @@ main_body:
 define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
 main_body:
   %ret = call <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
-  store <2 x half> %ret, ptr undef
+  store <2 x half> %ret, ptr poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
index 89daf3ae88cbc..95aa339a05ecd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
@@ -12,7 +12,7 @@ declare <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half>, <4 x
 define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
-  store float %ret, ptr undef
+  store float %ret, ptr poison
   ret void
 }
 
@@ -21,6 +21,6 @@ main_body:
 define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
-  store <2 x half> %ret, ptr undef
+  store <2 x half> %ret, ptr poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
index 5b0b91f983fe6..d55cd96f6d7cd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
@@ -12,7 +12,7 @@ declare <2 x half> @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2f16(<2 x half>,
 define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
-  store float %ret, ptr undef
+  store float %ret, ptr poison
   ret void
 }
 
@@ -21,6 +21,6 @@ main_body:
 define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call <2 x half> @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
-  store <2 x half> %ret, ptr undef
+  store <2 x half> %ret, ptr poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
index dd2f26f7b73a1..ad588ebee2f9e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
@@ -105,7 +105,7 @@ define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) {
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX11-NEXT:    s_endpgm
   %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)
-  store volatile double %result, ptr undef
+  store volatile double %result, ptr poison
   ret void
 }
 
@@ -167,7 +167,7 @@ define amdgpu_kernel void @s_trig_preop_f64_imm(double %a, i32 %b) {
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX11-NEXT:    s_endpgm
   %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)
-  store volatile double %result, ptr undef
+  store volatile double %result, ptr poison
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.r600.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.r600.ll
index f1d6a848848c1..95a3263a58a2b 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.r600.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.r600.ll
@@ -70,7 +70,7 @@ define amdgpu_kernel void @addrspacecast_flat_undef_to_local(ptr addrspace(1) %o
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    CF_END
 ; CHECK-NEXT:    PAD
-  store ptr addrspace(3) addrspacecast (ptr undef to ptr addrspace(3)), ptr addrspace(1) %out
+  store ptr addrspace(3) addrspacecast (ptr poison to ptr addrspace(3)), ptr addrspace(1) %out
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
index 6b935a8768d3d..5d438887cbc91 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
@@ -176,7 +176,7 @@ define void @test_7_7(ptr addrspace(7) %p, ptr addrspace(7) %p1) {
   ret void
 }
 
-@cst = internal addrspace(4) global ptr undef, align 4
+@cst = internal addrspace(4) global ptr poison, align 4
 
 ; CHECK-LABEL: Function: test_8_0
 ; CHECK-DAG: NoAlias:   i8 addrspace(3)* %p, i8* %p1
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
index b34df3ffca264..2ac5c78d8cdb5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
@@ -162,7 +162,7 @@ entry:
   br label %bb.1
 
 bb.1:
-  store float 1.0, ptr undef
+  store float 1.0, ptr poison
   br label %bb.2
 
 bb.2:
diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
index 41e136624d7d2..24b695283de4a 100644
--- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
@@ -68,7 +68,7 @@ define amdgpu_kernel void @max_10_sgprs() #0 {
 ;  %x.3 = call i64 @llvm.amdgcn.dispatch.id()
 ;  %x.4 = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
 ;  %x.5 = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()
-;  store volatile i32 0, ptr undef
+;  store volatile i32 0, ptr poison
 ;  br label %stores
 ;
 ;stores:
@@ -99,7 +99,7 @@ define amdgpu_kernel void @max_10_sgprs() #0 {
 ;                                        ptr addrspace(1) %out3,
 ;                                        ptr addrspace(1) %out4,
 ;                                        i32 %one, i32 %two, i32 %three, i32 %four) #2 {
-;  store volatile i32 0, ptr undef
+;  store volatile i32 0, ptr poison
 ;  %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
 ;  store volatile i32 %x.0, ptr addrspace(1) poison
 ;  %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
index 6b1ecc9dffdb7..2e843048bee16 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
@@ -14,7 +14,7 @@ define amdgpu_kernel void @eq_t(float %x) {
   %s1 = select i1 %c1, i32 56789, i32 1
   %c2 = icmp eq i32 %s1, 56789
   %s2 = select i1 %c2, float 4.0, float 2.0
-  store float %s2, ptr undef, align 4
+  store float %s2, ptr poison, align 4
   ret void
 }
 
@@ -31,7 +31,7 @@ define amdgpu_kernel void @ne_t(float %x) {
   %s1 = select i1 %c1, i32 56789, i32 1
   %c2 = icmp ne i32 %s1, 56789
   %s2 = select i1 %c2, float 4.0, float 2.0
-  store float %s2, ptr undef, align 4
+  store float %s2, ptr poison, align 4
   ret void
 }
 
@@ -48,7 +48,7 @@ define amdgpu_kernel void @eq_f(float %x) {
   %s1 = select i1 %c1, i32 1, i32 56789
   %c2 = icmp eq i32 %s1, 56789
   %s2 = select i1 %c2, float 4.0, float 2.0
-  store float %s2, ptr undef, align 4
+  store float %s2, ptr poison, align 4
   ret void
 }
 
@@ -65,7 +65,7 @@ define amdgpu_kernel void @ne_f(float %x) {
   %s1 = select i1 %c1, i32 1, i32 56789
   %c2 = icmp ne i32 %s1, 56789
   %s2 = select i1 %c2, float 4.0, float 2.0
-  store float %s2, ptr undef, align 4
+  store float %s2, ptr poison, align 4
   ret void
 }
 
@@ -79,6 +79,6 @@ define amdgpu_kernel void @different_constants(float %x) {
   %s1 = select i1 %c1, i32 56789, i32 1
   %c2 = icmp eq i32 %s1, 5678
   %s2 = select i1 %c2, float 4.0, float 2.0
-  store float %s2, ptr undef, align 4
+  store float %s2, ptr poison, align 4
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll b/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
index 7ce49d2966516..873fceedd7b72 100644
--- a/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
@@ -59,7 +59,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -142,7 +142,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inreg
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -225,7 +225,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -308,7 +308,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inr
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -391,7 +391,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -474,7 +474,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inreg
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -557,7 +557,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -640,7 +640,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inr
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -723,7 +723,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -806,7 +806,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inreg
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -889,7 +889,7 @@ define amdgpu_ps void @struct_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, d
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -972,7 +972,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inr
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll b/llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
index 2f20ca8301bd9..f004c19b574a4 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
@@ -10,11 +10,11 @@ define amdgpu_kernel void @test(<4 x i32> %x) #0 {
   %.x.int = bitcast <4 x i32> %x to i128
   %.x.ptr = inttoptr i128 %.x.int to ptr addrspace(8)
   %r1 = tail call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %.x.ptr, i32 %id, i32 0, i32 0, i32 0)
-  store volatile <4 x float> %r1, ptr undef
+  store volatile <4 x float> %r1, ptr poison
   %r2 = tail call <4 x half> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f16(ptr addrspace(8) %.x.ptr, i32 %id, i32 0, i32 0, i32 0)
-  store volatile <4 x half> %r2, ptr undef
+  store volatile <4 x half> %r2, ptr poison
   %r3 = tail call <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32 1, i32 2, <4 x i32> %x, i32 0, i32 0, i32 0)
-  store <4 x i32> %r3, ptr undef
+  store <4 x i32> %r3, ptr poison
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll b/llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
index a15bf7f32dc27..2dbc117f987ef 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
@@ -75,7 +75,7 @@ define amdgpu_kernel void @indirect_call_known_no_special_inputs() {
 bb:
   %cond = load i1, ptr addrspace(4) null
   %tmp = select i1 %cond, ptr @wobble, ptr @snork
-  call void %tmp(ptr undef, i32 undef, ptr undef)
+  call void %tmp(ptr poison, i32 undef, ptr poison)
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
index 33a0ed2caa9e6..b978b13c71c3e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
@@ -421,7 +421,7 @@ main_body:
   %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
   %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
 
@@ -569,7 +569,7 @@ main_body:
   %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
   %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
 
@@ -730,7 +730,7 @@ main_body:
   %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
   %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
 
@@ -880,7 +880,7 @@ main_body:
   %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
   %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll b/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
index 4262cc44a6e74..caff6c29dd709 100644
--- a/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
+++ b/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
@@ -37,20 +37,20 @@ define i64 @lshl_add_u64_vvv(i64 %v, i64 %s, i64 %a) {
 define amdgpu_kernel void @lshl_add_u64_s2v(i64 %v) {
 ; GCN-LABEL: lshl_add_u64_s2v:
 ; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], s[{{[0-9:]+}}], 2, v[{{[0-9:]+}}]
-  %a = load i64, ptr undef
+  %a = load i64, ptr poison
   %shl = shl i64 %v, 2
   %add = add i64 %shl, %a
-  store i64 %add, ptr undef
+  store i64 %add, ptr poison
   ret void
 }
 
 define amdgpu_kernel void @lshl_add_u64_v2s(i64 %a) {
 ; GCN-LABEL: lshl_add_u64_v2s:
 ; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 2, s[{{[0-9:]+}}]
-  %v = load i64, ptr undef
+  %v = load i64, ptr poison
   %shl = shl i64 %v, 2
   %add = add i64 %shl, %a
-  store i64 %add, ptr undef
+  store i64 %add, ptr poison
   ret void
 }
 
@@ -61,7 +61,7 @@ define amdgpu_kernel void @lshl_add_u64_s2s(i64 %v, i64 %a) {
 ; GCN:    s_addc_u32
   %shl = shl i64 %v, 2
   %add = add i64 %shl, %a
-  store i64 %add, ptr undef
+  store i64 %add, ptr poison
   ret void
 }
 
@@ -75,18 +75,18 @@ define i64 @add_u64_vv(i64 %v, i64 %a) {
 define amdgpu_kernel void @add_u64_sv(i64 %v) {
 ; GCN-LABEL: add_u64_sv:
 ; GCN: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1]
-  %a = load i64, ptr undef
+  %a = load i64, ptr poison
   %add = add i64 %v, %a
-  store i64 %add, ptr undef
+  store i64 %add, ptr poison
   ret void
 }
 
 define amdgpu_kernel void @add_u64_vs(i64 %a) {
 ; GCN-LABEL: add_u64_vs:
 ; GCN: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1]
-  %v = load i64, ptr undef
+  %v = load i64, ptr poison
   %add = add i64 %v, %a
-  store i64 %add, ptr undef
+  store i64 %add, ptr poison
   ret void
 }
 
@@ -95,7 +95,7 @@ define amdgpu_kernel void @add_u64_ss(i64 %v, i64 %a) {
 ; GCN: s_add_u32
 ; GCN: s_addc_u32 s1, s1, s3
   %add = add i64 %v, %a
-  store i64 %add, ptr undef
+  store i64 %add, ptr poison
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll b/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
index f3b61bd4d4057..ac8d7d65dfec4 100644
--- a/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
@@ -324,7 +324,7 @@ define amdgpu_ps float @mad_i32_vvv_multiuse(i32 %a, i32 %b, i32 %c) {
 ; GFX11-NEXT:    ; return to shader part epilog
   %mul = mul i32 %a, %b
   %add = add i32 %mul, %c
-  store i32 %mul, ptr undef
+  store i32 %mul, ptr poison
   %cast = bitcast i32 %add to float
   ret float %cast
 }
diff --git a/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll b/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
index 6d4467a541203..3bd8700e33661 100644
--- a/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
@@ -12,7 +12,7 @@ entry:
   br label %if.end
 
 if.end:                                           ; preds = %entry
-  %0 = load i32, ptr undef, align 4
+  %0 = load i32, ptr poison, align 4
   %mul = mul i32 %0, 3
   %cmp13 = icmp eq i32 %mul, 989619
   br i1 %cmp13, label %cleanup.cont, label %if.end15
@@ -125,7 +125,7 @@ if.end5.i400:                                     ; preds = %if.then3.i394, %if.
   %conv612.i397 = sext i8 %7 to i32
   %sub13.i398 = add nsw i32 %conv612.i397, -48
   %cmp714.i399 = icmp ugt i32 %sub13.i398, 9
-  %8 = load i8, ptr undef, align 1
+  %8 = load i8, ptr poison, align 1
   %cmp9.not.i500 = icmp eq i8 0, %8
   br label %land.lhs.true402.critedge
 
diff --git a/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll b/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
index 2c2058473e235..1ecf8f228c625 100644
--- a/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
+++ b/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
@@ -1795,7 +1795,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_1(ptr %p) {
 ; GFX12-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 1
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -1845,7 +1845,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_11bit_max(ptr %p) {
 ; GFX12-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 2047
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -1895,7 +1895,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_12bit_max(ptr %p) {
 ; GFX12-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 4095
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -1975,7 +1975,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_13bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 8191
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2055,7 +2055,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_11bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -2048
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2135,7 +2135,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_12bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -4096
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2215,7 +2215,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_13bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -8192
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2265,7 +2265,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_11bit_max(ptr %p) {
 ; GFX12-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 4095
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2345,7 +2345,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_12bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 8191
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2425,7 +2425,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_13bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 16383
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2505,7 +2505,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_11bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -4096
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2585,7 +2585,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_12bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -8192
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2665,7 +2665,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_13bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -16384
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2760,7 +2760,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split0(ptr %p) {
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 8589936639
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2855,7 +2855,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split1(ptr %p) {
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 8589936640
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -2950,7 +2950,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split0(ptr %p) {
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 8589938687
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -3046,7 +3046,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split1(ptr %p) {
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 8589938688
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -3142,7 +3142,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split0(ptr %p) {
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 8589942783
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -3238,7 +3238,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split1(ptr %p) {
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 8589942784
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -3337,7 +3337,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_neg_high_split0(ptr
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -9223372036854773761
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -3436,7 +3436,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_neg_high_split1(ptr
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -9223372036854773760
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -3535,7 +3535,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_neg_high_split0(ptr
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -9223372036854771713
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -3634,7 +3634,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_neg_high_split1(ptr
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -9223372036854771712
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -3733,7 +3733,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_neg_high_split0(ptr
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -9223372036854767617
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 
@@ -3832,7 +3832,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_neg_high_split1(ptr
 ; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -9223372036854767616
   %load = load volatile i8, ptr %gep, align 1
-  store i8 %load, ptr undef
+  store i8 %load, ptr poison
   ret void
 }
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
diff --git a/llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll b/llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll
index d8cef318f27b9..a55d3c9477282 100644
--- a/llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll
+++ b/llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll
@@ -6,7 +6,7 @@ define amdgpu_kernel void @test_kernel(i32 %n) {
 entry:
   %str = alloca [9 x i8], align 1, addrspace(5)
   %call1 = call i32 (ptr addrspace(4), ...) @printf(ptr addrspace(4) @.str, ptr addrspace(5) %str, i32 %n)
-  %call2 = call <2 x i64> (ptr, i32, i64, i64, i64, i64, i64, i64, i64, i64) @__ockl_hostcall_internal(ptr undef, i32 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9)
+  %call2 = call <2 x i64> (ptr, i32, i64, i64, i64, i64, i64, i64, i64, i64) @__ockl_hostcall_internal(ptr poison, i32 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9)
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/opencl-printf.ll b/llvm/test/CodeGen/AMDGPU/opencl-printf.ll
index 24a6ab1d6c9bd..c80e768c28c71 100644
--- a/llvm/test/CodeGen/AMDGPU/opencl-printf.ll
+++ b/llvm/test/CodeGen/AMDGPU/opencl-printf.ll
@@ -36,7 +36,7 @@
 @printed.str.float.neg0 = private addrspace(4) constant float -0.0, align 4
 @printed.str.float.0 = private addrspace(4) constant float 0.0, align 4
 @printed.str.ptr.null = private addrspace(4) constant ptr null, align 4
-@printed.str.ptr.undef = private addrspace(4) constant ptr undef, align 4
+@printed.str.ptr.undef = private addrspace(4) constant ptr poison, align 4
 @format.str.f = private unnamed_addr addrspace(4) constant [33 x i8] c"%f %f %f %f %f %f %f %f %f %f %f\00", align 1
 @format.str.p = private unnamed_addr addrspace(4) constant [15 x i8] c"%p %p %p %p %p\00", align 1
 @format.str.d = private unnamed_addr addrspace(4) constant [30 x i8] c"%d %d %d %d %d %d %d %d %d %d\00", align 1
diff --git a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
index 2039558b9fc7d..2004e1eb061bf 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
@@ -565,7 +565,7 @@ bb:
   %i13 = fadd <2 x float> zeroinitializer, %shift8
   %i14 = shufflevector <2 x float> %arg, <2 x float> %i13, <2 x i32> <i32 0, i32 2>
   %i15 = fsub <2 x float> %i14, zeroinitializer
-  store <2 x float> %i15, ptr undef
+  store <2 x float> %i15, ptr poison
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll b/llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
index 25a2924bef541..85514e6bfe0a3 100644
--- a/llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
+++ b/llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
@@ -10,7 +10,7 @@
 define void @foo1(i32 %x) #1 {
 entry:
   %cc = icmp eq i32 %x, 0
-  store volatile i1 %cc, ptr undef
+  store volatile i1 %cc, ptr poison
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll b/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
index af6045b6bced9..74d908f43b5ab 100644
--- a/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
@@ -170,10 +170,10 @@ define amdgpu_kernel void @kernel_64_256() #7 {
 define internal void @default_captured_address() {
 ; CHECK-LABEL: define {{[^@]+}}@default_captured_address
 ; CHECK-SAME: () #[[ATTR8:[0-9]+]] {
-; CHECK-NEXT:    store volatile ptr @default_captured_address, ptr undef, align 8
+; CHECK-NEXT:    store volatile ptr @default_captured_address, ptr poison, align 8
 ; CHECK-NEXT:    ret void
 ;
-  store volatile ptr @default_captured_address, ptr undef, align 8
+  store volatile ptr @default_captured_address, ptr poison, align 8
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll b/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
index e76944fb97d56..ae114f3213d8f 100644
--- a/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
+++ b/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
@@ -192,10 +192,10 @@ define amdgpu_kernel void @kernel_3_8() #8 {
 define internal void @default_captured_address() {
 ; CHECK-LABEL: define internal void @default_captured_address
 ; CHECK-SAME: () #[[ATTR9:[0-9]+]] {
-; CHECK-NEXT:    store volatile ptr @default_captured_address, ptr undef, align 8
+; CHECK-NEXT:    store volatile ptr @default_captured_address, ptr poison, align 8
 ; CHECK-NEXT:    ret void
 ;
-  store volatile ptr @default_captured_address, ptr undef, align 8
+  store volatile ptr @default_captured_address, ptr poison, align 8
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll b/llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll
index 44678c70226e0..da31c7681c82e 100644
--- a/llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll
+++ b/llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll
@@ -7,8 +7,8 @@
 ; CHECK-NOT: AMDIC: try folding   call void @llvm.dbg.value
 
 define void @foo(i32 %i) {
-  call void @llvm.lifetime.start.p0(i64 1, ptr undef)
-  call void @llvm.lifetime.end.p0(i64 1, ptr undef)
+  call void @llvm.lifetime.start.p0(i64 1, ptr poison)
+  call void @llvm.lifetime.end.p0(i64 1, ptr poison)
   call void @llvm.dbg.value(metadata i32 undef, metadata !DILocalVariable(name: "1", scope: !2), metadata !DIExpression()), !dbg !3
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll b/llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll
index a266c6385e8c8..7e29f59c4e94e 100644
--- a/llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll
+++ b/llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll
@@ -9,7 +9,7 @@ define amdgpu_kernel void @test_insertelement() #0 {
 entry:
   %alloca = alloca i16, align 4, addrspace(5)
   %in = insertelement <2 x ptr addrspace(5)> poison, ptr addrspace(5) %alloca, i32 0
-  store <2 x ptr addrspace(5)> %in, ptr undef, align 4
+  store <2 x ptr addrspace(5)> %in, ptr poison, align 4
   ret void
 }
 
@@ -20,7 +20,7 @@ define amdgpu_kernel void @test_insertvalue() #0 {
 entry:
   %alloca = alloca i16, align 4, addrspace(5)
   %in = insertvalue { ptr addrspace(5) } poison, ptr addrspace(5) %alloca, 0
-  store { ptr addrspace(5) } %in, ptr undef, align 4
+  store { ptr addrspace(5) } %in, ptr poison, align 4
   ret void
 }
 
@@ -31,7 +31,7 @@ define amdgpu_kernel void @test_insertvalue_array() #0 {
 entry:
   %alloca = alloca i16, align 4, addrspace(5)
   %in = insertvalue [2 x ptr addrspace(5)] poison, ptr addrspace(5) %alloca, 0
-  store [2 x ptr addrspace(5)] %in, ptr undef, align 4
+  store [2 x ptr addrspace(5)] %in, ptr poison, align 4
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/swdev282079.ll b/llvm/test/CodeGen/AMDGPU/swdev282079.ll
index 5dcdb9cade83e..184eb4f6f0baa 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev282079.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev282079.ll
@@ -3,7 +3,7 @@
 define protected amdgpu_kernel void @foo(ptr addrspace(1) %arg, ptr addrspace(1) %arg1) {
 bb:
   %tmp = addrspacecast ptr addrspace(5) null to ptr
-  %tmp2 = call i64 @eggs(ptr undef) #1
+  %tmp2 = call i64 @eggs(ptr poison) #1
   %tmp3 = load ptr, ptr %tmp, align 8
   %tmp4 = getelementptr inbounds i64, ptr %tmp3, i64 undef
   store i64 %tmp2, ptr %tmp4, align 8
diff --git a/llvm/test/CodeGen/AMDGPU/swdev373493.ll b/llvm/test/CodeGen/AMDGPU/swdev373493.ll
index 5917522f2bfa0..caf58823aa6d5 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev373493.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev373493.ll
@@ -60,8 +60,8 @@ bb:
   ]
 
 bb7:                                              ; preds = %bb
-  %tmp = load ptr, ptr undef, align 8
-  tail call fastcc void @eggs(ptr noundef addrspacecast (ptr addrspace(4) getelementptr inbounds ([4096 x i64], ptr addrspace(4) @global, i64 0, i64 243) to ptr), ptr %tmp, ptr undef, ptr noundef nonnull align 8 dereferenceable(24) %arg2, ptr noundef %arg3, ptr noundef %arg4, ptr noundef %arg5)
+  %tmp = load ptr, ptr poison, align 8
+  tail call fastcc void @eggs(ptr noundef addrspacecast (ptr addrspace(4) getelementptr inbounds ([4096 x i64], ptr addrspace(4) @global, i64 0, i64 243) to ptr), ptr %tmp, ptr poison, ptr noundef nonnull align 8 dereferenceable(24) %arg2, ptr noundef %arg3, ptr noundef %arg4, ptr noundef %arg5)
   br label %bb9
 
 bb8:                                              ; preds = %bb
diff --git a/llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll b/llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll
index 6bd9f1cc70b41..094ca2ad0e89d 100644
--- a/llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll
+++ b/llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll
@@ -48,7 +48,7 @@ define void @test(i1 %c0) #1 {
 
   unreach.blk:                                      ; preds = %preheader.blk, %pre.false.blk
     %phi.val = phi i32 [ %call.pre.false, %pre.false.blk ], [ poison, %preheader.blk ]
-    store i32 %phi.val, ptr undef
+    store i32 %phi.val, ptr poison
     unreachable
 
   exit:                                             ; preds = %switch.blk