diff --git a/llvm/include/llvm/CodeGen/MachineFrameInfo.h b/llvm/include/llvm/CodeGen/MachineFrameInfo.h index 213b7ec6b3fbf..cf9c757a9721f 100644 --- a/llvm/include/llvm/CodeGen/MachineFrameInfo.h +++ b/llvm/include/llvm/CodeGen/MachineFrameInfo.h @@ -32,7 +32,7 @@ class AllocaInst; /// Callee saved reg can also be saved to a different register rather than /// on the stack by setting DstReg instead of FrameIdx. class CalleeSavedInfo { - Register Reg; + MCRegister Reg; union { int FrameIdx; unsigned DstReg; @@ -58,7 +58,7 @@ class CalleeSavedInfo { explicit CalleeSavedInfo(unsigned R, int FI = 0) : Reg(R), FrameIdx(FI) {} // Accessors. - Register getReg() const { return Reg; } + MCRegister getReg() const { return Reg; } int getFrameIdx() const { return FrameIdx; } unsigned getDstReg() const { return DstReg; } void setFrameIdx(int FI) { diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp index 2ba17e46be5a6..f5677bcd6b5f9 100644 --- a/llvm/lib/CodeGen/LivePhysRegs.cpp +++ b/llvm/lib/CodeGen/LivePhysRegs.cpp @@ -301,7 +301,7 @@ void llvm::recomputeLivenessFlags(MachineBasicBlock &MBB) { // the last instruction in the block. if (MI.isReturn() && MFI.isCalleeSavedInfoValid()) { for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) { - if (Info.getReg() == Reg) { + if (Info.getReg() == Reg.asMCReg()) { IsNotLive = !Info.isRestored(); break; } diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index eb8929cae069e..c582dc527c017 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -481,7 +481,7 @@ static void assignCalleeSavedSpillSlots(MachineFunction &F, if (CS.isSpilledToReg()) continue; - unsigned Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); int FrameIdx; @@ -570,7 +570,7 @@ static void updateLiveness(MachineFunction &MF) { MachineRegisterInfo &MRI = MF.getRegInfo(); for (const CalleeSavedInfo &I : CSI) { for (MachineBasicBlock *MBB : Visited) { - MCPhysReg Reg = I.getReg(); + MCRegister Reg = I.getReg(); // Add the callee-saved register as live-in. // It's killed at the spill. if (!MRI.isReserved(Reg) && !MBB->isLiveIn(Reg)) @@ -605,7 +605,7 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock, if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) { for (const CalleeSavedInfo &CS : CSI) { // Insert the spill to the stack frame. - unsigned Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); if (CS.isSpilledToReg()) { BuildMI(SaveBlock, I, DebugLoc(), @@ -634,7 +634,7 @@ static void insertCSRRestores(MachineBasicBlock &RestoreBlock, if (!TFI->restoreCalleeSavedRegisters(RestoreBlock, I, CSI, TRI)) { for (const CalleeSavedInfo &CI : reverse(CSI)) { - unsigned Reg = CI.getReg(); + MCRegister Reg = CI.getReg(); if (CI.isSpilledToReg()) { BuildMI(RestoreBlock, I, DebugLoc(), TII.get(TargetOpcode::COPY), Reg) .addReg(CI.getDstReg(), getKillRegState(true)); diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index d118022395762..1761f58faf0fe 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -655,7 +655,7 @@ void AArch64FrameLowering::emitCalleeSavedSVELocations( // Not all unwinders may know about SVE registers, so assume the lowest // common demoninator. assert(!Info.isSpilledToReg() && "Spilling to registers not implemented"); - unsigned Reg = Info.getReg(); + MCRegister Reg = Info.getReg(); if (!static_cast(TRI).regNeedsCFI(Reg, Reg)) continue; @@ -716,7 +716,7 @@ void AArch64FrameLowering::resetCFIToInitialState( const std::vector &CSI = MF.getFrameInfo().getCalleeSavedInfo(); for (const auto &Info : CSI) { - unsigned Reg = Info.getReg(); + MCRegister Reg = Info.getReg(); if (!TRI.regNeedsCFI(Reg, Reg)) continue; insertCFISameValue(CFIDesc, MF, MBB, InsertPt, @@ -744,7 +744,7 @@ static void emitCalleeSavedRestores(MachineBasicBlock &MBB, (MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector)) continue; - unsigned Reg = Info.getReg(); + MCRegister Reg = Info.getReg(); if (SVE && !static_cast(TRI).regNeedsCFI(Reg, Reg)) continue; @@ -3051,7 +3051,7 @@ static void computeCalleeSaveRegisterPairs( int Scale = TRI->getSpillSize(*RPI.RC); // Add the next reg to the pair if it is in the same register class. if (unsigned(i + RegInc) < Count && !AFI->hasStackHazardSlotIndex()) { - Register NextReg = CSI[i + RegInc].getReg(); + MCRegister NextReg = CSI[i + RegInc].getReg(); bool IsFirst = i == FirstReg; switch (RPI.Type) { case RegPairInfo::GPR: @@ -3986,7 +3986,7 @@ bool AArch64FrameLowering::assignCalleeSavedSpillSlots( Register LastReg = 0; int HazardSlotIndex = std::numeric_limits::max(); for (auto &CS : CSI) { - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); // Create a hazard slot as we switch between GPR and FPR CSRs. diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp index 8fd34325bb00d..52b362875b4ef 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -49,8 +49,8 @@ AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT, unsigned HwMode) /// callee-saves required by the base ABI. For the SVE registers z8-z15 only the /// lower 64-bits (d8-d15) need to be saved. The lower 64-bits subreg is /// returned in \p RegToUseForCFI. -bool AArch64RegisterInfo::regNeedsCFI(unsigned Reg, - unsigned &RegToUseForCFI) const { +bool AArch64RegisterInfo::regNeedsCFI(MCRegister Reg, + MCRegister &RegToUseForCFI) const { if (AArch64::PPRRegClass.contains(Reg)) return false; diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h index 898a509f75908..ddee0d6a0dc38 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h @@ -140,7 +140,7 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo { const LiveRegMatrix *Matrix) const override; unsigned getLocalAddressRegister(const MachineFunction &MF) const; - bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const; + bool regNeedsCFI(MCRegister Reg, MCRegister &RegToUseForCFI) const; /// SrcRC and DstRC will be morphed into NewRC if this returns true bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 060db477a59f8..ce21f8963fe88 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -1719,11 +1719,12 @@ bool SIFrameLowering::assignCalleeSavedSpillSlots( NumModifiedRegs++; for (auto &CS : CSI) { - if (CS.getReg() == FramePtrReg && SGPRForFPSaveRestoreCopy) { + if (CS.getReg() == FramePtrReg.asMCReg() && SGPRForFPSaveRestoreCopy) { CS.setDstReg(SGPRForFPSaveRestoreCopy); if (--NumModifiedRegs) break; - } else if (CS.getReg() == BasePtrReg && SGPRForBPSaveRestoreCopy) { + } else if (CS.getReg() == BasePtrReg.asMCReg() && + SGPRForBPSaveRestoreCopy) { CS.setDstReg(SGPRForBPSaveRestoreCopy); if (--NumModifiedRegs) break; diff --git a/llvm/lib/Target/ARC/ARCFrameLowering.cpp b/llvm/lib/Target/ARC/ARCFrameLowering.cpp index 95054eac8c4fa..9f6a79e3210c4 100644 --- a/llvm/lib/Target/ARC/ARCFrameLowering.cpp +++ b/llvm/lib/Target/ARC/ARCFrameLowering.cpp @@ -219,7 +219,7 @@ void ARCFrameLowering::emitPrologue(MachineFunction &MF, } // CFI for the rest of the registers. for (const auto &Entry : CSI) { - unsigned Reg = Entry.getReg(); + MCRegister Reg = Entry.getReg(); int FI = Entry.getFrameIdx(); // Skip BLINK and FP. if ((hasFP(MF) && Reg == ARC::FP) || (MFI.hasCalls() && Reg == ARC::BLINK)) diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 3393c55f1639d..6e885ab574cea 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -952,13 +952,13 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF, SpillArea FramePtrSpillArea = SpillArea::GPRCS1; bool BeforeFPPush = true; for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); int FI = I.getFrameIdx(); SpillArea Area = getSpillArea(Reg, PushPopSplit, AFI->getNumAlignedDPRCS2Regs(), RegInfo); - if (Reg == FramePtr) { + if (Reg == FramePtr.asMCReg()) { FramePtrSpillFI = FI; FramePtrSpillArea = Area; } @@ -1280,7 +1280,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF, // recording where each register ended up: if (!NeedsWinCFI) { for (const auto &Entry : reverse(CSI)) { - Register Reg = Entry.getReg(); + MCRegister Reg = Entry.getReg(); int FI = Entry.getFrameIdx(); MachineBasicBlock::iterator CFIPos; switch (getSpillArea(Reg, PushPopSplit, AFI->getNumAlignedDPRCS2Regs(), @@ -1668,7 +1668,7 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, while (i != 0) { unsigned LastReg = 0; for (; i != 0; --i) { - Register Reg = CSI[i-1].getReg(); + MCRegister Reg = CSI[i-1].getReg(); if (!Func(Reg)) continue; @@ -1761,7 +1761,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, bool DeleteRet = false; for (; i != 0; --i) { CalleeSavedInfo &Info = CSI[i-1]; - Register Reg = Info.getReg(); + MCRegister Reg = Info.getReg(); if (!Func(Reg)) continue; @@ -3003,7 +3003,7 @@ bool ARMFrameLowering::assignCalleeSavedSpillSlots( // LR, R7, R6, R5, R4, , R11, R10, R9, R8, D15-D8 CSI.insert(find_if(CSI, [=](const auto &CS) { - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); return Reg == ARM::R10 || Reg == ARM::R11 || Reg == ARM::R8 || Reg == ARM::R9 || ARM::DPRRegClass.contains(Reg); @@ -3021,7 +3021,7 @@ bool ARMFrameLowering::assignCalleeSavedSpillSlots( "address."); CSI.insert(find_if(CSI, [=](const auto &CS) { - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); return Reg != ARM::LR; }), CalleeSavedInfo(ARM::R12)); diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp index faa0352507fba..a69e307a5da20 100644 --- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -210,9 +210,9 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF, bool HasFrameRecordArea = hasFP(MF) && ARM::hGPRRegClass.contains(FramePtr); for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); int FI = I.getFrameIdx(); - if (Reg == FramePtr) + if (Reg == FramePtr.asMCReg()) FramePtrSpillFI = FI; switch (Reg) { case ARM::R11: @@ -371,7 +371,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF, .setMIFlags(MachineInstr::FrameSetup); } for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); int FI = I.getFrameIdx(); switch (Reg) { case ARM::R8: @@ -403,7 +403,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF, if (GPRCS2Size > 0) { MachineBasicBlock::iterator Pos = std::next(GPRCS2Push); for (auto &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); int FI = I.getFrameIdx(); switch (Reg) { case ARM::R8: @@ -432,8 +432,8 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF, // at this point in the prologue, so pick one. unsigned ScratchRegister = ARM::NoRegister; for (auto &I : CSI) { - Register Reg = I.getReg(); - if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) { + MCRegister Reg = I.getReg(); + if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr.asMCReg())) { ScratchRegister = Reg; break; } @@ -552,8 +552,8 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, unsigned ScratchRegister = ARM::NoRegister; bool HasFP = hasFP(MF); for (auto &I : MFI.getCalleeSavedInfo()) { - Register Reg = I.getReg(); - if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) { + MCRegister Reg = I.getReg(); + if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr.asMCReg())) { ScratchRegister = Reg; break; } @@ -1118,8 +1118,8 @@ bool Thumb1FrameLowering::spillCalleeSavedRegisters( std::set FrameRecord; std::set SpilledGPRs; for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); - if (NeedsFrameRecordPush && (Reg == FPReg || Reg == ARM::LR)) + MCRegister Reg = I.getReg(); + if (NeedsFrameRecordPush && (Reg == FPReg.asMCReg() || Reg == ARM::LR)) FrameRecord.insert(Reg); else SpilledGPRs.insert(Reg); @@ -1206,8 +1206,8 @@ bool Thumb1FrameLowering::restoreCalleeSavedRegisters( std::set FrameRecord; std::set SpilledGPRs; for (CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); - if (NeedsFrameRecordPop && (Reg == FPReg || Reg == ARM::LR)) + MCRegister Reg = I.getReg(); + if (NeedsFrameRecordPop && (Reg == FPReg.asMCReg() || Reg == ARM::LR)) FrameRecord.insert(Reg); else SpilledGPRs.insert(Reg); diff --git a/llvm/lib/Target/AVR/AVRFrameLowering.cpp b/llvm/lib/Target/AVR/AVRFrameLowering.cpp index ea94a90580c9c..b919be3d4466d 100644 --- a/llvm/lib/Target/AVR/AVRFrameLowering.cpp +++ b/llvm/lib/Target/AVR/AVRFrameLowering.cpp @@ -254,7 +254,7 @@ bool AVRFrameLowering::spillCalleeSavedRegisters( AVRMachineFunctionInfo *AVRFI = MF.getInfo(); for (const CalleeSavedInfo &I : llvm::reverse(CSI)) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); bool IsNotLiveIn = !MBB.isLiveIn(Reg); // Check if Reg is a sub register of a 16-bit livein register, and then @@ -302,7 +302,7 @@ bool AVRFrameLowering::restoreCalleeSavedRegisters( const TargetInstrInfo &TII = *STI.getInstrInfo(); for (const CalleeSavedInfo &CCSI : CSI) { - Register Reg = CCSI.getReg(); + MCRegister Reg = CCSI.getReg(); assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && "Invalid register size"); diff --git a/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp b/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp index f29caafe39526..e81bb4745faff 100644 --- a/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp +++ b/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp @@ -135,7 +135,7 @@ void CSKYFrameLowering::emitPrologue(MachineFunction &MF, // directives. for (const auto &Entry : CSI) { int64_t Offset = MFI.getObjectOffset(Entry.getFrameIdx()); - Register Reg = Entry.getReg(); + MCRegister Reg = Entry.getReg(); unsigned Num = TRI->getRegSizeInBits(Reg, MRI) / 32; for (unsigned i = 0; i < Num; i++) { @@ -474,7 +474,7 @@ bool CSKYFrameLowering::spillCalleeSavedRegisters( for (auto &CS : CSI) { // Insert the spill to the stack frame. - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI, Register()); @@ -496,7 +496,7 @@ bool CSKYFrameLowering::restoreCalleeSavedRegisters( DL = MI->getDebugLoc(); for (auto &CS : reverse(CSI)) { - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI, Register()); diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index eddf7500f0974..c2e878d338e2f 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1409,7 +1409,7 @@ bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB, } for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); // Add live in registers. We treat eh_return callee saved register r0 - r3 // specially. They are not really callee saved registers as they are not // supposed to be killed. @@ -1478,7 +1478,7 @@ bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB, } for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); int FI = I.getFrameIdx(); HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI, Register()); @@ -1512,7 +1512,7 @@ void HexagonFrameLowering::processFunctionBeforeFrameFinalized( return; // Set the physical aligned-stack base address register. - Register AP = 0; + MCRegister AP; if (const MachineInstr *AI = getAlignaInstr(MF)) AP = AI->getOperand(0).getReg(); auto &HMFI = *MF.getInfo(); @@ -2588,7 +2588,7 @@ bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF, // a contiguous block starting from D8. BitVector Regs(Hexagon::NUM_TARGET_REGS); for (const CalleeSavedInfo &I : CSI) { - Register R = I.getReg(); + MCRegister R = I.getReg(); if (!Hexagon::DoubleRegsRegClass.contains(R)) return true; Regs[R] = true; diff --git a/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp index 4b7b5483f5b81..ac5e7f3891c72 100644 --- a/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp @@ -438,7 +438,7 @@ bool LoongArchFrameLowering::spillCalleeSavedRegisters( // Insert the spill to the stack frame. for (auto &CS : CSI) { - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); // If the register is RA and the return address is taken by method // LoongArchTargetLowering::lowerRETURNADDR, don't set kill flag. bool IsKill = diff --git a/llvm/lib/Target/M68k/M68kFrameLowering.cpp b/llvm/lib/Target/M68k/M68kFrameLowering.cpp index 721395027b512..ae2bb975bc9d6 100644 --- a/llvm/lib/Target/M68k/M68kFrameLowering.cpp +++ b/llvm/lib/Target/M68k/M68kFrameLowering.cpp @@ -462,7 +462,7 @@ void M68kFrameLowering::emitPrologueCalleeSavedFrameMoves( // Calculate offsets. for (const auto &I : CSI) { int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); BuildCFI(MBB, MBBI, DL, @@ -837,7 +837,7 @@ bool M68kFrameLowering::spillCalleeSavedRegisters( unsigned Mask = 0; for (const auto &Info : CSI) { FI = std::max(FI, Info.getFrameIdx()); - Register Reg = Info.getReg(); + MCRegister Reg = Info.getReg(); unsigned Shift = MRI.getSpillRegisterOrder(Reg); Mask |= 1 << Shift; } @@ -851,7 +851,7 @@ bool M68kFrameLowering::spillCalleeSavedRegisters( const MachineFunction &MF = *MBB.getParent(); const MachineRegisterInfo &RI = MF.getRegInfo(); for (const auto &Info : CSI) { - Register Reg = Info.getReg(); + MCRegister Reg = Info.getReg(); bool IsLiveIn = RI.isLiveIn(Reg); if (!IsLiveIn) MBB.addLiveIn(Reg); @@ -872,7 +872,7 @@ bool M68kFrameLowering::restoreCalleeSavedRegisters( unsigned Mask = 0; for (const auto &Info : CSI) { FI = std::max(FI, Info.getFrameIdx()); - Register Reg = Info.getReg(); + MCRegister Reg = Info.getReg(); unsigned Shift = MRI.getSpillRegisterOrder(Reg); Mask |= 1 << Shift; } diff --git a/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp b/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp index 76d6e8a324ae5..39f4324286efd 100644 --- a/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp @@ -64,7 +64,7 @@ void MSP430FrameLowering::emitCalleeSavedFrameMoves( // Calculate offsets. for (const CalleeSavedInfo &I : CSI) { int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); if (IsPrologue) { @@ -324,7 +324,7 @@ bool MSP430FrameLowering::spillCalleeSavedRegisters( MFI->setCalleeSavedFrameSize(CSI.size() * 2); for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); // Add the callee-saved register as live-in. It's killed at the spill. MBB.addLiveIn(Reg); BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) diff --git a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp index f1dce3f2a6f2a..576b93701f356 100644 --- a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp +++ b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp @@ -70,7 +70,7 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF, for (const CalleeSavedInfo &I : CSI) { int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); unsigned DReg = MRI->getDwarfRegNum(Reg, true); unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, DReg, Offset)); @@ -120,7 +120,7 @@ bool Mips16FrameLowering::spillCalleeSavedRegisters( // method MipsTargetLowering::lowerRETURNADDR. // It's killed at the spill, unless the register is RA and return address // is taken. - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA) && MF->getFrameInfo().isReturnAddressTaken(); if (!IsRAAndRetAddrIsTaken) diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp index 04f3a974f5408..e9ac94183066f 100644 --- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -452,7 +452,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, // directives. for (const CalleeSavedInfo &I : CSI) { int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); // If Reg is a double precision register, emit two cfa_offsets, // one for each of the paired single precision registers. @@ -801,7 +801,7 @@ bool MipsSEFrameLowering::spillCalleeSavedRegisters( // method MipsTargetLowering::lowerRETURNADDR. // It's killed at the spill, unless the register is RA and return address // is taken. - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64) && MF->getFrameInfo().isReturnAddressTaken(); if (!IsRAAndRetAddrIsTaken) diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index f88af657c8ad5..7a912be290b07 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -1186,7 +1186,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF, // CFA. const std::vector &CSI = MFI.getCalleeSavedInfo(); for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just @@ -2108,7 +2108,7 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, SmallVector VRegs; for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); assert((!MF.getInfo()->mustSaveTOC() || (Reg != PPC::X2 && Reg != PPC::R2)) && "Not expecting to try to spill R2 in a function that must save TOC"); @@ -2343,7 +2343,7 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots( // in our CalleSaveInfo vector. for (auto &CalleeSaveReg : CSI) { - MCPhysReg Reg = CalleeSaveReg.getReg(); + MCRegister Reg = CalleeSaveReg.getReg(); MCRegister Lower = RegInfo->getSubReg(Reg, PPC::sub_32); MCRegister Higher = RegInfo->getSubReg(Reg, PPC::sub_32_hi_phony); @@ -2380,7 +2380,7 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots( if (BVAllocatable.none()) return false; - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); if (!PPC::G8RCRegClass.contains(Reg)) { AllSpilledToReg = false; @@ -2437,7 +2437,7 @@ bool PPCFrameLowering::spillCalleeSavedRegisters( } for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); // CR2 through CR4 are the nonvolatile CR fields. bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; @@ -2623,7 +2623,7 @@ bool PPCFrameLowering::restoreCalleeSavedRegisters( --BeforeI; for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - Register Reg = CSI[i].getReg(); + MCRegister Reg = CSI[i].getReg(); if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC) continue; diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index 6abf45591d78e..32834a6b84f10 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -43,7 +43,7 @@ class CFISaveRegisterEmitter { const DebugLoc &DL, const CalleeSavedInfo &CS) const { int FrameIdx = CS.getFrameIdx(); int64_t Offset = MFI.getObjectOffset(FrameIdx); - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( nullptr, RI.getDwarfRegNum(Reg, true), Offset)); BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) @@ -61,7 +61,7 @@ class CFIRestoreRegisterEmitter { void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII, const DebugLoc &DL, const CalleeSavedInfo &CS) const { - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true))); BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) @@ -135,7 +135,6 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, return; const llvm::RISCVRegisterInfo *TRI = STI.getRegisterInfo(); - Register RAReg = TRI->getRARegister(); // Do not save RA to the SCS if it's not saved to the regular stack, // i.e. RA is not at risk of being overwritten. @@ -200,8 +199,6 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, if (!HasHWShadowStack && !HasSWShadowStack) return; - Register RAReg = STI.getRegisterInfo()->getRARegister(); - // See emitSCSPrologue() above. std::vector &CSI = MF.getFrameInfo().getCalleeSavedInfo(); if (llvm::none_of( @@ -250,7 +247,7 @@ static int getLibCallID(const MachineFunction &MF, if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF)) return -1; - Register MaxReg; + MCRegister MaxReg; for (auto &CS : CSI) // assignCalleeSavedSpillSlots assigns negative frame indexes to // registers which can be saved by libcall. @@ -372,7 +369,7 @@ getPushPopEncodingAndNum(const Register MaxReg) { // Get the max reg of Push/Pop for restoring callee saved registers. static Register getMaxPushPopReg(const MachineFunction &MF, const std::vector &CSI) { - Register MaxPushPopReg = RISCV::NoRegister; + MCRegister MaxPushPopReg; for (auto &CS : CSI) { if (llvm::find_if(FixedCSRFIMap, [&](auto P) { return P.first == CS.getReg(); @@ -1809,7 +1806,7 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots( const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); for (auto &CS : CSI) { - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); unsigned Size = RegInfo->getSpillSize(*RC); @@ -1911,7 +1908,7 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters( auto storeRegsToStackSlots = [&](decltype(UnmanagedCSI) CSInfo) { for (auto &CS : CSInfo) { // Insert the spill to the stack frame. - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(), RC, TRI, Register(), @@ -2023,7 +2020,7 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters( auto loadRegFromStackSlot = [&](decltype(UnmanagedCSI) CSInfo) { for (auto &CS : CSInfo) { - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI, Register(), MachineInstr::FrameDestroy); diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp index 54a950ee213f4..9561ea544b270 100644 --- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp @@ -172,7 +172,7 @@ bool SystemZELFFrameLowering::assignCalleeSavedSpillSlots( unsigned HighGPR = SystemZ::R15D; int StartSPOffset = SystemZMC::ELFCallFrameSize; for (auto &CS : CSI) { - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); int Offset = getRegSpillOffset(MF, Reg); if (Offset) { if (SystemZ::GR64BitRegClass.contains(Reg) && StartSPOffset > Offset) { @@ -213,7 +213,7 @@ bool SystemZELFFrameLowering::assignCalleeSavedSpillSlots( for (auto &CS : CSI) { if (CS.getFrameIdx() != INT32_MAX) continue; - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); unsigned Size = TRI->getSpillSize(*RC); CurrOffset -= Size; @@ -341,7 +341,7 @@ bool SystemZELFFrameLowering::spillCalleeSavedRegisters( // Make sure all call-saved GPRs are included as operands and are // marked as live on entry. for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (SystemZ::GR64BitRegClass.contains(Reg)) addSavedGPR(MBB, MIB, Reg, true); } @@ -354,7 +354,7 @@ bool SystemZELFFrameLowering::spillCalleeSavedRegisters( // Save FPRs/VRs in the normal TargetInstrInfo way. for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (SystemZ::FP64BitRegClass.contains(Reg)) { MBB.addLiveIn(Reg); TII->storeRegToStackSlot(MBB, MBBI, Reg, true, I.getFrameIdx(), @@ -384,7 +384,7 @@ bool SystemZELFFrameLowering::restoreCalleeSavedRegisters( // Restore FPRs/VRs in the normal TargetInstrInfo way. for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (SystemZ::FP64BitRegClass.contains(Reg)) TII->loadRegFromStackSlot(MBB, MBBI, Reg, I.getFrameIdx(), &SystemZ::FP64BitRegClass, TRI, Register()); @@ -416,7 +416,7 @@ bool SystemZELFFrameLowering::restoreCalleeSavedRegisters( // Do a second scan adding regs as being defined by instruction for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (Reg != RestoreGPRs.LowGPR && Reg != RestoreGPRs.HighGPR && SystemZ::GR64BitRegClass.contains(Reg)) MIB.addReg(Reg, RegState::ImplicitDefine); @@ -570,7 +570,7 @@ void SystemZELFFrameLowering::emitPrologue(MachineFunction &MF, // Add CFI for the GPR saves. for (auto &Save : CSI) { - Register Reg = Save.getReg(); + MCRegister Reg = Save.getReg(); if (SystemZ::GR64BitRegClass.contains(Reg)) { int FI = Save.getFrameIdx(); int64_t Offset = MFFrame.getObjectOffset(FI); @@ -650,7 +650,7 @@ void SystemZELFFrameLowering::emitPrologue(MachineFunction &MF, // Skip over the FPR/VR saves. SmallVector CFIIndexes; for (auto &Save : CSI) { - Register Reg = Save.getReg(); + MCRegister Reg = Save.getReg(); if (SystemZ::FP64BitRegClass.contains(Reg)) { if (MBBI != MBB.end() && (MBBI->getOpcode() == SystemZ::STD || @@ -1012,7 +1012,7 @@ bool SystemZXPLINKFrameLowering::assignCalleeSavedSpillSlots( int FPSI = MFI->getFramePointerSaveIndex(); for (auto &CS : CSI) { - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); int Offset = RegSpillOffsets[Reg]; if (Offset >= 0) { if (GRRegClass.contains(Reg)) { @@ -1041,7 +1041,7 @@ bool SystemZXPLINKFrameLowering::assignCalleeSavedSpillSlots( MFFrame.setStackID(FrameIdx, TargetStackID::NoAlloc); } } else { - Register Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); Align Alignment = TRI->getSpillAlign(*RC); unsigned Size = TRI->getSpillSize(*RC); @@ -1115,7 +1115,7 @@ bool SystemZXPLINKFrameLowering::spillCalleeSavedRegisters( // marked as live on entry. auto &GRRegClass = SystemZ::GR64BitRegClass; for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (GRRegClass.contains(Reg)) addSavedGPR(MBB, MIB, Reg, true); } @@ -1123,7 +1123,7 @@ bool SystemZXPLINKFrameLowering::spillCalleeSavedRegisters( // Spill FPRs to the stack in the normal TargetInstrInfo way for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (SystemZ::FP64BitRegClass.contains(Reg)) { MBB.addLiveIn(Reg); TII->storeRegToStackSlot(MBB, MBBI, Reg, true, I.getFrameIdx(), @@ -1156,7 +1156,7 @@ bool SystemZXPLINKFrameLowering::restoreCalleeSavedRegisters( // Restore FPRs in the normal TargetInstrInfo way. for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (SystemZ::FP64BitRegClass.contains(Reg)) TII->loadRegFromStackSlot(MBB, MBBI, Reg, I.getFrameIdx(), &SystemZ::FP64BitRegClass, TRI, Register()); @@ -1190,7 +1190,7 @@ bool SystemZXPLINKFrameLowering::restoreCalleeSavedRegisters( // Do a second scan adding regs as being defined by instruction for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (Reg > RestoreGPRs.LowGPR && Reg < RestoreGPRs.HighGPR) MIB.addReg(Reg, RegState::ImplicitDefine); } diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp index 10fb6994b51b6..68bf1d09d1093 100644 --- a/llvm/lib/Target/X86/X86FrameLowering.cpp +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp @@ -528,7 +528,7 @@ void X86FrameLowering::emitCalleeSavedFrameMoves( // Calculate offsets. for (const CalleeSavedInfo &I : CSI) { int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); if (IsPrologue) { @@ -2935,7 +2935,7 @@ bool X86FrameLowering::assignCalleeSavedSpillSlots( // Assign slots for GPRs. It increases frame size. for (CalleeSavedInfo &I : llvm::reverse(CSI)) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg)) continue; @@ -2973,7 +2973,7 @@ bool X86FrameLowering::assignCalleeSavedSpillSlots( // Assign slots for XMMs. for (CalleeSavedInfo &I : llvm::reverse(CSI)) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg)) continue; @@ -3044,12 +3044,12 @@ bool X86FrameLowering::spillCalleeSavedRegisters( }; for (auto RI = CSI.rbegin(), RE = CSI.rend(); RI != RE; ++RI) { - Register Reg = RI->getReg(); + MCRegister Reg = RI->getReg(); if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg)) continue; if (X86FI->isCandidateForPush2Pop2(Reg)) { - Register Reg2 = (++RI)->getReg(); + MCRegister Reg2 = (++RI)->getReg(); BuildMI(MBB, MI, DL, TII.get(getPUSH2Opcode(STI))) .addReg(Reg, UpdateLiveInGetKillRegState(Reg)) .addReg(Reg2, UpdateLiveInGetKillRegState(Reg2)) @@ -3072,7 +3072,7 @@ bool X86FrameLowering::spillCalleeSavedRegisters( // Make XMM regs spilled. X86 does not have ability of push/pop XMM. // It can be done by spilling XMMs to stack frame. for (const CalleeSavedInfo &I : llvm::reverse(CSI)) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg)) continue; @@ -3148,7 +3148,7 @@ bool X86FrameLowering::restoreCalleeSavedRegisters( // Reload XMMs from stack frame. for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg)) continue; @@ -3174,7 +3174,7 @@ bool X86FrameLowering::restoreCalleeSavedRegisters( // POP GPRs. for (auto I = CSI.begin(), E = CSI.end(); I != E; ++I) { - Register Reg = I->getReg(); + MCRegister Reg = I->getReg(); if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg)) continue; diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp index 01896bf98cc1f..cdb5186d23d3c 100644 --- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp @@ -425,7 +425,7 @@ bool XCoreFrameLowering::spillCalleeSavedRegisters( DL = MI->getDebugLoc(); for (const CalleeSavedInfo &I : CSI) { - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) && "LR & FP are always handled in emitPrologue"); @@ -453,7 +453,7 @@ bool XCoreFrameLowering::restoreCalleeSavedRegisters( if (!AtStart) --BeforeI; for (const CalleeSavedInfo &CSR : CSI) { - Register Reg = CSR.getReg(); + MCRegister Reg = CSR.getReg(); assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) && "LR & FP are always handled in emitEpilogue"); diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index f8ed5dd5e757a..3fc0c47c528d3 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -98,7 +98,7 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF, // directives. for (const auto &I : CSI) { int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); - Register Reg = I.getReg(); + MCRegister Reg = I.getReg(); unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( nullptr, MRI->getDwarfRegNum(Reg, 1), Offset)); @@ -203,7 +203,7 @@ bool XtensaFrameLowering::spillCalleeSavedRegisters( // method XtensaTargetLowering::LowerRETURNADDR. // It's killed at the spill, unless the register is RA and return address // is taken. - Register Reg = CSI[i].getReg(); + MCRegister Reg = CSI[i].getReg(); bool IsA0AndRetAddrIsTaken = (Reg == Xtensa::A0) && MF->getFrameInfo().isReturnAddressTaken(); if (!IsA0AndRetAddrIsTaken)