From a23a670a297e511025bc562b621d9f67bd25503c Mon Sep 17 00:00:00 2001 From: abhishek-kaushik22 Date: Wed, 4 Dec 2024 14:42:34 +0530 Subject: [PATCH 1/4] [X86][AVX512] Check input-types to COMX --- llvm/lib/Target/X86/X86ISelLowering.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 96b03feaa4580..c8d6bd7c62212 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -24228,8 +24228,13 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { if (Subtarget.hasAVX10_2()) { if (CC == ISD::SETOEQ || CC == ISD::SETUNE) { auto NewCC = (CC == ISD::SETOEQ) ? X86::COND_E : (X86::COND_NE); - return getSETCC(NewCC, DAG.getNode(X86ISD::UCOMX, dl, MVT::i32, Op0, Op1), - dl, DAG); + auto isValidType = [&](MVT Type) { + return Type == MVT::f16 || Type == MVT::f32 || Type == MVT::f64; + }; + if (isValidType(Op0.getSimpleValueType()) && + isValidType(Op1.getSimpleValueType())) + return getSETCC( + NewCC, DAG.getNode(X86ISD::UCOMX, dl, MVT::i32, Op0, Op1), dl, DAG); } } // Handle floating point. From 647ef4d3124bcec74114759ad8d58294f916aae3 Mon Sep 17 00:00:00 2001 From: abhishek-kaushik22 Date: Wed, 4 Dec 2024 15:11:22 +0530 Subject: [PATCH 2/4] Add regression test --- llvm/test/CodeGen/X86/avx10_2-cmp.ll | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/llvm/test/CodeGen/X86/avx10_2-cmp.ll b/llvm/test/CodeGen/X86/avx10_2-cmp.ll index de0bec7ea2695..140a20c17ea6d 100644 --- a/llvm/test/CodeGen/X86/avx10_2-cmp.ll +++ b/llvm/test/CodeGen/X86/avx10_2-cmp.ll @@ -235,3 +235,44 @@ define i1 @dune_mem(ptr %xp, ptr %yp) { %1 = fcmp une double %x, %y ret i1 %1 } + +define i32 @PR118606(x86_fp80 %val1) #0 { +; X64-LABEL: PR118606: +; X64: # %bb.0: # %entry +; X64-NEXT: fldt {{[0-9]+}}(%rsp) +; X64-NEXT: fldz +; X64-NEXT: fucomi %st(1), %st +; X64-NEXT: fstp %st(1) +; X64-NEXT: fld1 +; X64-NEXT: fcmovne %st(1), %st +; X64-NEXT: fcmovu %st(1), %st +; X64-NEXT: fucompi %st(1), %st +; X64-NEXT: fstp %st(0) +; X64-NEXT: xorl %eax, %eax +; X64-NEXT: retq +; +; X86-LABEL: PR118606: +; X86: # %bb.0: # %entry +; X86-NEXT: fldt {{[0-9]+}}(%esp) +; X86-NEXT: fldz +; X86-NEXT: fucomi %st(1), %st +; X86-NEXT: fstp %st(1) +; X86-NEXT: fld1 +; X86-NEXT: fcmovne %st(1), %st +; X86-NEXT: fcmovu %st(1), %st +; X86-NEXT: fucompi %st(1), %st +; X86-NEXT: fstp %st(0) +; X86-NEXT: xorl %eax, %eax +; X86-NEXT: retl +entry: + %cmp8 = fcmp oeq x86_fp80 %val1, 0xK00000000000000000000 + %0 = select i1 %cmp8, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK00000000000000000000 + %cmp64 = fcmp ogt x86_fp80 %0, 0xK00000000000000000000 + br i1 %cmp64, label %if.then66, label %if.end70 + +if.then66: ; preds = %entry + ret i32 0 + +if.end70: ; preds = %entry + ret i32 0 +} From 37696d18d0d12cbb8c97cccd1ee239d59ce632c7 Mon Sep 17 00:00:00 2001 From: abhishek-kaushik22 Date: Wed, 4 Dec 2024 16:28:54 +0530 Subject: [PATCH 3/4] Only check for type f80 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index c8d6bd7c62212..a6e21cd70c64c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -24228,11 +24228,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { if (Subtarget.hasAVX10_2()) { if (CC == ISD::SETOEQ || CC == ISD::SETUNE) { auto NewCC = (CC == ISD::SETOEQ) ? X86::COND_E : (X86::COND_NE); - auto isValidType = [&](MVT Type) { - return Type == MVT::f16 || Type == MVT::f32 || Type == MVT::f64; - }; - if (isValidType(Op0.getSimpleValueType()) && - isValidType(Op1.getSimpleValueType())) + if (Op0.getSimpleValueType() != MVT::f80) return getSETCC( NewCC, DAG.getNode(X86ISD::UCOMX, dl, MVT::i32, Op0, Op1), dl, DAG); } From 91258fe439c88070cf3c2812c9942192ed621cdd Mon Sep 17 00:00:00 2001 From: abhishek-kaushik22 Date: Thu, 5 Dec 2024 11:44:41 +0530 Subject: [PATCH 4/4] Add assertion --- llvm/lib/Target/X86/X86ISelLowering.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 624750d8e0eb2..f6c799bbd3a75 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -24228,6 +24228,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { if (Subtarget.hasAVX10_2()) { if (CC == ISD::SETOEQ || CC == ISD::SETUNE) { auto NewCC = (CC == ISD::SETOEQ) ? X86::COND_E : (X86::COND_NE); + assert(Op0.getSimpleValueType() != MVT::bf16 && "Unsupported Type"); if (Op0.getSimpleValueType() != MVT::f80) return getSETCC( NewCC, DAG.getNode(X86ISD::UCOMX, dl, MVT::i32, Op0, Op1), dl, DAG);