From 90b27e75897ee756e35dd23bd157a454cb42abdc Mon Sep 17 00:00:00 2001 From: abhishek-kaushik22 Date: Tue, 19 Nov 2024 13:58:41 +0530 Subject: [PATCH 1/6] [SDAG] [X86] Extend SplitVecOp_VSETCC for STRICT_FSETCCS --- .../SelectionDAG/LegalizeVectorTypes.cpp | 11 ++++--- .../X86/vec-strict-cmp-512-skx-fp64.ll | 31 +++++++++++++++++++ 2 files changed, 38 insertions(+), 4 deletions(-) create mode 100644 llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index eccda73548e87..3dda807ed6525 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -3235,6 +3235,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { case ISD::VP_SETCC: case ISD::STRICT_FSETCC: + case ISD::STRICT_FSETCCS: case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break; case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; @@ -4236,7 +4237,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) { } SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { - bool isStrict = N->getOpcode() == ISD::STRICT_FSETCC; + bool isStrict = N->getOpcode() == ISD::STRICT_FSETCC || + N->getOpcode() == ISD::STRICT_FSETCCS; assert(N->getValueType(0).isVector() && N->getOperand(isStrict ? 1 : 0).getValueType().isVector() && "Operand types must be vectors"); @@ -4255,11 +4257,12 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { if (N->getOpcode() == ISD::SETCC) { LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); - } else if (N->getOpcode() == ISD::STRICT_FSETCC) { - LoRes = DAG.getNode(ISD::STRICT_FSETCC, DL, + } else if (N->getOpcode() == ISD::STRICT_FSETCC || + N->getOpcode() == ISD::STRICT_FSETCCS) { + LoRes = DAG.getNode(N->getOpcode(), DL, DAG.getVTList(PartResVT, N->getValueType(1)), N->getOperand(0), Lo0, Lo1, N->getOperand(3)); - HiRes = DAG.getNode(ISD::STRICT_FSETCC, DL, + HiRes = DAG.getNode(N->getOpcode(), DL, DAG.getVTList(PartResVT, N->getValueType(1)), N->getOperand(0), Hi0, Hi1, N->getOperand(3)); SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, diff --git a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll new file mode 100644 index 0000000000000..181d0cd0ef1d7 --- /dev/null +++ b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mtriple=x86_64 -mcpu=skx | FileCheck %s --check-prefixes=SKX + +define <16 x i32> @test_v16f64_ogt(<16 x i32> %a, <16 x i32> %b, <16 x double> %f1, <16 x double> %f2) #0 { +; SKX-LABEL: test_v16f64_ogt +; SKX: # %bb.0: +; SKX-NEXT: pushq %rbp +; SKX-NEXT: movq %rsp, %rbp +; SKX-NEXT: andq $-32, %rsp +; SKX-NEXT: subq $32, %rsp +; SKX-NEXT: vcmpgtpd 80(%rbp), %ymm6, %k0 +; SKX-NEXT: vcmpgtpd 112(%rbp), %ymm7, %k1 +; SKX-NEXT: kshiftlb $4, %k1, %k1 +; SKX-NEXT: korb %k1, %k0, %k1 +; SKX-NEXT: vcmpgtpd 16(%rbp), %ymm4, %k0 +; SKX-NEXT: vcmpgtpd 48(%rbp), %ymm5, %k2 +; SKX-NEXT: kshiftlb $4, %k2, %k2 +; SKX-NEXT: korb %k2, %k0, %k2 +; SKX-NEXT: vpblendmd %ymm0, %ymm2, %ymm0 {%k2} +; SKX-NEXT: vpblendmd %ymm1, %ymm3, %ymm1 {%k1} +; SKX-NEXT: movq %rbp, %rsp +; SKX-NEXT: popq %rbp +; SKX-NEXT: retq + %cond = tail call <16 x i1> @llvm.experimental.constrained.fcmps.v16f64( + <16 x double> %f1, <16 x double> %f2, metadata !"ogt", metadata !"fpexcept.maytrap") + %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b + ret <16 x i32> %res +} + +declare <16 x i1> @llvm.experimental.constrained.fcmps.v16f64(<16 x double>, <16 x double>, metadata, metadata) + +attributes #0 = { nounwind strictfp "min-legal-vector-width"="0" } \ No newline at end of file From 401449798893724789acb4077c38834b8d3422a2 Mon Sep 17 00:00:00 2001 From: abhishek-kaushik22 Date: Tue, 19 Nov 2024 14:00:31 +0530 Subject: [PATCH 2/6] Update vec-strict-cmp-512-skx-fp64.ll --- llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll index 181d0cd0ef1d7..c3d4052c553f5 100644 --- a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll +++ b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll @@ -28,4 +28,4 @@ define <16 x i32> @test_v16f64_ogt(<16 x i32> %a, <16 x i32> %b, <16 x double> % declare <16 x i1> @llvm.experimental.constrained.fcmps.v16f64(<16 x double>, <16 x double>, metadata, metadata) -attributes #0 = { nounwind strictfp "min-legal-vector-width"="0" } \ No newline at end of file +attributes #0 = { nounwind strictfp "min-legal-vector-width"="0" } From 79d4592e02738b614b1a72254ee7ce31be80ec4e Mon Sep 17 00:00:00 2001 From: abhishek-kaushik22 Date: Tue, 19 Nov 2024 15:48:36 +0530 Subject: [PATCH 3/6] Use a variable for N->getOpcode() calls --- .../SelectionDAG/LegalizeVectorTypes.cpp | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 3dda807ed6525..8ac0835d719e1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -4237,8 +4237,9 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) { } SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { - bool isStrict = N->getOpcode() == ISD::STRICT_FSETCC || - N->getOpcode() == ISD::STRICT_FSETCCS; + auto Opc = N->getOpcode(); + bool isStrict = Opc == ISD::STRICT_FSETCC || + Opc == ISD::STRICT_FSETCCS; assert(N->getValueType(0).isVector() && N->getOperand(isStrict ? 1 : 0).getValueType().isVector() && "Operand types must be vectors"); @@ -4254,22 +4255,22 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { EVT PartResVT = EVT::getVectorVT(Context, MVT::i1, PartEltCnt); EVT WideResVT = EVT::getVectorVT(Context, MVT::i1, PartEltCnt*2); - if (N->getOpcode() == ISD::SETCC) { + if (Opc == ISD::SETCC) { LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); - } else if (N->getOpcode() == ISD::STRICT_FSETCC || - N->getOpcode() == ISD::STRICT_FSETCCS) { - LoRes = DAG.getNode(N->getOpcode(), DL, + } else if (Opc == ISD::STRICT_FSETCC || + Opc == ISD::STRICT_FSETCCS) { + LoRes = DAG.getNode(Opc, DL, DAG.getVTList(PartResVT, N->getValueType(1)), N->getOperand(0), Lo0, Lo1, N->getOperand(3)); - HiRes = DAG.getNode(N->getOpcode(), DL, + HiRes = DAG.getNode(Opc, DL, DAG.getVTList(PartResVT, N->getValueType(1)), N->getOperand(0), Hi0, Hi1, N->getOperand(3)); SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, LoRes.getValue(1), HiRes.getValue(1)); ReplaceValueWith(SDValue(N, 1), NewChain); } else { - assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode"); + assert(Opc == ISD::VP_SETCC && "Expected VP_SETCC opcode"); SDValue MaskLo, MaskHi, EVLLo, EVLHi; std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(3)); std::tie(EVLLo, EVLHi) = From 6aa250588b370c49081ad0dc3c2f983e3a9c91a0 Mon Sep 17 00:00:00 2001 From: abhishek-kaushik22 Date: Tue, 19 Nov 2024 15:54:30 +0530 Subject: [PATCH 4/6] Update LegalizeVectorTypes.cpp --- .../lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 8ac0835d719e1..d891e818ca56d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -4238,8 +4238,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) { SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { auto Opc = N->getOpcode(); - bool isStrict = Opc == ISD::STRICT_FSETCC || - Opc == ISD::STRICT_FSETCCS; + bool isStrict = Opc == ISD::STRICT_FSETCC || Opc == ISD::STRICT_FSETCCS; assert(N->getValueType(0).isVector() && N->getOperand(isStrict ? 1 : 0).getValueType().isVector() && "Operand types must be vectors"); @@ -4258,13 +4257,10 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { if (Opc == ISD::SETCC) { LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); - } else if (Opc == ISD::STRICT_FSETCC || - Opc == ISD::STRICT_FSETCCS) { - LoRes = DAG.getNode(Opc, DL, - DAG.getVTList(PartResVT, N->getValueType(1)), + } else if (Opc == ISD::STRICT_FSETCC || Opc == ISD::STRICT_FSETCCS) { + LoRes = DAG.getNode(Opc, DL, DAG.getVTList(PartResVT, N->getValueType(1)), N->getOperand(0), Lo0, Lo1, N->getOperand(3)); - HiRes = DAG.getNode(Opc, DL, - DAG.getVTList(PartResVT, N->getValueType(1)), + HiRes = DAG.getNode(Opc, DL, DAG.getVTList(PartResVT, N->getValueType(1)), N->getOperand(0), Hi0, Hi1, N->getOperand(3)); SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, LoRes.getValue(1), HiRes.getValue(1)); From 6f69ac5167c1515e78278317b27e39ffe39506e0 Mon Sep 17 00:00:00 2001 From: abhishek-kaushik22 Date: Tue, 19 Nov 2024 16:09:24 +0530 Subject: [PATCH 5/6] Update LegalizeVectorTypes.cpp --- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index d891e818ca56d..3d24b039aeafc 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -4257,7 +4257,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { if (Opc == ISD::SETCC) { LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); - } else if (Opc == ISD::STRICT_FSETCC || Opc == ISD::STRICT_FSETCCS) { + } else if (isStrict) { LoRes = DAG.getNode(Opc, DL, DAG.getVTList(PartResVT, N->getValueType(1)), N->getOperand(0), Lo0, Lo1, N->getOperand(3)); HiRes = DAG.getNode(Opc, DL, DAG.getVTList(PartResVT, N->getValueType(1)), From be062db6513df450229b105039c7ce05fb96d523 Mon Sep 17 00:00:00 2001 From: abhishek-kaushik22 Date: Thu, 21 Nov 2024 11:31:38 +0530 Subject: [PATCH 6/6] Add test to existing file, replace auto with unsigned --- .../SelectionDAG/LegalizeVectorTypes.cpp | 2 +- .../X86/vec-strict-cmp-512-skx-fp64.ll | 31 ------------------- .../CodeGen/X86/vec-strict-cmp-512-skx.ll | 27 ++++++++++++++++ 3 files changed, 28 insertions(+), 32 deletions(-) delete mode 100644 llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 3d24b039aeafc..465128099f444 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -4237,7 +4237,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) { } SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { - auto Opc = N->getOpcode(); + unsigned Opc = N->getOpcode(); bool isStrict = Opc == ISD::STRICT_FSETCC || Opc == ISD::STRICT_FSETCCS; assert(N->getValueType(0).isVector() && N->getOperand(isStrict ? 1 : 0).getValueType().isVector() && diff --git a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll deleted file mode 100644 index c3d4052c553f5..0000000000000 --- a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64 -mcpu=skx | FileCheck %s --check-prefixes=SKX - -define <16 x i32> @test_v16f64_ogt(<16 x i32> %a, <16 x i32> %b, <16 x double> %f1, <16 x double> %f2) #0 { -; SKX-LABEL: test_v16f64_ogt -; SKX: # %bb.0: -; SKX-NEXT: pushq %rbp -; SKX-NEXT: movq %rsp, %rbp -; SKX-NEXT: andq $-32, %rsp -; SKX-NEXT: subq $32, %rsp -; SKX-NEXT: vcmpgtpd 80(%rbp), %ymm6, %k0 -; SKX-NEXT: vcmpgtpd 112(%rbp), %ymm7, %k1 -; SKX-NEXT: kshiftlb $4, %k1, %k1 -; SKX-NEXT: korb %k1, %k0, %k1 -; SKX-NEXT: vcmpgtpd 16(%rbp), %ymm4, %k0 -; SKX-NEXT: vcmpgtpd 48(%rbp), %ymm5, %k2 -; SKX-NEXT: kshiftlb $4, %k2, %k2 -; SKX-NEXT: korb %k2, %k0, %k2 -; SKX-NEXT: vpblendmd %ymm0, %ymm2, %ymm0 {%k2} -; SKX-NEXT: vpblendmd %ymm1, %ymm3, %ymm1 {%k1} -; SKX-NEXT: movq %rbp, %rsp -; SKX-NEXT: popq %rbp -; SKX-NEXT: retq - %cond = tail call <16 x i1> @llvm.experimental.constrained.fcmps.v16f64( - <16 x double> %f1, <16 x double> %f2, metadata !"ogt", metadata !"fpexcept.maytrap") - %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b - ret <16 x i32> %res -} - -declare <16 x i1> @llvm.experimental.constrained.fcmps.v16f64(<16 x double>, <16 x double>, metadata, metadata) - -attributes #0 = { nounwind strictfp "min-legal-vector-width"="0" } diff --git a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll index 3028b74967378..0ec33ad800912 100644 --- a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll +++ b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll @@ -34,7 +34,34 @@ define <8 x i32> @test_v8f64_oeq_q(<8 x i32> %a, <8 x i32> %b, <8 x double> %f1, ret <8 x i32> %res } +define <16 x i32> @test_v16f64_ogt(<16 x i32> %a, <16 x i32> %b, <16 x double> %f1, <16 x double> %f2) #0 { +; SKX-LABEL: test_v16f64_ogt +; SKX: # %bb.0: +; SKX-NEXT: pushq %rbp +; SKX-NEXT: movq %rsp, %rbp +; SKX-NEXT: andq $-32, %rsp +; SKX-NEXT: subq $32, %rsp +; SKX-NEXT: vcmpgtpd 80(%rbp), %ymm6, %k0 +; SKX-NEXT: vcmpgtpd 112(%rbp), %ymm7, %k1 +; SKX-NEXT: kshiftlb $4, %k1, %k1 +; SKX-NEXT: korb %k1, %k0, %k1 +; SKX-NEXT: vcmpgtpd 16(%rbp), %ymm4, %k0 +; SKX-NEXT: vcmpgtpd 48(%rbp), %ymm5, %k2 +; SKX-NEXT: kshiftlb $4, %k2, %k2 +; SKX-NEXT: korb %k2, %k0, %k2 +; SKX-NEXT: vpblendmd %ymm0, %ymm2, %ymm0 {%k2} +; SKX-NEXT: vpblendmd %ymm1, %ymm3, %ymm1 {%k1} +; SKX-NEXT: movq %rbp, %rsp +; SKX-NEXT: popq %rbp +; SKX-NEXT: retq + %cond = tail call <16 x i1> @llvm.experimental.constrained.fcmps.v16f64( + <16 x double> %f1, <16 x double> %f2, metadata !"ogt", metadata !"fpexcept.maytrap") + %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b + ret <16 x i32> %res +} + declare <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float>, <16 x float>, metadata, metadata) declare <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double>, <8 x double>, metadata, metadata) +declare <16 x i1> @llvm.experimental.constrained.fcmps.v16f64(<16 x double>, <16 x double>, metadata, metadata) attributes #0 = { nounwind strictfp "min-legal-vector-width"="0" }