From ca4b5d06e1bb2be3c92341ebcbb9b4e3208b646d Mon Sep 17 00:00:00 2001 From: Marian Lukac Date: Wed, 23 Oct 2024 14:54:22 +0000 Subject: [PATCH 1/4] [AArch64] Update feature dep. for Armv9.6 extensions --- llvm/lib/Target/AArch64/AArch64Features.td | 13 +++--- .../TargetParser/TargetParserTest.cpp | 42 +++++++++++++++++-- 2 files changed, 46 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 476d5a4e093ef..afa96821984b3 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -526,23 +526,23 @@ def FeatureCMPBR : ExtensionWithMArch<"cmpbr", "CMPBR", "FEAT_CMPBR", "Enable Armv9.6-A base compare and branch instructions">; def FeatureF8F32MM: ExtensionWithMArch<"f8f32mm", "F8F32MM", "FEAT_F8F32MM", - "Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication">; + "Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication", [FeatureNEON, FeatureFP8]>; def FeatureF8F16MM: ExtensionWithMArch<"f8f16mm", "F8F16MM", "FEAT_F8F16MM", - "Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication">; + "Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication", [FeatureNEON, FeatureFP8]>; def FeatureFPRCVT: ExtensionWithMArch<"fprcvt", "FPRCVT", "FEAT_FPRCVT", "Enable Armv9.6-A base convert instructions for SIMD&FP scalar register operands of" - " different input and output sizes">; + " different input and output sizes", [FeatureFPARMv8]>; def FeatureLSFE : ExtensionWithMArch<"lsfe", "LSFE", "FEAT_LSFE", - "Enable Armv9.6-A base Atomic floating-point in-memory instructions">; + "Enable Armv9.6-A base Atomic floating-point in-memory instructions", [FeatureFPARMv8]>; def FeatureSME2p2: ExtensionWithMArch<"sme2p2", "SME2p2", "FEAT_SME2p2", "Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions", [FeatureSME2p1]>; def FeatureSSVE_AES : ExtensionWithMArch<"ssve-aes", "SSVE_AES", "FEAT_SSVE_AES", - "Enable Armv9.6-A SVE2 AES support in streaming SVE mode">; + "Enable Armv9.6-A SVE2 AES support in streaming SVE mode", [FeatureSME2, FeatureSVE2AES]>; def FeatureSVE2p2 : ExtensionWithMArch<"sve2p2", "SVE2p2", "FEAT_SVE2p2", "Enable Armv9.6-A Scalable Vector Extension 2.2 instructions", [FeatureSVE2p1]>; @@ -554,7 +554,8 @@ def FeatureSVEBFSCALE: ExtensionWithMArch<"sve-bfscale", "SVE_BFSCALE", "FEAT_SV "Enable Armv9.6-A SVE BFloat16 scaling instructions">; def FeatureSVE_F16F32MM: ExtensionWithMArch<"sve-f16f32mm", "SVE_F16F32MM", "FEAT_SVE_F16F32MM", - "Enable Armv9.6-A FP16 to FP32 Matrix Multiply instructions">; + "Enable Armv9.6-A FP16 to FP32 Matrix Multiply instructions", [FeatureSVE]>; + def FeatureLSUI: ExtensionWithMArch<"lsui", "LSUI", "FEAT_LSUI", "Enable Armv9.6-A unprivileged load/store instructions">; diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 572006166d0d8..07e3742a7e9f9 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1782,7 +1782,15 @@ AArch64ExtensionDependenciesBaseArchTestParams {AArch64::ARMV8A, {"nofp", "jscvt"}, {"fp-armv8", "jsconv"}, {}}, {AArch64::ARMV8A, {"jscvt", "nofp"}, {}, {"fp-armv8", "jsconv"}}, - // simd -> {aes, sha2, sha3, sm4} + // fp -> lsfe + {AArch64::ARMV9_6A, {"nofp", "lsfe"}, {"fp-armv8", "lsfe"}, {}}, + {AArch64::ARMV9_6A, {"lsfe", "nofp"}, {}, {"fp-armv8", "lsfe"}}, + + // fp -> fprcvt + {AArch64::ARMV9_6A, {"nofp", "fprcvt"}, {"fp-armv8", "fprcvt"}, {}}, + {AArch64::ARMV9_6A, {"fprcvt", "nofp"}, {}, {"fp-armv8", "fprcvt"}}, + + // simd -> {aes, sha2, sha3, sm4, f8f16mm, f8f32mm} {AArch64::ARMV8A, {"nosimd", "aes"}, {"neon", "aes"}, {}}, {AArch64::ARMV8A, {"aes", "nosimd"}, {}, {"neon", "aes"}}, {AArch64::ARMV8A, {"nosimd", "sha2"}, {"neon", "sha2"}, {}}, @@ -1791,6 +1799,10 @@ AArch64ExtensionDependenciesBaseArchTestParams {AArch64::ARMV8A, {"sha3", "nosimd"}, {}, {"neon", "sha3"}}, {AArch64::ARMV8A, {"nosimd", "sm4"}, {"neon", "sm4"}, {}}, {AArch64::ARMV8A, {"sm4", "nosimd"}, {}, {"neon", "sm4"}}, + {AArch64::ARMV9_6A, {"nosimd", "f8f16mm"}, {"neon", "f8f16mm"}, {}}, + {AArch64::ARMV9_6A, {"f8f16mm", "nosimd"}, {}, {"neon", "f8f16mm"}}, + {AArch64::ARMV9_6A, {"nosimd", "f8f32mm"}, {"neon", "f8f32mm"}, {}}, + {AArch64::ARMV9_6A, {"f8f32mm", "nosimd"}, {}, {"neon", "f8f32mm"}}, // simd -> {rdm, dotprod, fcma} {AArch64::ARMV8A, {"nosimd", "rdm"}, {"neon", "rdm"}, {}}, @@ -1810,13 +1822,21 @@ AArch64ExtensionDependenciesBaseArchTestParams {AArch64::ARMV8A, {"nobf16", "sme"}, {"bf16", "sme"}, {}}, {AArch64::ARMV8A, {"sme", "nobf16"}, {}, {"bf16", "sme"}}, - // sve -> {sve2, f32mm, f64mm} + // sve -> {sve2, f32mm, f64mm, sve-f16f32mm} {AArch64::ARMV8A, {"nosve", "sve2"}, {"sve", "sve2"}, {}}, {AArch64::ARMV8A, {"sve2", "nosve"}, {}, {"sve", "sve2"}}, {AArch64::ARMV8A, {"nosve", "f32mm"}, {"sve", "f32mm"}, {}}, {AArch64::ARMV8A, {"f32mm", "nosve"}, {}, {"sve", "f32mm"}}, {AArch64::ARMV8A, {"nosve", "f64mm"}, {"sve", "f64mm"}, {}}, {AArch64::ARMV8A, {"f64mm", "nosve"}, {}, {"sve", "f64mm"}}, + {AArch64::ARMV9_6A, + {"nosve", "sve-f16f32mm"}, + {"sve", "sve-f16f32mm"}, + {}}, + {AArch64::ARMV9_6A, + {"sve-f16f32mm", "nosve"}, + {}, + {"sve", "sve-f16f32mm"}}, // sve2 -> {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4} {AArch64::ARMV8A, {"nosve2", "sve2p1"}, {"sve2", "sve2p1"}, {}}, @@ -1861,7 +1881,7 @@ AArch64ExtensionDependenciesBaseArchTestParams {AArch64::ARMV8A, {"sme-fa64", "nosme"}, {}, {"sme", "sme-fa64"}}, // sme2 -> {sme2p1, ssve-fp8fma, ssve-fp8dot2, ssve-fp8dot4, sme-f8f16, - // sme-f8f32, sme-b16b16} + // sme-f8f32, sme-b16b16i, ssve-aes} {AArch64::ARMV8A, {"nosme2", "sme2p1"}, {"sme2", "sme2p1"}, {}}, {AArch64::ARMV8A, {"sme2p1", "nosme2"}, {}, {"sme2", "sme2p1"}}, {AArch64::ARMV8A, @@ -1894,6 +1914,8 @@ AArch64ExtensionDependenciesBaseArchTestParams {AArch64::ARMV8A, {"sme-f8f32", "nosme2"}, {}, {"sme2", "sme-f8f32"}}, {AArch64::ARMV8A, {"nosme2", "sme-b16b16"}, {"sme2", "sme-b16b16"}, {}}, {AArch64::ARMV8A, {"sme-b16b16", "nosme2"}, {}, {"sme2", "sme-b16b16"}}, + {AArch64::ARMV9_6A, {"nosme2", "ssve-aes"}, {"sme2", "ssve-aes"}, {}}, + {AArch64::ARMV9_6A, {"ssve-aes", "nosme2"}, {}, {"ssve-aes", "sme2"}}, // sme2p1 -> {sme2p2} {AArch64::ARMV9_6A, {"nosme2p1", "sme2p2"}, {"sme2p2", "sme2p1"}, {}}, @@ -1904,6 +1926,10 @@ AArch64ExtensionDependenciesBaseArchTestParams {AArch64::ARMV8A, {"sme-f8f16", "nofp8"}, {}, {"fp8", "sme-f8f16"}}, {AArch64::ARMV8A, {"nofp8", "sme-f8f32"}, {"fp8", "sme-f8f32"}, {}}, {AArch64::ARMV8A, {"sme-f8f32", "nofp8"}, {}, {"fp8", "sme-f8f32"}}, + {AArch64::ARMV9_6A, {"nofp8", "f8f16mm"}, {"fp8", "f8f16mm"}, {}}, + {AArch64::ARMV9_6A, {"f8f16mm", "nofp8"}, {}, {"fp8", "f8f16mm"}}, + {AArch64::ARMV9_6A, {"nofp8", "f8f32mm"}, {"fp8", "f8f32mm"}, {}}, + {AArch64::ARMV9_6A, {"f8f32mm", "nofp8"}, {}, {"fp8", "f8f32mm"}}, // lse -> lse128 {AArch64::ARMV8A, {"nolse", "lse128"}, {"lse", "lse128"}, {}}, @@ -1926,6 +1952,16 @@ AArch64ExtensionDependenciesBaseArchTestParams // rcpc -> rcpc3 {AArch64::ARMV8A, {"norcpc", "rcpc3"}, {"rcpc", "rcpc3"}, {}}, {AArch64::ARMV8A, {"rcpc3", "norcpc"}, {}, {"rcpc", "rcpc3"}}, + + // sve-aes -> ssve-aes + {AArch64::ARMV9_6A, + {"nosve2-aes", "ssve-aes"}, + {"sve2-aes", "ssve-aes"}, + {}}, + {AArch64::ARMV9_6A, + {"ssve-aes", "nosve2-aes"}, + {}, + {"ssve-aes", "sve2-aes"}}, }; INSTANTIATE_TEST_SUITE_P( From 1f2953e47b451238d7cc9d1e801c5ea1b9cbd536 Mon Sep 17 00:00:00 2001 From: Lukacma Date: Thu, 24 Oct 2024 10:22:35 +0100 Subject: [PATCH 2/4] Update llvm/unittests/TargetParser/TargetParserTest.cpp Co-authored-by: Jonathan Thackray --- llvm/unittests/TargetParser/TargetParserTest.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 07e3742a7e9f9..f3f2a029d09fd 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1881,7 +1881,7 @@ AArch64ExtensionDependenciesBaseArchTestParams {AArch64::ARMV8A, {"sme-fa64", "nosme"}, {}, {"sme", "sme-fa64"}}, // sme2 -> {sme2p1, ssve-fp8fma, ssve-fp8dot2, ssve-fp8dot4, sme-f8f16, - // sme-f8f32, sme-b16b16i, ssve-aes} + // sme-f8f32, sme-b16b16, ssve-aes} {AArch64::ARMV8A, {"nosme2", "sme2p1"}, {"sme2", "sme2p1"}, {}}, {AArch64::ARMV8A, {"sme2p1", "nosme2"}, {}, {"sme2", "sme2p1"}}, {AArch64::ARMV8A, From f90fd226fa69dee7167d97396e5a57f22b3634a9 Mon Sep 17 00:00:00 2001 From: Lukacma Date: Thu, 24 Oct 2024 10:22:43 +0100 Subject: [PATCH 3/4] Update llvm/unittests/TargetParser/TargetParserTest.cpp Co-authored-by: SpencerAbson --- llvm/unittests/TargetParser/TargetParserTest.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index f3f2a029d09fd..d277fcb8b5bef 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1953,7 +1953,7 @@ AArch64ExtensionDependenciesBaseArchTestParams {AArch64::ARMV8A, {"norcpc", "rcpc3"}, {"rcpc", "rcpc3"}, {}}, {AArch64::ARMV8A, {"rcpc3", "norcpc"}, {}, {"rcpc", "rcpc3"}}, - // sve-aes -> ssve-aes + // sve2-aes -> ssve-aes {AArch64::ARMV9_6A, {"nosve2-aes", "ssve-aes"}, {"sve2-aes", "ssve-aes"}, From 158a14ac6794f40a6f4852622fa4f192e18c6b3d Mon Sep 17 00:00:00 2001 From: Marian Lukac Date: Thu, 24 Oct 2024 09:24:46 +0000 Subject: [PATCH 4/4] update comment --- llvm/unittests/TargetParser/TargetParserTest.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index d277fcb8b5bef..51ea9cb6d6443 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1921,7 +1921,7 @@ AArch64ExtensionDependenciesBaseArchTestParams {AArch64::ARMV9_6A, {"nosme2p1", "sme2p2"}, {"sme2p2", "sme2p1"}, {}}, {AArch64::ARMV9_6A, {"sme2p2", "nosme2p1"}, {}, {"sme2p1", "sme2p2"}}, - // fp8 -> {sme-f8f16, sme-f8f32} + // fp8 -> {sme-f8f16, sme-f8f32, f8f16mm, f8f32mm} {AArch64::ARMV8A, {"nofp8", "sme-f8f16"}, {"fp8", "sme-f8f16"}, {}}, {AArch64::ARMV8A, {"sme-f8f16", "nofp8"}, {}, {"fp8", "sme-f8f16"}}, {AArch64::ARMV8A, {"nofp8", "sme-f8f32"}, {"fp8", "sme-f8f32"}, {}},