diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 07b59b241d9f9..408adcd330b84 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -159,6 +159,12 @@ class TargetInstrInfo : public MCInstrInfo {
     return true;
   }
 
+  /// For a "cheap" instruction which doesn't enable additional sinking,
+  /// should MachineSink break a critical edge to sink it anyways?
+  virtual bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const {
+    return false;
+  }
+
 protected:
   /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
   /// set, this hook lets the target specify whether the instruction is actually
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 0def107f6306d..7d0bedab7cdab 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -958,7 +958,9 @@ bool MachineSinking::isWorthBreakingCriticalEdge(
     }
   }
 
-  return false;
+  // Let the target decide if it's worth breaking this
+  // critical edge for a "cheap" instruction.
+  return TII->shouldBreakCriticalEdgeToSink(MI);
 }
 
 bool MachineSinking::isLegalToBreakCriticalEdge(MachineInstr &MI,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index c3aa367486627..005cba5d35610 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -78,6 +78,11 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
 
+  bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override {
+    return MI.getOpcode() == RISCV::ADDI && MI.getOperand(1).isReg() &&
+           MI.getOperand(1).getReg() == RISCV::X0;
+  }
+
   void copyPhysRegVector(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
                          MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
index a4f92640697bc..7133d5c100e75 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
@@ -43,23 +43,21 @@ define i32 @fcvt_wu_d(double %a) nounwind {
 define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind {
 ; RV32IFD-LABEL: fcvt_wu_d_multiple_use:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.wu.d a1, fa0, rtz
-; RV32IFD-NEXT:    li a0, 1
-; RV32IFD-NEXT:    beqz a1, .LBB4_2
+; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; RV32IFD-NEXT:    bnez a0, .LBB4_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    mv a0, a1
+; RV32IFD-NEXT:    li a0, 1
 ; RV32IFD-NEXT:  .LBB4_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_wu_d_multiple_use:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.wu.d a1, fa0, rtz
-; RV64IFD-NEXT:    slli a0, a1, 32
-; RV64IFD-NEXT:    srli a2, a0, 32
-; RV64IFD-NEXT:    li a0, 1
-; RV64IFD-NEXT:    beqz a2, .LBB4_2
+; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; RV64IFD-NEXT:    slli a1, a0, 32
+; RV64IFD-NEXT:    srli a1, a1, 32
+; RV64IFD-NEXT:    bnez a1, .LBB4_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    mv a0, a1
+; RV64IFD-NEXT:    li a0, 1
 ; RV64IFD-NEXT:  .LBB4_2:
 ; RV64IFD-NEXT:    ret
   %a = fptoui double %x to i32
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
index 7e96d529af36f..e6df28f5f28d1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
@@ -27,23 +27,21 @@ define i32 @fcvt_wu_s(float %a) nounwind {
 define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind {
 ; RV32IF-LABEL: fcvt_wu_s_multiple_use:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV32IF-NEXT:    li a0, 1
-; RV32IF-NEXT:    beqz a1, .LBB2_2
+; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; RV32IF-NEXT:    bnez a0, .LBB2_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    mv a0, a1
+; RV32IF-NEXT:    li a0, 1
 ; RV32IF-NEXT:  .LBB2_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_wu_s_multiple_use:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV64IF-NEXT:    slli a0, a1, 32
-; RV64IF-NEXT:    srli a2, a0, 32
-; RV64IF-NEXT:    li a0, 1
-; RV64IF-NEXT:    beqz a2, .LBB2_2
+; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; RV64IF-NEXT:    slli a1, a0, 32
+; RV64IF-NEXT:    srli a1, a1, 32
+; RV64IF-NEXT:    bnez a1, .LBB2_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    mv a0, a1
+; RV64IF-NEXT:    li a0, 1
 ; RV64IF-NEXT:  .LBB2_2:
 ; RV64IF-NEXT:    ret
   %a = fptoui float %x to i32
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
index 94c03c400ffa3..16c588fa2f2ce 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
@@ -196,11 +196,9 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
 define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: findLastSet_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -32
-; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    li s0, -1
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a1, a0, 32
 ; RV64I-NEXT:    srliw a2, a0, 1
 ; RV64I-NEXT:    lui a3, 349525
@@ -227,36 +225,37 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
 ; RV64I-NEXT:    srli a2, a0, 4
 ; RV64I-NEXT:    add a0, a2, a0
 ; RV64I-NEXT:    lui a2, 4112
-; RV64I-NEXT:    srli s1, a1, 32
+; RV64I-NEXT:    srli s0, a1, 32
 ; RV64I-NEXT:    addiw a1, a3, -241
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    addiw a1, a2, 257
 ; RV64I-NEXT:    call __muldi3
-; RV64I-NEXT:    beqz s1, .LBB3_2
+; RV64I-NEXT:    beqz s0, .LBB3_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    srliw a0, a0, 24
 ; RV64I-NEXT:    li a1, 32
 ; RV64I-NEXT:    subw a1, a1, a0
-; RV64I-NEXT:    xori s0, a1, 31
+; RV64I-NEXT:    xori a0, a1, 31
+; RV64I-NEXT:    j .LBB3_3
 ; RV64I-NEXT:  .LBB3_2:
-; RV64I-NEXT:    mv a0, s0
-; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 32
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:  .LBB3_3:
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: findLastSet_i32:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    slli a1, a0, 32
-; RV64ZBB-NEXT:    srli a2, a1, 32
-; RV64ZBB-NEXT:    li a1, -1
-; RV64ZBB-NEXT:    beqz a2, .LBB3_2
+; RV64ZBB-NEXT:    srli a1, a1, 32
+; RV64ZBB-NEXT:    beqz a1, .LBB3_2
 ; RV64ZBB-NEXT:  # %bb.1:
 ; RV64ZBB-NEXT:    clzw a0, a0
-; RV64ZBB-NEXT:    xori a1, a0, 31
+; RV64ZBB-NEXT:    xori a0, a0, 31
+; RV64ZBB-NEXT:    ret
 ; RV64ZBB-NEXT:  .LBB3_2:
-; RV64ZBB-NEXT:    mv a0, a1
+; RV64ZBB-NEXT:    li a0, -1
 ; RV64ZBB-NEXT:    ret
   %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true)
   %2 = xor i32 31, %1
@@ -493,14 +492,12 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
 define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: findFirstSet_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -32
-; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    li s0, -1
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    addi a1, s1, -1
+; RV64I-NEXT:    addi a1, s0, -1
 ; RV64I-NEXT:    lui a2, 349525
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    addiw a1, a2, 1365
@@ -521,29 +518,30 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    addiw a1, a1, 257
 ; RV64I-NEXT:    call __muldi3
-; RV64I-NEXT:    slli s1, s1, 32
-; RV64I-NEXT:    srli s1, s1, 32
-; RV64I-NEXT:    beqz s1, .LBB8_2
+; RV64I-NEXT:    slli s0, s0, 32
+; RV64I-NEXT:    srli s0, s0, 32
+; RV64I-NEXT:    beqz s0, .LBB8_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    srliw s0, a0, 24
+; RV64I-NEXT:    srliw a0, a0, 24
+; RV64I-NEXT:    j .LBB8_3
 ; RV64I-NEXT:  .LBB8_2:
-; RV64I-NEXT:    mv a0, s0
-; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 32
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:  .LBB8_3:
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: findFirstSet_i32:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    slli a1, a0, 32
-; RV64ZBB-NEXT:    srli a2, a1, 32
-; RV64ZBB-NEXT:    li a1, -1
-; RV64ZBB-NEXT:    beqz a2, .LBB8_2
+; RV64ZBB-NEXT:    srli a1, a1, 32
+; RV64ZBB-NEXT:    beqz a1, .LBB8_2
 ; RV64ZBB-NEXT:  # %bb.1:
-; RV64ZBB-NEXT:    ctzw a1, a0
+; RV64ZBB-NEXT:    ctzw a0, a0
+; RV64ZBB-NEXT:    ret
 ; RV64ZBB-NEXT:  .LBB8_2:
-; RV64ZBB-NEXT:    mv a0, a1
+; RV64ZBB-NEXT:    li a0, -1
 ; RV64ZBB-NEXT:    ret
   %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
   %2 = icmp eq i32 %a, 0
diff --git a/llvm/test/CodeGen/RISCV/aext-to-sext.ll b/llvm/test/CodeGen/RISCV/aext-to-sext.ll
index 888ea666d7131..f3f71a923bdc2 100644
--- a/llvm/test/CodeGen/RISCV/aext-to-sext.ll
+++ b/llvm/test/CodeGen/RISCV/aext-to-sext.ll
@@ -78,12 +78,14 @@ bar:
 define i64 @sext_phi_constants(i32 signext %c) {
 ; RV64I-LABEL: sext_phi_constants:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    bnez a0, .LBB2_2
-; RV64I-NEXT:  # %bb.1: # %iffalse
-; RV64I-NEXT:    li a1, -2
-; RV64I-NEXT:  .LBB2_2: # %merge
-; RV64I-NEXT:    slli a0, a1, 32
+; RV64I-NEXT:    beqz a0, .LBB2_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:    j .LBB2_3
+; RV64I-NEXT:  .LBB2_2: # %iffalse
+; RV64I-NEXT:    li a0, -2
+; RV64I-NEXT:  .LBB2_3: # %merge
+; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
   %a = icmp ne i32 %c, 0
diff --git a/llvm/test/CodeGen/RISCV/compress-opt-select.ll b/llvm/test/CodeGen/RISCV/compress-opt-select.ll
index 2667fde89e935..f9333a45016a0 100644
--- a/llvm/test/CodeGen/RISCV/compress-opt-select.ll
+++ b/llvm/test/CodeGen/RISCV/compress-opt-select.ll
@@ -10,24 +10,24 @@
 define i32 @ne_small_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_small_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    c.li a2, 20
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    bne a1, a2, .LBB0_2
+; RV32IFDC-NEXT:    c.li a1, 20
+; RV32IFDC-NEXT:    bne a0, a1, .LBB0_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB0_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_small_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, 20
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB0_2
+; RV32IFD-NEXT:    addi a1, zero, 20
+; RV32IFD-NEXT:    bne a0, a1, .LBB0_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB0_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, 20
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -38,24 +38,24 @@ define i32 @ne_small_pos(i32 %in0) minsize {
 define i32 @ne_small_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_small_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    c.li a2, -20
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    bne a1, a2, .LBB1_2
+; RV32IFDC-NEXT:    c.li a1, -20
+; RV32IFDC-NEXT:    bne a0, a1, .LBB1_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB1_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_small_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -20
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB1_2
+; RV32IFD-NEXT:    addi a1, zero, -20
+; RV32IFD-NEXT:    bne a0, a1, .LBB1_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB1_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, -20
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -66,24 +66,24 @@ define i32 @ne_small_neg(i32 %in0) minsize {
 define i32 @ne_small_edge_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_small_edge_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    c.li a2, 31
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    bne a1, a2, .LBB2_2
+; RV32IFDC-NEXT:    c.li a1, 31
+; RV32IFDC-NEXT:    bne a0, a1, .LBB2_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB2_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_small_edge_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, 31
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB2_2
+; RV32IFD-NEXT:    addi a1, zero, 31
+; RV32IFD-NEXT:    bne a0, a1, .LBB2_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB2_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, 31
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -94,24 +94,24 @@ define i32 @ne_small_edge_pos(i32 %in0) minsize {
 define i32 @ne_small_edge_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_small_edge_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    c.li a2, -32
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    bne a1, a2, .LBB3_2
+; RV32IFDC-NEXT:    c.li a1, -32
+; RV32IFDC-NEXT:    bne a0, a1, .LBB3_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB3_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_small_edge_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -32
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB3_2
+; RV32IFD-NEXT:    addi a1, zero, -32
+; RV32IFD-NEXT:    bne a0, a1, .LBB3_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB3_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, -32
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -123,23 +123,24 @@ define i32 @ne_small_edge_neg(i32 %in0) minsize {
 define i32 @ne_medium_ledge_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_medium_ledge_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, -33
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.bnez a1, .LBB4_2
+; RV32IFDC-NEXT:    addi a0, a0, -33
+; RV32IFDC-NEXT:    c.bnez a0, .LBB4_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB4_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_medium_ledge_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, 33
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB4_2
+; RV32IFD-NEXT:    addi a1, zero, 33
+; RV32IFD-NEXT:    bne a0, a1, .LBB4_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB4_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, 33
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -151,23 +152,24 @@ define i32 @ne_medium_ledge_pos(i32 %in0) minsize {
 define i32 @ne_medium_ledge_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_medium_ledge_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, 33
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.bnez a1, .LBB5_2
+; RV32IFDC-NEXT:    addi a0, a0, 33
+; RV32IFDC-NEXT:    c.bnez a0, .LBB5_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB5_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_medium_ledge_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -33
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB5_2
+; RV32IFD-NEXT:    addi a1, zero, -33
+; RV32IFD-NEXT:    bne a0, a1, .LBB5_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB5_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, -33
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -179,23 +181,24 @@ define i32 @ne_medium_ledge_neg(i32 %in0) minsize {
 define i32 @ne_medium_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_medium_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, -63
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.bnez a1, .LBB6_2
+; RV32IFDC-NEXT:    addi a0, a0, -63
+; RV32IFDC-NEXT:    c.bnez a0, .LBB6_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB6_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_medium_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, 63
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB6_2
+; RV32IFD-NEXT:    addi a1, zero, 63
+; RV32IFD-NEXT:    bne a0, a1, .LBB6_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB6_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, 63
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -207,23 +210,24 @@ define i32 @ne_medium_pos(i32 %in0) minsize {
 define i32 @ne_medium_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_medium_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, 63
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.bnez a1, .LBB7_2
+; RV32IFDC-NEXT:    addi a0, a0, 63
+; RV32IFDC-NEXT:    c.bnez a0, .LBB7_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB7_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_medium_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -63
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB7_2
+; RV32IFD-NEXT:    addi a1, zero, -63
+; RV32IFD-NEXT:    bne a0, a1, .LBB7_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB7_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, -63
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -235,23 +239,24 @@ define i32 @ne_medium_neg(i32 %in0) minsize {
 define i32 @ne_medium_bedge_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_medium_bedge_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, -2047
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.bnez a1, .LBB8_2
+; RV32IFDC-NEXT:    addi a0, a0, -2047
+; RV32IFDC-NEXT:    c.bnez a0, .LBB8_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB8_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_medium_bedge_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, 2047
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB8_2
+; RV32IFD-NEXT:    addi a1, zero, 2047
+; RV32IFD-NEXT:    bne a0, a1, .LBB8_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB8_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, 2047
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -263,23 +268,24 @@ define i32 @ne_medium_bedge_pos(i32 %in0) minsize {
 define i32 @ne_medium_bedge_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_medium_bedge_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, 2047
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.bnez a1, .LBB9_2
+; RV32IFDC-NEXT:    addi a0, a0, 2047
+; RV32IFDC-NEXT:    c.bnez a0, .LBB9_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB9_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_medium_bedge_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -2047
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB9_2
+; RV32IFD-NEXT:    addi a1, zero, -2047
+; RV32IFD-NEXT:    bne a0, a1, .LBB9_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB9_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, -2047
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -290,26 +296,26 @@ define i32 @ne_medium_bedge_neg(i32 %in0) minsize {
 define i32 @ne_big_ledge_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_big_ledge_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    c.li a0, 1
-; RV32IFDC-NEXT:    slli a2, a0, 11
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    bne a1, a2, .LBB10_2
+; RV32IFDC-NEXT:    c.li a1, 1
+; RV32IFDC-NEXT:    c.slli a1, 11
+; RV32IFDC-NEXT:    bne a0, a1, .LBB10_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB10_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_big_ledge_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a0, zero, 1
-; RV32IFD-NEXT:    slli a2, a0, 11
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB10_2
+; RV32IFD-NEXT:    addi a1, zero, 1
+; RV32IFD-NEXT:    slli a1, a1, 11
+; RV32IFD-NEXT:    bne a0, a1, .LBB10_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB10_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, 2048
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -320,24 +326,24 @@ define i32 @ne_big_ledge_pos(i32 %in0) minsize {
 define i32 @ne_big_ledge_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: ne_big_ledge_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    addi a2, zero, -2048
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    bne a1, a2, .LBB11_2
+; RV32IFDC-NEXT:    addi a1, zero, -2048
+; RV32IFDC-NEXT:    bne a0, a1, .LBB11_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB11_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: ne_big_ledge_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -2048
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    bne a1, a2, .LBB11_2
+; RV32IFD-NEXT:    addi a1, zero, -2048
+; RV32IFD-NEXT:    bne a0, a1, .LBB11_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB11_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp ne i32 %in0, -2048
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -351,24 +357,24 @@ define i32 @ne_big_ledge_neg(i32 %in0) minsize {
 define i32 @eq_small_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_small_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    c.li a2, 20
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    beq a1, a2, .LBB12_2
+; RV32IFDC-NEXT:    c.li a1, 20
+; RV32IFDC-NEXT:    beq a0, a1, .LBB12_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB12_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_small_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, 20
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB12_2
+; RV32IFD-NEXT:    addi a1, zero, 20
+; RV32IFD-NEXT:    beq a0, a1, .LBB12_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB12_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, 20
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -379,24 +385,24 @@ define i32 @eq_small_pos(i32 %in0) minsize {
 define i32 @eq_small_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_small_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    c.li a2, -20
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    beq a1, a2, .LBB13_2
+; RV32IFDC-NEXT:    c.li a1, -20
+; RV32IFDC-NEXT:    beq a0, a1, .LBB13_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB13_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_small_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -20
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB13_2
+; RV32IFD-NEXT:    addi a1, zero, -20
+; RV32IFD-NEXT:    beq a0, a1, .LBB13_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB13_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, -20
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -407,24 +413,24 @@ define i32 @eq_small_neg(i32 %in0) minsize {
 define i32 @eq_small_edge_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_small_edge_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    c.li a2, 31
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    beq a1, a2, .LBB14_2
+; RV32IFDC-NEXT:    c.li a1, 31
+; RV32IFDC-NEXT:    beq a0, a1, .LBB14_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB14_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_small_edge_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, 31
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB14_2
+; RV32IFD-NEXT:    addi a1, zero, 31
+; RV32IFD-NEXT:    beq a0, a1, .LBB14_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB14_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, 31
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -435,24 +441,24 @@ define i32 @eq_small_edge_pos(i32 %in0) minsize {
 define i32 @eq_small_edge_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_small_edge_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    c.li a2, -32
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    beq a1, a2, .LBB15_2
+; RV32IFDC-NEXT:    c.li a1, -32
+; RV32IFDC-NEXT:    beq a0, a1, .LBB15_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB15_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_small_edge_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -32
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB15_2
+; RV32IFD-NEXT:    addi a1, zero, -32
+; RV32IFD-NEXT:    beq a0, a1, .LBB15_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB15_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, -32
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -464,23 +470,24 @@ define i32 @eq_small_edge_neg(i32 %in0) minsize {
 define i32 @eq_medium_ledge_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_medium_ledge_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, -33
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.beqz a1, .LBB16_2
+; RV32IFDC-NEXT:    addi a0, a0, -33
+; RV32IFDC-NEXT:    c.beqz a0, .LBB16_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB16_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_medium_ledge_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, 33
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB16_2
+; RV32IFD-NEXT:    addi a1, zero, 33
+; RV32IFD-NEXT:    beq a0, a1, .LBB16_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB16_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, 33
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -492,23 +499,24 @@ define i32 @eq_medium_ledge_pos(i32 %in0) minsize {
 define i32 @eq_medium_ledge_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_medium_ledge_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, 33
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.beqz a1, .LBB17_2
+; RV32IFDC-NEXT:    addi a0, a0, 33
+; RV32IFDC-NEXT:    c.beqz a0, .LBB17_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB17_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_medium_ledge_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -33
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB17_2
+; RV32IFD-NEXT:    addi a1, zero, -33
+; RV32IFD-NEXT:    beq a0, a1, .LBB17_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB17_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, -33
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -520,23 +528,24 @@ define i32 @eq_medium_ledge_neg(i32 %in0) minsize {
 define i32 @eq_medium_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_medium_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, -63
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.beqz a1, .LBB18_2
+; RV32IFDC-NEXT:    addi a0, a0, -63
+; RV32IFDC-NEXT:    c.beqz a0, .LBB18_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB18_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_medium_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, 63
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB18_2
+; RV32IFD-NEXT:    addi a1, zero, 63
+; RV32IFD-NEXT:    beq a0, a1, .LBB18_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB18_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, 63
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -548,23 +557,24 @@ define i32 @eq_medium_pos(i32 %in0) minsize {
 define i32 @eq_medium_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_medium_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, 63
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.beqz a1, .LBB19_2
+; RV32IFDC-NEXT:    addi a0, a0, 63
+; RV32IFDC-NEXT:    c.beqz a0, .LBB19_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB19_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_medium_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -63
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB19_2
+; RV32IFD-NEXT:    addi a1, zero, -63
+; RV32IFD-NEXT:    beq a0, a1, .LBB19_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB19_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, -63
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -576,23 +586,24 @@ define i32 @eq_medium_neg(i32 %in0) minsize {
 define i32 @eq_medium_bedge_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_medium_bedge_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, -2047
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.beqz a1, .LBB20_2
+; RV32IFDC-NEXT:    addi a0, a0, -2047
+; RV32IFDC-NEXT:    c.beqz a0, .LBB20_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB20_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_medium_bedge_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, 2047
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB20_2
+; RV32IFD-NEXT:    addi a1, zero, 2047
+; RV32IFD-NEXT:    beq a0, a1, .LBB20_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB20_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, 2047
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -604,23 +615,24 @@ define i32 @eq_medium_bedge_pos(i32 %in0) minsize {
 define i32 @eq_medium_bedge_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_medium_bedge_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    addi a1, a0, 2047
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    c.beqz a1, .LBB21_2
+; RV32IFDC-NEXT:    addi a0, a0, 2047
+; RV32IFDC-NEXT:    c.beqz a0, .LBB21_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB21_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_medium_bedge_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -2047
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB21_2
+; RV32IFD-NEXT:    addi a1, zero, -2047
+; RV32IFD-NEXT:    beq a0, a1, .LBB21_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB21_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, -2047
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -631,26 +643,26 @@ define i32 @eq_medium_bedge_neg(i32 %in0) minsize {
 define i32 @eq_big_ledge_pos(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_big_ledge_pos:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    c.li a0, 1
-; RV32IFDC-NEXT:    slli a2, a0, 11
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    beq a1, a2, .LBB22_2
+; RV32IFDC-NEXT:    c.li a1, 1
+; RV32IFDC-NEXT:    c.slli a1, 11
+; RV32IFDC-NEXT:    beq a0, a1, .LBB22_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB22_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_big_ledge_pos:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a0, zero, 1
-; RV32IFD-NEXT:    slli a2, a0, 11
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB22_2
+; RV32IFD-NEXT:    addi a1, zero, 1
+; RV32IFD-NEXT:    slli a1, a1, 11
+; RV32IFD-NEXT:    beq a0, a1, .LBB22_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB22_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, 2048
   %toRet = select i1 %cmp, i32 -99, i32 42
@@ -661,24 +673,24 @@ define i32 @eq_big_ledge_pos(i32 %in0) minsize {
 define i32 @eq_big_ledge_neg(i32 %in0) minsize {
 ; RV32IFDC-LABEL: eq_big_ledge_neg:
 ; RV32IFDC:       # %bb.0:
-; RV32IFDC-NEXT:    c.mv a1, a0
-; RV32IFDC-NEXT:    addi a2, zero, -2048
-; RV32IFDC-NEXT:    addi a0, zero, -99
-; RV32IFDC-NEXT:    beq a1, a2, .LBB23_2
+; RV32IFDC-NEXT:    addi a1, zero, -2048
+; RV32IFDC-NEXT:    beq a0, a1, .LBB23_2
 ; RV32IFDC-NEXT:  # %bb.1:
 ; RV32IFDC-NEXT:    addi a0, zero, 42
+; RV32IFDC-NEXT:    c.jr ra
 ; RV32IFDC-NEXT:  .LBB23_2:
+; RV32IFDC-NEXT:    addi a0, zero, -99
 ; RV32IFDC-NEXT:    c.jr ra
 ;
 ; RV32IFD-LABEL: eq_big_ledge_neg:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi a1, a0, 0
-; RV32IFD-NEXT:    addi a2, zero, -2048
-; RV32IFD-NEXT:    addi a0, zero, -99
-; RV32IFD-NEXT:    beq a1, a2, .LBB23_2
+; RV32IFD-NEXT:    addi a1, zero, -2048
+; RV32IFD-NEXT:    beq a0, a1, .LBB23_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    addi a0, zero, 42
+; RV32IFD-NEXT:    jalr zero, 0(ra)
 ; RV32IFD-NEXT:  .LBB23_2:
+; RV32IFD-NEXT:    addi a0, zero, -99
 ; RV32IFD-NEXT:    jalr zero, 0(ra)
   %cmp = icmp eq i32 %in0, -2048
   %toRet = select i1 %cmp, i32 -99, i32 42
diff --git a/llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll b/llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
index 19faef6853eaa..eb84774014a4b 100644
--- a/llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
+++ b/llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
@@ -184,13 +184,13 @@ declare i32 @toupper()
 define signext i32 @overlap_live_ranges(ptr %arg, i32 signext %arg1) {
 ; CHECK-LABEL: overlap_live_ranges:
 ; CHECK:       # %bb.0: # %bb
-; CHECK-NEXT:    li a3, 1
-; CHECK-NEXT:    li a2, 13
-; CHECK-NEXT:    bne a1, a3, .LBB1_2
+; CHECK-NEXT:    li a2, 1
+; CHECK-NEXT:    bne a1, a2, .LBB1_2
 ; CHECK-NEXT:  # %bb.1: # %bb2
-; CHECK-NEXT:    lw a2, 4(a0)
-; CHECK-NEXT:  .LBB1_2: # %bb5
-; CHECK-NEXT:    mv a0, a2
+; CHECK-NEXT:    lw a0, 4(a0)
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    li a0, 13
 ; CHECK-NEXT:    ret
 bb:
   %i = icmp eq i32 %arg1, 1
@@ -308,34 +308,37 @@ define signext i32 @branch_dispatch(i8 %a) {
 ; CHECK-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset ra, -8
 ; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_remember_state
 ; CHECK-NEXT:    andi a0, a0, 255
 ; CHECK-NEXT:    li a1, 32
-; CHECK-NEXT:    li s0, 13
-; CHECK-NEXT:    beq a0, a1, .LBB3_8
+; CHECK-NEXT:    beq a0, a1, .LBB3_7
 ; CHECK-NEXT:  # %bb.1: # %case.1
 ; CHECK-NEXT:    li a1, 12
-; CHECK-NEXT:    li s0, 53
 ; CHECK-NEXT:    beq a0, a1, .LBB3_8
 ; CHECK-NEXT:  # %bb.2: # %case.2
 ; CHECK-NEXT:    li a1, 70
-; CHECK-NEXT:    li s0, 33
-; CHECK-NEXT:    beq a0, a1, .LBB3_8
+; CHECK-NEXT:    beq a0, a1, .LBB3_9
 ; CHECK-NEXT:  # %bb.3: # %case.3
 ; CHECK-NEXT:    li a1, 234
 ; CHECK-NEXT:    li s0, 23
-; CHECK-NEXT:    beq a0, a1, .LBB3_8
+; CHECK-NEXT:    beq a0, a1, .LBB3_10
 ; CHECK-NEXT:  # %bb.4: # %case.4
-; CHECK-NEXT:    beqz a0, .LBB3_7
+; CHECK-NEXT:    beqz a0, .LBB3_11
 ; CHECK-NEXT:  # %bb.5: # %case.5
 ; CHECK-NEXT:    li a1, 5
+; CHECK-NEXT:    bne a0, a1, .LBB3_10
+; CHECK-NEXT:  # %bb.6:
 ; CHECK-NEXT:    li s0, 54
-; CHECK-NEXT:    beq a0, a1, .LBB3_8
-; CHECK-NEXT:  # %bb.6: # %case.default
-; CHECK-NEXT:    li s0, 23
-; CHECK-NEXT:    j .LBB3_8
+; CHECK-NEXT:    j .LBB3_10
 ; CHECK-NEXT:  .LBB3_7:
-; CHECK-NEXT:    li s0, 644
-; CHECK-NEXT:  .LBB3_8: # %merge
+; CHECK-NEXT:    li s0, 13
+; CHECK-NEXT:    j .LBB3_10
+; CHECK-NEXT:  .LBB3_8:
+; CHECK-NEXT:    li s0, 53
+; CHECK-NEXT:    j .LBB3_10
+; CHECK-NEXT:  .LBB3_9:
+; CHECK-NEXT:    li s0, 33
+; CHECK-NEXT:  .LBB3_10: # %merge
 ; CHECK-NEXT:    mv a0, s0
 ; CHECK-NEXT:    call use
 ; CHECK-NEXT:    mv a0, s0
@@ -346,6 +349,10 @@ define signext i32 @branch_dispatch(i8 %a) {
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB3_11:
+; CHECK-NEXT:    .cfi_restore_state
+; CHECK-NEXT:    li s0, 644
+; CHECK-NEXT:    j .LBB3_10
 case.0:
   %c0 = icmp ne i8 %a, 32
   br i1 %c0, label %case.1, label %merge
diff --git a/llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll b/llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
index f69909e76d4c1..a2c572e07ff7d 100644
--- a/llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
+++ b/llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
@@ -5,15 +5,13 @@ define signext i32 @mulw(i32 signext %s, i32 signext %n, i32 signext %k) nounwin
 ; CHECK-LABEL: mulw:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li a2, 1
-; CHECK-NEXT:    bge a0, a1, .LBB0_3
-; CHECK-NEXT:  # %bb.1: # %for.body.preheader
-; CHECK-NEXT:    li a2, 1
-; CHECK-NEXT:  .LBB0_2: # %for.body
+; CHECK-NEXT:    bge a0, a1, .LBB0_2
+; CHECK-NEXT:  .LBB0_1: # %for.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    mulw a2, a0, a2
 ; CHECK-NEXT:    addiw a0, a0, 1
-; CHECK-NEXT:    blt a0, a1, .LBB0_2
-; CHECK-NEXT:  .LBB0_3: # %for.cond.cleanup
+; CHECK-NEXT:    blt a0, a1, .LBB0_1
+; CHECK-NEXT:  .LBB0_2: # %for.cond.cleanup
 ; CHECK-NEXT:    mv a0, a2
 ; CHECK-NEXT:    ret
 entry:
diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
index 96081fc462d6f..6a24d03de8749 100644
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -61,22 +61,22 @@ define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {
 define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
 ; RV32-LABEL: select_const_int_harder:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    mv a1, a0
-; RV32-NEXT:    li a0, 6
-; RV32-NEXT:    bnez a1, .LBB3_2
+; RV32-NEXT:    bnez a0, .LBB3_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    li a0, 38
+; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB3_2:
+; RV32-NEXT:    li a0, 6
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: select_const_int_harder:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    mv a1, a0
-; RV64-NEXT:    li a0, 6
-; RV64-NEXT:    bnez a1, .LBB3_2
+; RV64-NEXT:    bnez a0, .LBB3_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    li a0, 38
+; RV64-NEXT:    ret
 ; RV64-NEXT:  .LBB3_2:
+; RV64-NEXT:    li a0, 6
 ; RV64-NEXT:    ret
   %1 = select i1 %a, i32 6, i32 38
   ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index 252cf776299b3..4405cc3f5e163 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -1585,22 +1585,22 @@ define i32 @select_cst_not5(i32 signext %a, i32 signext %b) {
 define i32 @select_cst_unknown(i32 signext %a, i32 signext %b) {
 ; RV32IM-LABEL: select_cst_unknown:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a2, a0
-; RV32IM-NEXT:    li a0, 5
-; RV32IM-NEXT:    blt a2, a1, .LBB42_2
+; RV32IM-NEXT:    blt a0, a1, .LBB42_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    li a0, -7
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB42_2:
+; RV32IM-NEXT:    li a0, 5
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst_unknown:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a2, a0
-; RV64IM-NEXT:    li a0, 5
-; RV64IM-NEXT:    blt a2, a1, .LBB42_2
+; RV64IM-NEXT:    blt a0, a1, .LBB42_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    li a0, -7
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB42_2:
+; RV64IM-NEXT:    li a0, 5
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst_unknown:
@@ -1626,22 +1626,22 @@ define i32 @select_cst_unknown(i32 signext %a, i32 signext %b) {
 define i32 @select_cst1(i1 zeroext %cond) {
 ; RV32IM-LABEL: select_cst1:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a1, a0
-; RV32IM-NEXT:    li a0, 10
-; RV32IM-NEXT:    bnez a1, .LBB43_2
+; RV32IM-NEXT:    bnez a0, .LBB43_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    li a0, 20
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB43_2:
+; RV32IM-NEXT:    li a0, 10
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst1:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a1, a0
-; RV64IM-NEXT:    li a0, 10
-; RV64IM-NEXT:    bnez a1, .LBB43_2
+; RV64IM-NEXT:    bnez a0, .LBB43_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    li a0, 20
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB43_2:
+; RV64IM-NEXT:    li a0, 10
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst1:
@@ -1664,24 +1664,24 @@ define i32 @select_cst1(i1 zeroext %cond) {
 define i32 @select_cst2(i1 zeroext %cond) {
 ; RV32IM-LABEL: select_cst2:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a1, a0
-; RV32IM-NEXT:    li a0, 10
-; RV32IM-NEXT:    bnez a1, .LBB44_2
+; RV32IM-NEXT:    bnez a0, .LBB44_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    lui a0, 5
 ; RV32IM-NEXT:    addi a0, a0, -480
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB44_2:
+; RV32IM-NEXT:    li a0, 10
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst2:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a1, a0
-; RV64IM-NEXT:    li a0, 10
-; RV64IM-NEXT:    bnez a1, .LBB44_2
+; RV64IM-NEXT:    bnez a0, .LBB44_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    lui a0, 5
 ; RV64IM-NEXT:    addiw a0, a0, -480
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB44_2:
+; RV64IM-NEXT:    li a0, 10
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst2:
@@ -1782,24 +1782,24 @@ define i32 @select_cst4(i1 zeroext %cond) {
 define i32 @select_cst5(i1 zeroext %cond) {
 ; RV32IM-LABEL: select_cst5:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a1, a0
-; RV32IM-NEXT:    li a0, 2047
-; RV32IM-NEXT:    bnez a1, .LBB47_2
+; RV32IM-NEXT:    bnez a0, .LBB47_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    lui a0, 1
 ; RV32IM-NEXT:    addi a0, a0, -2047
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB47_2:
+; RV32IM-NEXT:    li a0, 2047
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst5:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a1, a0
-; RV64IM-NEXT:    li a0, 2047
-; RV64IM-NEXT:    bnez a1, .LBB47_2
+; RV64IM-NEXT:    bnez a0, .LBB47_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    lui a0, 1
 ; RV64IM-NEXT:    addiw a0, a0, -2047
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB47_2:
+; RV64IM-NEXT:    li a0, 2047
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst5:
@@ -1862,22 +1862,22 @@ define i32 @select_cst5_invert(i1 zeroext %cond) {
 define i32 @select_cst_diff2(i1 zeroext %cond) {
 ; RV32IM-LABEL: select_cst_diff2:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a1, a0
-; RV32IM-NEXT:    li a0, 120
-; RV32IM-NEXT:    bnez a1, .LBB49_2
+; RV32IM-NEXT:    bnez a0, .LBB49_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    li a0, 122
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB49_2:
+; RV32IM-NEXT:    li a0, 120
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst_diff2:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a1, a0
-; RV64IM-NEXT:    li a0, 120
-; RV64IM-NEXT:    bnez a1, .LBB49_2
+; RV64IM-NEXT:    bnez a0, .LBB49_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    li a0, 122
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB49_2:
+; RV64IM-NEXT:    li a0, 120
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst_diff2:
@@ -1900,22 +1900,22 @@ define i32 @select_cst_diff2(i1 zeroext %cond) {
 define i32 @select_cst_diff2_invert(i1 zeroext %cond) {
 ; RV32IM-LABEL: select_cst_diff2_invert:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a1, a0
-; RV32IM-NEXT:    li a0, 122
-; RV32IM-NEXT:    bnez a1, .LBB50_2
+; RV32IM-NEXT:    bnez a0, .LBB50_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    li a0, 120
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB50_2:
+; RV32IM-NEXT:    li a0, 122
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst_diff2_invert:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a1, a0
-; RV64IM-NEXT:    li a0, 122
-; RV64IM-NEXT:    bnez a1, .LBB50_2
+; RV64IM-NEXT:    bnez a0, .LBB50_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    li a0, 120
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB50_2:
+; RV64IM-NEXT:    li a0, 122
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst_diff2_invert:
@@ -1938,22 +1938,22 @@ define i32 @select_cst_diff2_invert(i1 zeroext %cond) {
 define i32 @select_cst_diff4(i1 zeroext %cond) {
 ; RV32IM-LABEL: select_cst_diff4:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a1, a0
-; RV32IM-NEXT:    li a0, 10
-; RV32IM-NEXT:    bnez a1, .LBB51_2
+; RV32IM-NEXT:    bnez a0, .LBB51_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    li a0, 6
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB51_2:
+; RV32IM-NEXT:    li a0, 10
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst_diff4:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a1, a0
-; RV64IM-NEXT:    li a0, 10
-; RV64IM-NEXT:    bnez a1, .LBB51_2
+; RV64IM-NEXT:    bnez a0, .LBB51_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    li a0, 6
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB51_2:
+; RV64IM-NEXT:    li a0, 10
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst_diff4:
@@ -1976,22 +1976,22 @@ define i32 @select_cst_diff4(i1 zeroext %cond) {
 define i32 @select_cst_diff4_invert(i1 zeroext %cond) {
 ; RV32IM-LABEL: select_cst_diff4_invert:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a1, a0
-; RV32IM-NEXT:    li a0, 6
-; RV32IM-NEXT:    bnez a1, .LBB52_2
+; RV32IM-NEXT:    bnez a0, .LBB52_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    li a0, 10
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB52_2:
+; RV32IM-NEXT:    li a0, 6
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst_diff4_invert:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a1, a0
-; RV64IM-NEXT:    li a0, 6
-; RV64IM-NEXT:    bnez a1, .LBB52_2
+; RV64IM-NEXT:    bnez a0, .LBB52_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    li a0, 10
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB52_2:
+; RV64IM-NEXT:    li a0, 6
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst_diff4_invert:
@@ -2014,22 +2014,22 @@ define i32 @select_cst_diff4_invert(i1 zeroext %cond) {
 define i32 @select_cst_diff8(i1 zeroext %cond) {
 ; RV32IM-LABEL: select_cst_diff8:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a1, a0
-; RV32IM-NEXT:    li a0, 14
-; RV32IM-NEXT:    bnez a1, .LBB53_2
+; RV32IM-NEXT:    bnez a0, .LBB53_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    li a0, 6
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB53_2:
+; RV32IM-NEXT:    li a0, 14
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst_diff8:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a1, a0
-; RV64IM-NEXT:    li a0, 14
-; RV64IM-NEXT:    bnez a1, .LBB53_2
+; RV64IM-NEXT:    bnez a0, .LBB53_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    li a0, 6
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB53_2:
+; RV64IM-NEXT:    li a0, 14
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst_diff8:
@@ -2052,22 +2052,22 @@ define i32 @select_cst_diff8(i1 zeroext %cond) {
 define i32 @select_cst_diff8_invert(i1 zeroext %cond) {
 ; RV32IM-LABEL: select_cst_diff8_invert:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a1, a0
-; RV32IM-NEXT:    li a0, 6
-; RV32IM-NEXT:    bnez a1, .LBB54_2
+; RV32IM-NEXT:    bnez a0, .LBB54_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    li a0, 14
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB54_2:
+; RV32IM-NEXT:    li a0, 6
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst_diff8_invert:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a1, a0
-; RV64IM-NEXT:    li a0, 6
-; RV64IM-NEXT:    bnez a1, .LBB54_2
+; RV64IM-NEXT:    bnez a0, .LBB54_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    li a0, 14
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB54_2:
+; RV64IM-NEXT:    li a0, 6
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst_diff8_invert:
@@ -2091,22 +2091,22 @@ define i32 @select_cst_diff8_invert(i1 zeroext %cond) {
 define i32 @select_cst_diff1024(i1 zeroext %cond) {
 ; RV32IM-LABEL: select_cst_diff1024:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a1, a0
-; RV32IM-NEXT:    li a0, 1030
-; RV32IM-NEXT:    bnez a1, .LBB55_2
+; RV32IM-NEXT:    bnez a0, .LBB55_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    li a0, 6
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB55_2:
+; RV32IM-NEXT:    li a0, 1030
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst_diff1024:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a1, a0
-; RV64IM-NEXT:    li a0, 1030
-; RV64IM-NEXT:    bnez a1, .LBB55_2
+; RV64IM-NEXT:    bnez a0, .LBB55_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    li a0, 6
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB55_2:
+; RV64IM-NEXT:    li a0, 1030
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst_diff1024:
@@ -2129,22 +2129,22 @@ define i32 @select_cst_diff1024(i1 zeroext %cond) {
 define i32 @select_cst_diff1024_invert(i1 zeroext %cond) {
 ; RV32IM-LABEL: select_cst_diff1024_invert:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    mv a1, a0
-; RV32IM-NEXT:    li a0, 6
-; RV32IM-NEXT:    bnez a1, .LBB56_2
+; RV32IM-NEXT:    bnez a0, .LBB56_2
 ; RV32IM-NEXT:  # %bb.1:
 ; RV32IM-NEXT:    li a0, 1030
+; RV32IM-NEXT:    ret
 ; RV32IM-NEXT:  .LBB56_2:
+; RV32IM-NEXT:    li a0, 6
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_cst_diff1024_invert:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    mv a1, a0
-; RV64IM-NEXT:    li a0, 6
-; RV64IM-NEXT:    bnez a1, .LBB56_2
+; RV64IM-NEXT:    bnez a0, .LBB56_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    li a0, 1030
+; RV64IM-NEXT:    ret
 ; RV64IM-NEXT:  .LBB56_2:
+; RV64IM-NEXT:    li a0, 6
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_cst_diff1024_invert:
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll
index 11b0e5263e112..e0a16aa05cd00 100644
--- a/llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -1032,17 +1032,19 @@ bb7:                                              ; preds = %bb2
 define signext i32 @bug(i32 signext %x) {
 ; CHECK-LABEL: bug:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    beqz a0, .LBB18_4
+; CHECK-NEXT:    beqz a0, .LBB18_5
 ; CHECK-NEXT:  # %bb.1: # %if.end
-; CHECK-NEXT:    srliw a2, a0, 16
-; CHECK-NEXT:    seqz a1, a2
-; CHECK-NEXT:    slli a1, a1, 4
-; CHECK-NEXT:    sllw a0, a0, a1
-; CHECK-NEXT:    li a1, 16
-; CHECK-NEXT:    beqz a2, .LBB18_3
+; CHECK-NEXT:    srliw a1, a0, 16
+; CHECK-NEXT:    seqz a2, a1
+; CHECK-NEXT:    slli a2, a2, 4
+; CHECK-NEXT:    sllw a0, a0, a2
+; CHECK-NEXT:    beqz a1, .LBB18_3
 ; CHECK-NEXT:  # %bb.2: # %if.end
 ; CHECK-NEXT:    li a1, 32
-; CHECK-NEXT:  .LBB18_3: # %if.end
+; CHECK-NEXT:    j .LBB18_4
+; CHECK-NEXT:  .LBB18_3:
+; CHECK-NEXT:    li a1, 16
+; CHECK-NEXT:  .LBB18_4: # %if.end
 ; CHECK-NEXT:    srliw a2, a0, 24
 ; CHECK-NEXT:    seqz a2, a2
 ; CHECK-NEXT:    slli a3, a2, 3
@@ -1067,22 +1069,24 @@ define signext i32 @bug(i32 signext %x) {
 ; CHECK-NEXT:    not a0, a0
 ; CHECK-NEXT:    srli a0, a0, 31
 ; CHECK-NEXT:    addw a0, a1, a0
-; CHECK-NEXT:  .LBB18_4: # %cleanup
+; CHECK-NEXT:  .LBB18_5: # %cleanup
 ; CHECK-NEXT:    ret
 ;
 ; NOREMOVAL-LABEL: bug:
 ; NOREMOVAL:       # %bb.0: # %entry
-; NOREMOVAL-NEXT:    beqz a0, .LBB18_4
+; NOREMOVAL-NEXT:    beqz a0, .LBB18_5
 ; NOREMOVAL-NEXT:  # %bb.1: # %if.end
-; NOREMOVAL-NEXT:    srliw a2, a0, 16
-; NOREMOVAL-NEXT:    seqz a1, a2
-; NOREMOVAL-NEXT:    slli a1, a1, 4
-; NOREMOVAL-NEXT:    sllw a0, a0, a1
-; NOREMOVAL-NEXT:    li a1, 16
-; NOREMOVAL-NEXT:    beqz a2, .LBB18_3
+; NOREMOVAL-NEXT:    srliw a1, a0, 16
+; NOREMOVAL-NEXT:    seqz a2, a1
+; NOREMOVAL-NEXT:    slli a2, a2, 4
+; NOREMOVAL-NEXT:    sllw a0, a0, a2
+; NOREMOVAL-NEXT:    beqz a1, .LBB18_3
 ; NOREMOVAL-NEXT:  # %bb.2: # %if.end
 ; NOREMOVAL-NEXT:    li a1, 32
-; NOREMOVAL-NEXT:  .LBB18_3: # %if.end
+; NOREMOVAL-NEXT:    j .LBB18_4
+; NOREMOVAL-NEXT:  .LBB18_3:
+; NOREMOVAL-NEXT:    li a1, 16
+; NOREMOVAL-NEXT:  .LBB18_4: # %if.end
 ; NOREMOVAL-NEXT:    srliw a2, a0, 24
 ; NOREMOVAL-NEXT:    seqz a2, a2
 ; NOREMOVAL-NEXT:    slli a3, a2, 3
@@ -1107,7 +1111,7 @@ define signext i32 @bug(i32 signext %x) {
 ; NOREMOVAL-NEXT:    not a0, a0
 ; NOREMOVAL-NEXT:    srli a0, a0, 31
 ; NOREMOVAL-NEXT:    addw a0, a1, a0
-; NOREMOVAL-NEXT:  .LBB18_4: # %cleanup
+; NOREMOVAL-NEXT:  .LBB18_5: # %cleanup
 ; NOREMOVAL-NEXT:    ret
 entry:
   %tobool.not = icmp eq i32 %x, 0
diff --git a/llvm/test/CodeGen/RISCV/typepromotion-overflow.ll b/llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
index ec7e0ecce80ca..ae1aabed49805 100644
--- a/llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
+++ b/llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
@@ -7,13 +7,14 @@ define zeroext i16 @overflow_add(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    ori a0, a0, 1
 ; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srli a1, a0, 48
-; CHECK-NEXT:    li a2, 1024
-; CHECK-NEXT:    li a0, 2
-; CHECK-NEXT:    bltu a2, a1, .LBB0_2
+; CHECK-NEXT:    srli a0, a0, 48
+; CHECK-NEXT:    li a1, 1024
+; CHECK-NEXT:    bltu a1, a0, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 5
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    li a0, 2
 ; CHECK-NEXT:    ret
   %add = add i16 %b, %a
   %or = or i16 %add, 1
@@ -28,13 +29,14 @@ define zeroext i16 @overflow_sub(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-NEXT:    subw a0, a0, a1
 ; CHECK-NEXT:    ori a0, a0, 1
 ; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srli a1, a0, 48
-; CHECK-NEXT:    li a2, 1024
-; CHECK-NEXT:    li a0, 2
-; CHECK-NEXT:    bltu a2, a1, .LBB1_2
+; CHECK-NEXT:    srli a0, a0, 48
+; CHECK-NEXT:    li a1, 1024
+; CHECK-NEXT:    bltu a1, a0, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 5
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    li a0, 2
 ; CHECK-NEXT:    ret
   %add = sub i16 %a, %b
   %or = or i16 %add, 1
@@ -49,13 +51,14 @@ define zeroext i16 @overflow_mul(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-NEXT:    mul a0, a1, a0
 ; CHECK-NEXT:    ori a0, a0, 1
 ; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srli a1, a0, 48
-; CHECK-NEXT:    li a2, 1024
-; CHECK-NEXT:    li a0, 2
-; CHECK-NEXT:    bltu a2, a1, .LBB2_2
+; CHECK-NEXT:    srli a0, a0, 48
+; CHECK-NEXT:    li a1, 1024
+; CHECK-NEXT:    bltu a1, a0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 5
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB2_2:
+; CHECK-NEXT:    li a0, 2
 ; CHECK-NEXT:    ret
   %add = mul i16 %b, %a
   %or = or i16 %add, 1
@@ -70,13 +73,14 @@ define zeroext i16 @overflow_shl(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-NEXT:    sll a0, a0, a1
 ; CHECK-NEXT:    ori a0, a0, 1
 ; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srli a1, a0, 48
-; CHECK-NEXT:    li a2, 1024
-; CHECK-NEXT:    li a0, 2
-; CHECK-NEXT:    bltu a2, a1, .LBB3_2
+; CHECK-NEXT:    srli a0, a0, 48
+; CHECK-NEXT:    li a1, 1024
+; CHECK-NEXT:    bltu a1, a0, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 5
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB3_2:
+; CHECK-NEXT:    li a0, 2
 ; CHECK-NEXT:    ret
   %add = shl i16 %a, %b
   %or = or i16 %add, 1
@@ -89,12 +93,13 @@ define i32 @overflow_add_no_consts(i8 zeroext %a, i8 zeroext %b, i8 zeroext %lim
 ; CHECK-LABEL: overflow_add_no_consts:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    add a0, a1, a0
-; CHECK-NEXT:    andi a1, a0, 255
-; CHECK-NEXT:    li a0, 8
-; CHECK-NEXT:    bltu a2, a1, .LBB4_2
+; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    bltu a2, a0, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB4_2:
+; CHECK-NEXT:    li a0, 8
 ; CHECK-NEXT:    ret
   %add = add i8 %b, %a
   %cmp = icmp ugt i8 %add, %limit
@@ -106,13 +111,14 @@ define i32 @overflow_add_const_limit(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: overflow_add_const_limit:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    add a0, a1, a0
-; CHECK-NEXT:    andi a1, a0, 255
-; CHECK-NEXT:    li a2, 128
-; CHECK-NEXT:    li a0, 8
-; CHECK-NEXT:    bltu a2, a1, .LBB5_2
+; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    li a1, 128
+; CHECK-NEXT:    bltu a1, a0, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB5_2:
+; CHECK-NEXT:    li a0, 8
 ; CHECK-NEXT:    ret
   %add = add i8 %b, %a
   %cmp = icmp ugt i8 %add, -128
@@ -124,13 +130,14 @@ define i32 @overflow_add_positive_const_limit(i8 zeroext %a) {
 ; CHECK-LABEL: overflow_add_positive_const_limit:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a1, a0, 56
-; CHECK-NEXT:    li a2, -1
-; CHECK-NEXT:    li a0, 8
-; CHECK-NEXT:    blt a1, a2, .LBB6_2
+; CHECK-NEXT:    srai a0, a0, 56
+; CHECK-NEXT:    li a1, -1
+; CHECK-NEXT:    blt a0, a1, .LBB6_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB6_2:
+; CHECK-NEXT:    li a0, 8
 ; CHECK-NEXT:    ret
   %cmp = icmp slt i8 %a, -1
   %res = select i1 %cmp, i32 8, i32 16
@@ -140,13 +147,13 @@ define i32 @overflow_add_positive_const_limit(i8 zeroext %a) {
 define i32 @unsafe_add_underflow(i8 zeroext %a) {
 ; CHECK-LABEL: unsafe_add_underflow:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mv a1, a0
-; CHECK-NEXT:    li a2, 1
-; CHECK-NEXT:    li a0, 8
-; CHECK-NEXT:    beq a1, a2, .LBB7_2
+; CHECK-NEXT:    li a1, 1
+; CHECK-NEXT:    beq a0, a1, .LBB7_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB7_2:
+; CHECK-NEXT:    li a0, 8
 ; CHECK-NEXT:    ret
   %cmp = icmp eq i8 %a, 1
   %res = select i1 %cmp, i32 8, i32 16
@@ -156,12 +163,12 @@ define i32 @unsafe_add_underflow(i8 zeroext %a) {
 define i32 @safe_add_underflow(i8 zeroext %a) {
 ; CHECK-LABEL: safe_add_underflow:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mv a1, a0
-; CHECK-NEXT:    li a0, 8
-; CHECK-NEXT:    beqz a1, .LBB8_2
+; CHECK-NEXT:    beqz a0, .LBB8_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB8_2:
+; CHECK-NEXT:    li a0, 8
 ; CHECK-NEXT:    ret
   %cmp = icmp eq i8 %a, 0
   %res = select i1 %cmp, i32 8, i32 16
@@ -171,13 +178,14 @@ define i32 @safe_add_underflow(i8 zeroext %a) {
 define i32 @safe_add_underflow_neg(i8 zeroext %a) {
 ; CHECK-LABEL: safe_add_underflow_neg:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a1, a0, -2
-; CHECK-NEXT:    li a2, 251
-; CHECK-NEXT:    li a0, 8
-; CHECK-NEXT:    bltu a1, a2, .LBB9_2
+; CHECK-NEXT:    addi a0, a0, -2
+; CHECK-NEXT:    li a1, 251
+; CHECK-NEXT:    bltu a0, a1, .LBB9_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB9_2:
+; CHECK-NEXT:    li a0, 8
 ; CHECK-NEXT:    ret
   %add = add i8 %a, -2
   %cmp = icmp ult i8 %add, -5
@@ -189,13 +197,14 @@ define i32 @overflow_sub_negative_const_limit(i8 zeroext %a) {
 ; CHECK-LABEL: overflow_sub_negative_const_limit:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a1, a0, 56
-; CHECK-NEXT:    li a2, -1
-; CHECK-NEXT:    li a0, 8
-; CHECK-NEXT:    blt a1, a2, .LBB10_2
+; CHECK-NEXT:    srai a0, a0, 56
+; CHECK-NEXT:    li a1, -1
+; CHECK-NEXT:    blt a0, a1, .LBB10_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB10_2:
+; CHECK-NEXT:    li a0, 8
 ; CHECK-NEXT:    ret
   %cmp = icmp slt i8 %a, -1
   %res = select i1 %cmp, i32 8, i32 16
@@ -206,13 +215,14 @@ define i32 @overflow_sub_negative_const_limit(i8 zeroext %a) {
 define i32 @sext_sub_underflow(i8 zeroext %a) {
 ; CHECK-LABEL: sext_sub_underflow:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a1, a0, -6
-; CHECK-NEXT:    li a2, -6
-; CHECK-NEXT:    li a0, 8
-; CHECK-NEXT:    bltu a2, a1, .LBB11_2
+; CHECK-NEXT:    addi a0, a0, -6
+; CHECK-NEXT:    li a1, -6
+; CHECK-NEXT:    bltu a1, a0, .LBB11_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB11_2:
+; CHECK-NEXT:    li a0, 8
 ; CHECK-NEXT:    ret
   %sub = add i8 %a, -6
   %cmp = icmp ugt i8 %sub, -6
@@ -223,12 +233,12 @@ define i32 @sext_sub_underflow(i8 zeroext %a) {
 define i32 @safe_sub_underflow(i8 zeroext %a) {
 ; CHECK-LABEL: safe_sub_underflow:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mv a1, a0
-; CHECK-NEXT:    li a0, 16
-; CHECK-NEXT:    beqz a1, .LBB12_2
+; CHECK-NEXT:    beqz a0, .LBB12_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 8
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB12_2:
+; CHECK-NEXT:    li a0, 16
 ; CHECK-NEXT:    ret
   %cmp.not = icmp eq i8 %a, 0
   %res = select i1 %cmp.not, i32 16, i32 8
@@ -238,13 +248,14 @@ define i32 @safe_sub_underflow(i8 zeroext %a) {
 define i32 @safe_sub_underflow_neg(i8 zeroext %a) {
 ; CHECK-LABEL: safe_sub_underflow_neg:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a1, a0, -4
-; CHECK-NEXT:    li a2, 250
-; CHECK-NEXT:    li a0, 8
-; CHECK-NEXT:    bltu a2, a1, .LBB13_2
+; CHECK-NEXT:    addi a0, a0, -4
+; CHECK-NEXT:    li a1, 250
+; CHECK-NEXT:    bltu a1, a0, .LBB13_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB13_2:
+; CHECK-NEXT:    li a0, 8
 ; CHECK-NEXT:    ret
   %sub = add i8 %a, -4
   %cmp = icmp ugt i8 %sub, -6
@@ -256,13 +267,14 @@ define i32 @safe_sub_underflow_neg(i8 zeroext %a) {
 define i32 @sext_sub_underflow_neg(i8 zeroext %a) {
 ; CHECK-LABEL: sext_sub_underflow_neg:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a1, a0, -4
-; CHECK-NEXT:    li a2, -3
-; CHECK-NEXT:    li a0, 8
-; CHECK-NEXT:    bltu a1, a2, .LBB14_2
+; CHECK-NEXT:    addi a0, a0, -4
+; CHECK-NEXT:    li a1, -3
+; CHECK-NEXT:    bltu a0, a1, .LBB14_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB14_2:
+; CHECK-NEXT:    li a0, 8
 ; CHECK-NEXT:    ret
   %sub = add i8 %a, -4
   %cmp = icmp ult i8 %sub, -3