From 759aeb6122d73422b4d8e35995d4bcf03eaf253c Mon Sep 17 00:00:00 2001 From: Zaara Syeda Date: Tue, 10 Sep 2024 12:59:39 -0400 Subject: [PATCH 1/3] [PowerPC] Fix assert exposed by PR 95931 in LowerBITCAST Hit Assertion failed: Num < NumOperands && "Invalid child # of SDNode!" Check opcode and value type before calling getOperand. --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 9 +++++---- llvm/test/CodeGen/PowerPC/f128-bitcast.ll | 22 +++++++++++++++++++++ 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index fd03eeba91149..ed63b50cd8eee 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -9470,12 +9470,13 @@ SDValue PPCTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const { SDLoc dl(Op); SDValue Op0 = Op->getOperand(0); + if ((Op.getValueType() != MVT::f128) || (Op0.getOpcode() != ISD::BUILD_PAIR)) + return SDValue(); + SDValue Lo = Op0.getOperand(0); SDValue Hi = Op0.getOperand(1); - - if ((Op.getValueType() != MVT::f128) || - (Op0.getOpcode() != ISD::BUILD_PAIR) || (Lo.getValueType() != MVT::i64) || - (Hi.getValueType() != MVT::i64) || !Subtarget.isPPC64()) + if ((Lo.getValueType() != MVT::i64) || (Hi.getValueType() != MVT::i64) || + !Subtarget.isPPC64()) return SDValue(); if (!Subtarget.isLittleEndian()) diff --git a/llvm/test/CodeGen/PowerPC/f128-bitcast.ll b/llvm/test/CodeGen/PowerPC/f128-bitcast.ll index ffbfbd0c64ff3..649ca59fe9ae0 100644 --- a/llvm/test/CodeGen/PowerPC/f128-bitcast.ll +++ b/llvm/test/CodeGen/PowerPC/f128-bitcast.ll @@ -86,3 +86,25 @@ entry: ret i64 %1 } +define <4 x i32> @test(i512 %a) { +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mtvsrdd v2, r4, r3 +; CHECK-NEXT: blr +; +; CHECK-BE-LABEL: test: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: mtvsrdd v2, r9, r10 +; CHECK-BE-NEXT: blr +; +; CHECK-P8-LABEL: test: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mtfprd f0, r3 +; CHECK-P8-NEXT: mtfprd f1, r4 +; CHECK-P8-NEXT: xxmrghd v2, vs1, vs0 +; CHECK-P8-NEXT: blr +entry: + %0 = trunc i512 %a to i128 + %1 = bitcast i128 %0 to <4 x i32> + ret <4 x i32> %1 +} From 5fc0f2cf3fadbed1eaa9fc1903b473b5d915bac0 Mon Sep 17 00:00:00 2001 From: Zaara Syeda Date: Tue, 10 Sep 2024 14:05:30 -0400 Subject: [PATCH 2/3] Address review comments --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index ed63b50cd8eee..d9847a21489e6 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -9470,13 +9470,13 @@ SDValue PPCTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const { SDLoc dl(Op); SDValue Op0 = Op->getOperand(0); - if ((Op.getValueType() != MVT::f128) || (Op0.getOpcode() != ISD::BUILD_PAIR)) + if (!Subtarget.isPPC64() || (Op0.getOpcode() != ISD::BUILD_PAIR) || + (Op.getValueType() != MVT::f128)) return SDValue(); SDValue Lo = Op0.getOperand(0); SDValue Hi = Op0.getOperand(1); - if ((Lo.getValueType() != MVT::i64) || (Hi.getValueType() != MVT::i64) || - !Subtarget.isPPC64()) + if ((Lo.getValueType() != MVT::i64) || (Hi.getValueType() != MVT::i64)) return SDValue(); if (!Subtarget.isLittleEndian()) From 1334780fc235a4435beb8854230180dd733bf727 Mon Sep 17 00:00:00 2001 From: Zaara Syeda Date: Tue, 10 Sep 2024 14:12:30 -0400 Subject: [PATCH 3/3] Address review --- llvm/test/CodeGen/PowerPC/f128-bitcast.ll | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/PowerPC/f128-bitcast.ll b/llvm/test/CodeGen/PowerPC/f128-bitcast.ll index 649ca59fe9ae0..55ba3cb1e0538 100644 --- a/llvm/test/CodeGen/PowerPC/f128-bitcast.ll +++ b/llvm/test/CodeGen/PowerPC/f128-bitcast.ll @@ -86,18 +86,18 @@ entry: ret i64 %1 } -define <4 x i32> @test(i512 %a) { -; CHECK-LABEL: test: +define <4 x i32> @truncBitcast(i512 %a) { +; CHECK-LABEL: truncBitcast: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: mtvsrdd v2, r4, r3 ; CHECK-NEXT: blr ; -; CHECK-BE-LABEL: test: +; CHECK-BE-LABEL: truncBitcast: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrdd v2, r9, r10 ; CHECK-BE-NEXT: blr ; -; CHECK-P8-LABEL: test: +; CHECK-P8-LABEL: truncBitcast: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mtfprd f0, r3 ; CHECK-P8-NEXT: mtfprd f1, r4