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llvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passesCovers the InstCombine, InstSimplify and AggressiveInstCombine passesmissed-optimization
Description
fold other select to logical and/or if either icmp predicate is free to invert
https://alive2.llvm.org/ce/z/aSYXfg
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define i32 @src_or(i32 %x, i32 %y, i32 %z, i1 %cmp1) {
#0:
%cmp2 = icmp eq i32 %z, 0
%sel1 = select i1 %cmp1, i32 %x, i32 %y
%sel2 = select i1 %cmp2, i32 %sel1, i32 %x
ret i32 %sel2
}
=>
define i32 @tgt_or(i32 %x, i32 %y, i32 %z, i1 %cmp1) {
#0:
%cmp2_inv = icmp ne i32 %z, 0
%sel1 = select i1 %cmp2_inv, i1 1, i1 %cmp1
%sel2 = select i1 %sel1, i32 %x, i32 %y
ret i32 %sel2
}
Transformation seems to be correct!
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define i32 @src_and(i32 %x, i32 %y, i32 %z, i1 %cmp1) {
#0:
%cmp2 = icmp eq i32 %z, 0
%sel1 = select i1 %cmp2, i32 %x, i32 %y
%sel2 = select i1 %cmp1, i32 %sel1, i32 %x
ret i32 %sel2
}
=>
define i32 @tgt_and(i32 %x, i32 %y, i32 %z, i1 %cmp1) {
#0:
%cmp2_inv = icmp ne i32 %z, 0
%sel1 = select i1 %cmp1, i1 %cmp2_inv, i1 0
%sel2 = select i1 %sel1, i32 %y, i32 %x
ret i32 %sel2
}
Transformation seems to be correct!
dtcxzyw
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llvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passesCovers the InstCombine, InstSimplify and AggressiveInstCombine passesmissed-optimization