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LLVM MCA does not match uops.info/Agner measurements for Icelake add/mul #81504

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SeeSpring opened this issue Feb 12, 2024 · 1 comment
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backend:X86 Scheduler Models Accuracy of X86 scheduler models

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@SeeSpring
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According to uops.info and Agner these instructions all have a throughput of 1 on Icelake and run on port 0

vaddps	%zmm0, %zmm1, %zmm2
vmulps	%zmm0, %zmm1, %zmm2

llvm-mca claims they have a RThroughput of 0.50 and p05
Godbolt of llvm-mca

Version
LLVM (http://llvm.org/):
  LLVM version 19.0.0git
  Optimized build.
  Default target: x86_64-unknown-linux-gnu
  Host CPU: cascadelake

  Registered Targets:
    aarch64     - AArch64 (little endian)
    aarch64_32  - AArch64 (little endian ILP32)
    aarch64_be  - AArch64 (big endian)
    amdgcn      - AMD GCN GPUs
    arm         - ARM
    arm64       - ARM64 (little endian)
    arm64_32    - ARM64 (little endian ILP32)
    armeb       - ARM (big endian)
    avr         - Atmel AVR Microcontroller
    bpf         - BPF (host endian)
    bpfeb       - BPF (big endian)
    bpfel       - BPF (little endian)
    dxil        - DirectX Intermediate Language
    hexagon     - Hexagon
    lanai       - Lanai
    loongarch32 - 32-bit LoongArch
    loongarch64 - 64-bit LoongArch
    m68k        - Motorola 68000 family
    mips        - MIPS (32-bit big endian)
    mips64      - MIPS (64-bit big endian)
    mips64el    - MIPS (64-bit little endian)
    mipsel      - MIPS (32-bit little endian)
    msp430      - MSP430 [experimental]
    nvptx       - NVIDIA PTX 32-bit
    nvptx64     - NVIDIA PTX 64-bit
    ppc32       - PowerPC 32
    ppc32le     - PowerPC 32 LE
    ppc64       - PowerPC 64
    ppc64le     - PowerPC 64 LE
    r600        - AMD GPUs HD2XXX-HD6XXX
    riscv32     - 32-bit RISC-V
    riscv64     - 64-bit RISC-V
    sparc       - Sparc
    sparcel     - Sparc LE
    sparcv9     - Sparc V9
    spirv       - SPIR-V Logical
    spirv32     - SPIR-V 32-bit
    spirv64     - SPIR-V 64-bit
    systemz     - SystemZ
    thumb       - Thumb
    thumbeb     - Thumb (big endian)
    ve          - VE
    wasm32      - WebAssembly 32-bit
    wasm64      - WebAssembly 64-bit
    x86         - 32-bit X86: Pentium-Pro and above
    x86-64      - 64-bit X86: EM64T and AMD64
    xcore       - XCore
Compiler returned: 0
@RKSimon RKSimon self-assigned this Feb 12, 2024
@RKSimon RKSimon added backend:X86 Scheduler Models Accuracy of X86 scheduler models and removed new issue labels Feb 12, 2024
@RKSimon
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RKSimon commented Feb 12, 2024

Thanks! The Icelake model was branched from Skylake and has never been exhaustively cleaned up or tested with llvm-exegesis

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