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Backport [RISCV] Graduate Zicond to non-experimental (#79811) (#80018)
The Zicond extension was ratified in the last few months, with no changes that affect the LLVM implementation. Although there's surely more tuning that could be done about when to select Zicond or not, there are no known correctness issues. Therefore, we should mark support as non-experimental. (cherry-picked from commit d833b9d)
1 parent a2d4a4c commit fe2fca3

18 files changed

+60
-68
lines changed

‎clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ __attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
3939
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,-relax,-zbb,-zfa" }
4040
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
4141
// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
42-
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
42+
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
4343
// Make sure we append negative features if we override the arch
4444
// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
4545
// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }

‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -764,6 +764,14 @@
764764
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICNTR-EXT %s
765765
// CHECK-ZICNTR-EXT: __riscv_zicntr 2000000{{$}}
766766

767+
// RUN: %clang --target=riscv32 \
768+
// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
769+
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
770+
// RUN: %clang --target=riscv64 \
771+
// RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \
772+
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
773+
// CHECK-ZICOND-EXT: __riscv_zicond 1000000{{$}}
774+
767775
// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32izicsr2p0 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICSR-EXT %s
@@ -1332,14 +1340,6 @@
13321340
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
13331341
// CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}}
13341342

1335-
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1336-
// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
1337-
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
1338-
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1339-
// RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \
1340-
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
1341-
// CHECK-ZICOND-EXT: __riscv_zicond 1000000{{$}}
1342-
13431343
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
13441344
// RUN: -march=rv32i_zimop0p1 -x c -E -dM %s \
13451345
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s

‎llvm/docs/RISCVUsage.rst

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,7 @@ on support follow.
130130
``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__)
131131
``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__)
132132
``Zicntr`` (`See Note <#riscv-i2p1-note>`__)
133+
``Zicond`` Supported
133134
``Zicsr`` (`See Note <#riscv-i2p1-note>`__)
134135
``Zifencei`` (`See Note <#riscv-i2p1-note>`__)
135136
``Zihintntl`` Supported
@@ -234,9 +235,6 @@ The primary goal of experimental support is to assist in the process of ratifica
234235
``experimental-zicfilp``, ``experimental-zicfiss``
235236
LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__.
236237

237-
``experimental-zicond``
238-
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1>`__.
239-
240238
``experimental-ztso``
241239
LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware.
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‎llvm/docs/ReleaseNotes.rst

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@@ -181,6 +181,7 @@ Changes to the RISC-V Backend
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specification.
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* The Smepmp 1.0 extension is now supported.
183183
* ``-mcpu=sifive-p670`` was added.
184+
* Support for the Zicond extension is no longer experimental.
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185186
Changes to the WebAssembly Backend
186187
----------------------------------

‎llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
128128
{"zicclsm", {1, 0}},
129129
{"ziccrse", {1, 0}},
130130
{"zicntr", {2, 0}},
131+
{"zicond", {1, 0}},
131132
{"zicsr", {2, 0}},
132133
{"zifencei", {2, 0}},
133134
{"zihintntl", {1, 0}},
@@ -200,8 +201,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
200201
{"zicfilp", {0, 4}},
201202
{"zicfiss", {0, 4}},
202203

203-
{"zicond", {1, 0}},
204-
205204
{"zimop", {0, 1}},
206205

207206
{"ztso", {0, 1}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 1 addition & 1 deletion
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@@ -72,7 +72,7 @@ def FeatureStdExtZicntr
7272
[FeatureStdExtZicsr]>;
7373

7474
def FeatureStdExtZicond
75-
: SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true",
75+
: SubtargetFeature<"zicond", "HasStdExtZicond", "true",
7676
"'Zicond' (Integer Conditional Operations)">;
7777
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
7878
AssemblerPredicate<(all_of FeatureStdExtZicond),

‎llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td

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@@ -8,8 +8,6 @@
88
//
99
// This file describes the RISC-V instructions from the standard Integer
1010
// Conditional operations extension (Zicond).
11-
// This version is still experimental as the 'Zicond' extension hasn't been
12-
// ratified yet. It is based on v1.0-rc1 of the specification.
1311
//
1412
//===----------------------------------------------------------------------===//
1513

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -84,7 +84,7 @@
8484
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
8585
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
8686
; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s
87-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
87+
; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
8888
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s
8989
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s
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; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
@@ -186,7 +186,7 @@
186186
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
187187
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
188188
; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
189-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
189+
; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
190190
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s
191191
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s
192192
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s

‎llvm/test/CodeGen/RISCV/cmov-branch-opt.ll

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@@ -3,13 +3,13 @@
33
; RUN: | FileCheck -check-prefix=NOCMOV %s
44
; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefixes=CMOV,CMOV-NOZICOND %s
6-
; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c,+experimental-zicond -verify-machineinstrs < %s \
6+
; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c,+zicond -verify-machineinstrs < %s \
77
; RUN: | FileCheck -check-prefixes=CMOV,CMOV-ZICOND %s
88
; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt -verify-machineinstrs < %s \
99
; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND %s
1010
; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+c -verify-machineinstrs < %s \
1111
; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND %s
12-
; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+experimental-zicond -verify-machineinstrs < %s \
12+
; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+zicond -verify-machineinstrs < %s \
1313
; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-ZICOND %s
1414

1515
; The conditional move optimization in sifive-p450 requires that only a

‎llvm/test/CodeGen/RISCV/condbinops.ll

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@@ -3,8 +3,8 @@
33
; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
44
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
55
; RUN: llc -mtriple=riscv64 -mattr=+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
6-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
7-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
6+
; RUN: llc -mtriple=riscv32 -mattr=+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
7+
; RUN: llc -mtriple=riscv64 -mattr=+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
88

99
define i32 @shl32(i32 %x, i32 %y, i1 %c) {
1010
; RV32I-LABEL: shl32:

‎llvm/test/CodeGen/RISCV/condops.ll

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@@ -3,8 +3,8 @@
33
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV64I
44
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
55
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
6-
; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
7-
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
6+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
7+
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
88

99
define i64 @zero1(i64 %rs1, i1 zeroext %rc) {
1010
; RV32I-LABEL: zero1:

‎llvm/test/CodeGen/RISCV/select-binop-identity.ll

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@@ -7,9 +7,9 @@
77
; RUN: | FileCheck -check-prefix=SFB64 %s
88
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops -verify-machineinstrs < %s \
99
; RUN: | FileCheck -check-prefixes=VTCONDOPS64 %s
10-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond -verify-machineinstrs < %s \
10+
; RUN: llc -mtriple=riscv32 -mattr=+zicond -verify-machineinstrs < %s \
1111
; RUN: | FileCheck -check-prefixes=RV32,ZICOND,ZICOND32 %s
12-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond -verify-machineinstrs < %s \
12+
; RUN: llc -mtriple=riscv64 -mattr=+zicond -verify-machineinstrs < %s \
1313
; RUN: | FileCheck -check-prefixes=ZICOND,ZICOND64 %s
1414

1515
; InstCombine canonicalizes (c ? x | y : x) to (x | (c ? y : 0)) similar for

‎llvm/test/CodeGen/RISCV/select.ll

Lines changed: 2 additions & 2 deletions
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@@ -2,8 +2,8 @@
22
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32IM %s
33
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IM %s
44
; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IMXVTCONDOPS %s
5-
; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s
6-
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s
5+
; RUN: llc -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s
6+
; RUN: llc -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s
77

88
define i16 @select_xor_1(i16 %A, i8 %cond) {
99
; RV32IM-LABEL: select_xor_1:

‎llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
; RUN: | FileCheck -check-prefix=NOSFB %s
44
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+zbb -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefixes=SFB,NOZICOND,RV64SFB %s
6-
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+experimental-zicond,+zbb \
6+
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+zicond,+zbb \
77
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=SFB,ZICOND %s
88
; RUN: llc -mtriple=riscv32 -mcpu=sifive-e76 -mattr=+zbb -verify-machineinstrs < %s \
99
; RUN: | FileCheck -check-prefixes=SFB,NOZICOND,RV32SFB %s

‎llvm/test/CodeGen/RISCV/xaluo.ll

Lines changed: 2 additions & 2 deletions
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@@ -3,8 +3,8 @@
33
; RUN: llc < %s -mtriple=riscv64 -mattr=+m -verify-machineinstrs | FileCheck %s --check-prefix=RV64
44
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zba -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZBA
55
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zba -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZBA
6-
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZICOND
7-
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZICOND
6+
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZICOND
7+
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZICOND
88

99
;
1010
; Get the actual value of the overflow bit.

‎llvm/test/MC/RISCV/rv32zicond-invalid.s

Lines changed: 2 additions & 2 deletions
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@@ -1,5 +1,5 @@
1-
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
2-
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
1+
# RUN: not llvm-mc -triple riscv32 -mattr=+zicond < %s 2>&1 | FileCheck %s
2+
# RUN: not llvm-mc -triple riscv64 -mattr=+zicond < %s 2>&1 | FileCheck %s
33

44
# Use of operand modifier on register name
55
czero.eqz t1, %lo(t2), t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction

‎llvm/test/MC/RISCV/rv32zicond-valid.s

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
1-
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicond -show-encoding \
1+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicond -show-encoding \
22
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
3-
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicond -show-encoding \
3+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicond -show-encoding \
44
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
5-
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicond < %s \
6-
# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
5+
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicond < %s \
6+
# RUN: | llvm-objdump --mattr=+zicond -d -r - \
77
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
8-
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicond < %s \
9-
# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
8+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicond < %s \
9+
# RUN: | llvm-objdump --mattr=+zicond -d -r - \
1010
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
1111

1212
# CHECK-ASM-AND-OBJ: czero.eqz t0, a3, ra

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